CN1667427A - Chip testing method and relevant apparatus - Google Patents
Chip testing method and relevant apparatus Download PDFInfo
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- CN1667427A CN1667427A CNA2005100672480A CN200510067248A CN1667427A CN 1667427 A CN1667427 A CN 1667427A CN A2005100672480 A CNA2005100672480 A CN A2005100672480A CN 200510067248 A CN200510067248 A CN 200510067248A CN 1667427 A CN1667427 A CN 1667427A
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Abstract
The invention relates to a chip detetion method and related apparatus, wherein, the method comprises following steps: setting internal circuit related circuit in chip; making emission and reception circuit by-passing and directly outputting circuit output signal to input circuit to definitely identify if output / input circuit and emission / reception circuit are normal, when detecting chips.
Description
Technical field
The invention provides a kind of chip detecting method and relevant apparatus, refer in particular in a kind of AFE (analog front end) (analogue front-end) that can differentiate chip separately each digital circuit/mimic channel whether normal chip detecting method and relevant apparatus.
Background technology
Electronic circuit is the most important hardware foundation of modernized information society; Along with the development of semiconductor information industry, the electronic circuit of multiple difference in functionality all can be integrated in the same chip, makes one chip just can have complicated function.
In order to ensure the normal operation of chip energy, it is necessary that the chip of making is tested.Yet existing chip testing technology focuses on the allomeric function of chip mostly.The most basic test is to predict chip due reaction under specific circumstances according to the specification and the function of chip design earlier, sends out which signal as responding after chip reception/execution signal specific/instruction.Next, just can make chip actual reception/this kind of execution signal/instruction, and check whether whether the actual signal that sends of responding of chip meets expection, meet the specification and the function of original design with the actual operation of understanding chip.
Though above-mentioned known measuring technology can judge whether the allomeric function of a chip finished product is normal, when chip can't normal operation, this kind measuring technology just can't determine in the chip it is which partly fails normal operation on earth.As previously mentioned, all be integrated with multiple complicated electronic circuit in the modern chip, if can not know the part of orienting fault failures in the chip, the Test Engineer of chip manufacturer (vendor) just is difficult to find out not normal reason, also just can't positively be improved.For instance, Xian Dai chip all has the output/input circuit of numeral and the emission/receiving circuit of simulation mostly; The signal that chip carries out will sending after the digital processing can be converted to specific format via output circuit, be fit to the digital output signal of output, drives practically with radiating circuit and sends this output signal.The signal that is sent to chip is then received by the receiving circuit in the chip earlier and detects, and carries out inverse transform by input circuit again, to form the digital signal that chip can be understood/handle.When chip is tested, if the actual signal that sends of chip do not meet the due reaction of chip, might be that digital input/output circuitry can't normal operation, also might be the malfunction of analog transmissions/receiving circuit.Yet because known measuring technology is only observed, the output of the integral body of comparable chip, just can not orient definitely is that any circuit is not normal on earth, and this also makes chip manufacturer be difficult to improve effectively its chip design or production technology.
Summary of the invention
Therefore, purpose of the present invention is exactly to propose a kind of preferable chip testing technology, to overcome the shortcoming of known technology, allow chip manufacturer can be expressly understood that comparatively whether the circuit running of different piece in the chip is normal, orients the not normal position of chip fast and also positively improved.
Basically, the present invention is the interlock circuit of built-in inner looping in chip (inner loop-back), so that optionally some circuit in bypass/isolating chip and the function of directly testing other circuit when test chip, and intersect with this and to contrast circuit part not normal in the chip.For instance, as previously mentioned, meeting is gone into AFE (analog front end) (AFE, Analogue Front End) with the output that numeral output/input circuit and analog transmissions/receiving circuit form a chip in the chip; If technology of the present invention will be implemented in this AFE (analog front end), just can between output/input circuit, set up controllable inner looping interlock circuit, as a multi-channel conversion circuit, be to transfer to radiating circuit or directly transfer to input circuit by inner looping so that switch the output signal of output circuit.When test chip, can turn-off this inner looping earlier, allow chip outside chip, send signal via output circuit one radiating circuit.Behind the signal that receiving chip sends,, just might be that output circuit or radiating circuit can't normal operations if this signal does not meet expection.In order to determine that further not normal part, the present invention just can make inner looping connect running, allow the signal of chip directly transfer to input circuit by output circuit.Perhaps, the signal that chip sends is normal but receive the signal of coming in problem is arranged, and whether can also technology of the present invention get rid of this moment is that receiving circuit is out of joint.In the equivalence,, also just can test the operation situation of output circuit separately because this inner looping test makes the signal bypass in radiating circuit (without radiating circuit).If confirm that the running of output circuit is normal, just can intersect that to contrast part not normal in the chip be radiating circuit.
In preferred embodiment of the present invention, technology of the present invention applies to chipset (chipset), as the advanced interconnection technique (SATA of serial in the chipset, be serial ATA, ATA is Advanced TechnologyAttachment) AFE (analog front end) under the specification, with the interface of the advanced interconnection technique of serial in the test chip group (SATA).As is known to the person skilled in the art, chipset in the computer system can be realized out the interface of multiple different size in one chip, as peripheral communication interconnect (PCI, Peripheral CommunicationInterconnect), intelligent electronic device (IDE, Intelligent Drive Electronic), the specification interface of the advanced interconnection technique of serial (SATA) etc., with the peripherals that connects the various interface specification (as auxiliary insert card, hard disk and memory storage etc.), make these devices can be via chipset with computer system in central processing unit, memory transactions data/signal.Wherein, the interface of the advanced interconnection technique of serial (SATA) belongs to high-speed interface, come transceive data with quite high data transmission road, thus its export into AFE (analog front end) just more need preferable, clearer and more definite circuit debug/measuring technology, guarantee its running normally.And technology of the present invention just can be applied to the interface circuit of the advanced interconnection technique of serial, the each several part circuit in the AFE (analog front end) of this interface circuit and interlock circuit are carried out the testing of circuit.
When chipset is carried out chip testing, the present invention also can go into solder joint (IO pad) with the output of other specification interfaces in the chipset respectively with the operation situation of different piece in the chip and be exported, export to outside the chip as when testing the interface of the advanced interconnection technique of serial, the operation situation separately of some internal circuit being gone into solder joint by the output of intelligent electronic device (IDE) interface individually, whether the running of circuit conforms with expection further to clarify separately, also helps the clearly location of not normal part.
Description of drawings
Fig. 1 is the function block schematic diagram of the invention process in a chip.
The synoptic diagram that Fig. 2 to Fig. 4 tests Fig. 1 chips for the present invention.
The synoptic diagram that Fig. 5 generally operates for Fig. 1 chips.
The main element symbol description
10 chips, 12 governor circuits
14,16 interface circuits, 18 interface control modules
20 coding modules, 22 output circuits
24 radiating circuits, 28 input circuits
30 receiving circuits, 32 whistles suppress pre-amplification circuit
34 restoring circuits, 36 change-over circuits
38 buffer modules, 40 test signal generation modules
42 check module 46 handover modules
48,50 multi-channel conversion circuits, 52 input ports
54, solder joint 58 external loop circuits are gone in 56 outputs
Sh signal Se coded signal
Tx output signal Txp-Txn, Rxp-Rxn signal
Rx received signal Rx_ready is equipped with just signal
St test signal Sp test pattern signal
SQr suppresses indicator signal with reference to indicator signal SQ whistle
SQi indicator signal TR check result
T_mode, L_mode control signal
Tx_valid enables signal
The RxD data-signal
The D1-D2 signal
Embodiment
Please refer to Fig. 1, Fig. 1 is the synoptic diagram that the present invention is implemented in advanced interconnection technique (SATA) interface of serial of a chipset; Chip 10 among Fig. 1 promptly can be a chipset.Can be provided with a governor circuit 12 and a plurality of interface circuit in the chip 10 as chipset; Among Fig. 1 with two interface circuits 14,16 as representative.Wherein, governor circuit 12 is used for the allomeric function of main control chip 10, and each interface circuit 14,16 promptly is used for the interface of specific standard in the support chip group; For instance, interface circuit 14 can be the interface of supporting intelligent electronic device (IDE) specification, allows chip 10 can connect through interface circuit 14 thus, the peripherals of management intelligent electronic device (IDE) specification; In the present invention, chip 10 also can be through interface circuit 10 thus and will be tested the interface that coherent signal is connected to the intelligent electronic device.Interface circuit 16 can be the interface of supporting advanced interconnection technique (SATA) specification of serial; Chip 10 can connect, manage the various peripherals under advanced interconnection technique (SATA) specification of serial by this interface circuit.12 of governor circuits are the exchanges data between the interface of these specifications of master control and central processing unit, storer comprehensively.As shown in Figure 1, can be provided with a plurality of outputs on the chip 10 and go into solder joint (IO pad) 54,56 and 58 etc., just the pin (pin) that is connected with external circuitry of chip 10; Governor circuit 12, interface circuit 14 and interface circuit 16 can be respectively with each export into solder joint 58,54 and 56 and with extraneous swap data/signal.
In order to realize the interface of advanced interconnection technique (SATA) specification of serial, can be provided with an interface control module 18, a coding module 20, an output circuit 22, a radiating circuit 24, a receiving circuit 30, an input circuit 28, a buffer module 38 and a whistle in the interface circuit 16 and suppress pre-amplification circuit 32.Interface control module 18 is used for the running of master control interface circuit 16.Coding module 20 can be one 8 coding modules that change 10 (8b/10b), and 10 coded signal Se that it can be received one 8 signal Sh and be converted into a correspondence by 8 buses are again by one 10 buses outputs.22 of output circuits can be parallel serial (parallel-to-serial) circuit that changes, and it can be received 10 signal by 10 buses, and are converted into the output signal Tx of serial (serial).Radiating circuit 24 can be a differential amplifier circuit, be used for output signal Tx change/drive into differential wave to (pair ofdifferential signals) Txp, Txn, and this differential wave to just going into solder joint 56 and be issued to outside the chip via output.This radiating circuit 24 can be enabled signal Tx_valid by one and control it and enable or forbid.Relatively, 30 of receiving circuits can be a differential receiving circuit, and the differential wave that the external world transfers to chip 10 can be detected by receiving circuit 30 Rxp, Rxn, to produce corresponding received signal Rx.Can be provided with a restoring circuit 34 and a change-over circuit 36 in the input circuit 28.Restoring circuit 34 can be one data/clock recovery (data/clock recovery) circuit, and it has an input port 52; Restoring circuit 34 input port 52 thus receives serial signal (as received signal Rx), and analyzes the data-signal RxD and corresponding clock that this signal carries in the serial signal thus; After locking default fundamental frequency clock smoothly, can also send once being equipped with signal Rx_ready.Change-over circuit 36 then can be converted to 10 parallel signal D1 (inverse transform of output circuit 22 just) with each of serial among the data-signal RxD, and exports it to buffer module 38 via 10 bus.Buffer module 38 can be carried out elastic buffer (elastic buffering) and word alignment (word align) processing to signal D1.In addition, whistle suppress pre-amplification circuit (squelch pre-amplifier) but 32 detection signals to whether having occurred common mode (common mode) signal among Rxp, the Rxn, and produce a whistle accordingly and suppress (squelch) indicator signal SQ and come as indicator signal SQi, be used for representing receiving circuit 30 whether to have receiving differential signal right.
When interface circuit 16 is realized the interface of advanced interconnection technique (SATA) specifications of serials and when managing the peripherals of this specification, the instruction/data that is sent to peripherals can be encoded to 10 coded signal via coding module 20 with it earlier with the form of 8 signals, output circuit 22 via numeral is converted into serial output signal Tx again, and the radiating circuit 24 by simulation is driven to differential wave to Txp, Txn and the actual peripherals that is sent to then.Relatively, the differential wave that peripherals is sent to interface circuit 16 can be detected/be received as the received signal Rx of series form by receiving circuit 30 to Rxp, Rxn, the pre-amplification circuit 32 of whistle inhibition simultaneously also can produce corresponding whistle inhibition indicator signal SQ and be used as indicator signal SQi, represent bus between this interface circuit and peripherals be triggered (toggle) with indicator signal SQi, make interface circuit 16 can prepare to receive extraneous signal, and make input circuit 28, buffer module 38 begin to handle the input signal of input port 52.The input circuit 28 of numeral can analyze its serial data that carries and clock from signal Rx, and serial data is converted to 10 parallel signal D1; Signal D1 just can form signal D2, and this signal D2 just can be understood by interface control module 18 via the buffered of buffer module 38.Output circuit 22, radiating circuit 24, receiving circuit 30 (whistle suppresses pre-amplification circuit 32) and input circuit 28 also just form the AFE (analog front end) (AFE) of interface circuit 16.
In order in interface circuit 16, to realize measuring technology of the present invention, the present invention is had a multi-channel conversion circuit 48 in especially in interface circuit 16, this multi-channel conversion circuit 48 can receive the control of a control signal L_mode, with the input port 52 that optionally the output signal Tx or the received signal Rx of receiving circuit 30 of output circuit 22 is transferred to input circuit 28.When multi-channel conversion circuit 48 selections directly transfer to the input port of input circuit 28 with output signal Tx, also just can form the inner looping (inner loop-back) of test usefulness.Cooperate the test running of inner looping, also be provided with a test signal generation module 40, all die change pieces 46, an inspection module 42 and another multi-channel conversion circuit 50 in the interface circuit 16 in addition.Wherein, test signal generation module 40 can be accepted the control of a test pattern signal Sp, produces 10 bit parallel test signal St of different patterns (pattern).For instance, test pattern signal Sp can be one 4 signal, and when the content of test pattern signal Sp was a certain numerical value, test signal St was a certain preset content; When the content of test pattern signal Sp was another numerical value, test signal generation module 40 just can produce the test signal St of another kind of preset content.46 of handover modules are controlled by another control signal T_mode, optionally coded signal Se or test signal St are transferred to output circuit 22 according to control signal T_mode.Check that 42 of modules can compare the similarities and differences of test signal St and signal D2, and produce corresponding check result TR.In addition, the control of 50 of multi-channel conversion circuits and multi-channel conversion circuit 48 same suspension control signal L_mode, it optionally replaces whistle to suppress whistle that pre-amplification circuit 32 produced with another default reference indicator signal SQr and suppresses indicator signal SQ with as indicator signal SQi.
Please refer to Fig. 2 (and in the lump with reference to figure 1); Fig. 2 signal be exactly the situation of the present invention's interface circuit 16 when test chip 10 when carrying out the inner looping test.When chip operates under this kind test pattern (test mode), the present invention just can control test signal generation module 40 by test pattern signal Sp, and replace coded signal Se with test signal St via the switching of handover module 46, and this test signal St will be converted to output signal Tx via output circuit 22; Simultaneously, radiating circuit 24 can make its forbidding via the control of enabling signal Tx_valid and not act on, 48 of multiplexing modules can switch with output signal Tx via the control of control signal L_mode and replace received signal Rx, it is the input of input circuit 28 that output signal Tx directly is used as, this has also just formed inner looping, make that the path that data-signal flows is to input circuit 28 by output circuit 22 loops, the participation of having got rid of simulation receiving circuit 30/ radiating circuit 24 (that is to say, receiving circuit 30 can decommission, stop signal reception/detection).The output signal Tx that produces according to test signal St can form corresponding signal D2 via the processing of restoring circuit 34, change-over circuit 36, buffer module 38, and check that module 42 will comparison signal D2 and original test signal St, whether can meet the performance of expection and normal operation to verify " output circuit 22-input circuit 28-buffer module 38 " this inner looping.Check that module 42 can learn the signal that inner looping expection institute should produce according to original test signal St, compare with the signal D2 of inner looping institute reality generation again, just can verify whether the running of inner looping meets expection.And check that module 42 is checked, the result of contrast just may be output as check result TR.
When the switching with multi-channel conversion circuit 48 forms inner looping, multi-channel conversion circuit 50 among the present invention also can switch with default reference indicator signal SQr is used as indicator signal SQi, is the input signal of input circuit 28 so that circuit such as input circuit 28, buffer module 38 can correctly be used as output signal Tx.Because under the inner looping test pattern, receiving circuit 30, whistle suppress received signals veritably not of pre-amplification circuit 32, also can not produce correct whistle inhibition indicator signal so whistle suppresses pre-amplification circuit 32.Just as previously mentioned, interface circuit 16 will just can correctly make input circuit 28, buffer module 38 come into operation according to the triggering of indicator signal.Can normally carry out in order to make the inner looping test, the present invention's this moment will be used as indicator signal SQi with default reference indicator signal SQr, interface circuit 16 can be normally be used as the output signal Tx of inner looping be the signal that received of input circuit 28 and be handled.
In preferred embodiment of the present invention, check that the check result TR that module 42 produces can be deposited in the register of chip 10, and the Test Engineer of chip just can go into solder joint (as exporting solder joint 58) via other output and comes this check result of access.As is known to the person skilled in the art, the chip as chipset can be provided with a plurality of registers; The value of these registers can reflect the operating state and the parameter of chipset, and is used as the pipeline that to be chipset intercom mutually with other external circuitry.For instance, when normal operation, the value of certain register in the chipset can be gone into solder joint and be connected in central processing unit (or each peripherals) via specific output, is used for notifying its operation situation to central processing unit (peripherals).And during the chip testing in carrying out Fig. 2, chip 10 can not be connected in central processing unit and peripherals, the Test Engineer just can make and check that module 42 is deposited at the built-in register of chipset with check result TR this moment, and go into solder joint by the output of this register correspondence and come its check result of access, understand the situation of inner looping test.In like manner, when testing, the output that the operation situation of each several part circuit also can be used other interface circuits in the inner looping is gone into solder joint and is exported.For instance, as anticipating shown in Fig. 1, when the function of chip 10 performance chipsets, it was pin is gone in another interface circuit 14 employed outputs originally that solder joint 54 is gone in output.But when verifying the inner looping of interface circuit 16 in the test of carrying out Fig. 2, interface circuit 14 need not operate, the running result of each part circuit in the interface circuit 16, as test signal St, signal D1 and D2 etc., go into solder joint 54 with regard to the output of energy unnumbered interface circuit 14 and exported, allow the Test Engineer can utilize these signals to verify each partly operation situation of circuit.For instance, comparison signal D1 and D2 just can verify whether the running of buffer module 38 is normal.In addition, set during test the control signal L_mode of test pattern and T_mode (and enabling signal Tx_valid) also the register in the utilized chip 10 set, or on chip 10,, these control signals go into solder joint for being provided with special-purpose output, allow the Test Engineer set this two signals outward, the mode that the control test is carried out by chip.In addition, in the example of Fig. 2, enable signal Tx_Valid radiating circuit 24 is enabled; So, output signal Tx can not only directly be back to input circuit 28, also can be issued to outside the chip 10 via radiating circuit 24 simultaneously, allows the Test Engineer can judge also whether output signal Tx is normal.
The present invention can utilize the result of inner looping test to cooperate other tests to contrast the operation situation of each several part circuit with intersection.The example of hookup 1 and Fig. 2 please continue with reference to figure 3; Fig. 3 carries out the synoptic diagram of external loop test for the present invention cooperates an external loop circuit 58 on chip 10.Solder joint 56 is gone in the output that this external loop circuit 58 can be connected in chip 10, and the signal circuit that is used for radiating circuit 24 is sent is to receiving circuit 30.Comparison diagram 2, Fig. 3 when carrying out the test of this external loop, enable signal Tx_valid and can change and radiating circuit 24 is enabled come into operation as can be known; The test signal St that control signal T_mode can make test signal generation module 40 produce becomes output signal Tx via output circuit 22, and this output signal Tx will via radiating circuit 24 send into differential wave to Txp, Txn.Differential wave can become differential wave respectively to Rxp, Rxn via the loop of external loop circuit 58 to Txp, Txn, is back to chip 10 once again, makes receiving circuit 30 provide corresponding received signal Rx according to this two signal Rxp, Rxn.At the same time, control signal L_mode also can change and cut off inner looping, so that received signal Rx is transferred to input circuit 28, it is that indication signal SQi makes input circuit 28, buffer module 38 can carry out corresponding running that the whistle inhibition indicator signal SQ that preposition whistle inhibition amplifying circuit 32 is produced according to signal Rxn, Rxp also can be taken as.After producing respective signal D1, D2 according to received signal Rx, check module 42 just can with signal D2 therewith the original input signal St of external loop compare, verify whether the operation situation of this external loop meets expection.By Fig. 2, Fig. 3 more as can be known, output circuit 22, input circuit 28 and buffer module 38 are only arranged on the signal flow path of inner looping, output circuit 22, radiating circuit 24, receiving circuit 30, input circuit 28 and buffer module 38 are then arranged on external loop.The test result of inner looping and external loop relatively just can be intersected and contrasted in the AFE (analog front end) operation situation of circuit separately.For instance, if the test of inner looping is normal, wrong generation is but found in the external loop test, just represents the radiating circuit 24, receiving circuit 30 possibly can't normal operation.Be similar to the situation among Fig. 2, in external loop when test of carrying out Fig. 3, the signal that circuit produced separately is as signal D1, D2, also can go into solder joint 54 outputs, allow the Test Engineer can utilize these signals further to determine the operation situation of each several part circuit via the output of interface circuit 14.In addition, also can be provided with the measurement of correlation circuit in the external loop circuit 58, with the characteristics of signals of measuring-signal Txp, Txn, as situation of signal jitter (jitter), time domain response etc.
Continue the 2nd, the example of Fig. 3, please refer to Fig. 4.As aforementioned, the most basic measuring technology of test chip is carried out the allomeric function test exactly, and the running that chip is preset checks whether the result of its output meets expection.Shown in Figure 4 be the present invention carries out this kind test in chip 10 synoptic diagram.Compare with Fig. 3, in Fig. 4, interface control module 18 can actual input to coding module 20 with signal Sh, by coding module 20 it is encoded to coded signal Se, and the switching of control signal T_mode can make this coded signal Se be transferred to output circuit 22 to produce corresponding output signal Tx.Receive differential wave that this signal Tx are derived to Txp, Txn by radiating circuit 24, just can check that whether this differential wave to meeting expection.Be similar to the example among Fig. 2, Fig. 3, when carrying out the test of Fig. 4, also the output of each several part circuit can be gone into signal and go into solder joint 54 outputs via output.For instance, whether the Test Engineer can conform to original signal Sh output with the signal of final output with contrast signal Sh.The test result of every test just can be differentiated the operation situation of circuit separately comparatively clearly in the intersection comparison diagram 2 to Fig. 4.For instance, do not meet expection if find the output of chip 10 when carrying out the test of Fig. 3 or Fig. 4, and find that inner looping is normal during the test of the inner looping in carrying out Fig. 2, probably being exactly the radiating circuit 24 of simulating can not normal operation.Relatively,, but find that when carrying out the test of Fig. 4 signal Txp, Txn are not inconsistent expection, just represent the coding module 20 possibly can't normal operation if determined that when carrying out the test of Fig. 2, Fig. 3 output circuit 22, radiating circuit 24 can normal operations.
The example of continuity Fig. 1 please refer to Fig. 5.Fig. 5 is that chip 10 operates on general modfel (normalmode) and synoptic diagram during the performance chipset function.Interlock circuit and loop that control signal T_mode, L_mode meeting isolation test is used make interface circuit 16 energy normal operations, realize the interface of the advanced interconnection technique of serial (SATA).Each output is gone into solder joint 54 and is also changed by interface circuit 14 and normally use.
In summary, compared to known measuring technology, the present invention can be in chip the interlock circuit of built-in inner looping, its can be when carrying out chip testing some circuit in the isolating chip optionally, to assist the Test Engineer can rapider, more clearly orient the part of makeing mistakes in the chip, make the testing of circuit can be more efficient, also help the lifting of chip accuracy, and can effectively reduce the chip design production cost.In Fig. 1 to Fig. 5, be that example illustrates technology of the present invention for be implemented in a chipset with the present invention, but spirit of the present invention can be widely used in various chips, make the more effective enforcement of chip testing energy.
The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.
Claims (18)
1. chip, it includes:
One output circuit is used to provide an output signal;
One radiating circuit is used for this output signal is sent to outside this chip;
One receiving circuit is used for receiving the signal that transfers to this chip and the received signal of a correspondence is provided;
One input circuit, it has an input port; This output circuit can receive by the signal of this input port input and be handled; And
One multi-channel conversion circuit is used for optionally this output signal or this a received signal input port that inputs to this input circuit wherein.
2. chip as claimed in claim 1, it can operate on a test pattern and a general pattern; When this chip operated on general modfel, this multi-channel conversion circuit inputed to the received signal of this receiving circuit the input port of this input circuit; When this chip operated on this test pattern, this multi-channel conversion circuit then can input to the output signal of this output circuit the input port of this input circuit, and this receiving circuit can stop received signal.
3. chip as claimed in claim 2, it also includes:
One coding module; When this chip operated on general modfel, the signal encoding that this coding circuit can produce this chip running was a coded signal;
One test signal generation module; When this chip operated on test pattern, this test signal generation module can produce a test signal; And
All die change pieces, its optionally with this coded signal or this test signal wherein one transfer to this output circuit, and this output circuit produces this output signal according to the signal that this handover module transmitted.
4. chip as claimed in claim 3, it also includes:
One checks module; When this chip operates on this test pattern and when making this input circuit receive the output signal of handling this output circuit, this inspections module can contrast the signal of this test signal and this input circuit processing generation, and the check result of a correspondence is provided.
5. chip as claimed in claim 4, it also includes:
One buffer module is connected electrically between this inspection module and this input circuit; This buffer module can be handled the signal that produces to this input circuit and carry out elastic buffer and word registration process; And this inspection module contrasts this test signal and this buffer module is handled the signal of generation so that this check result to be provided.
6. chip as claimed in claim 3, wherein this coding module is one 8 coding modules that change 10, its 8 signal encodings that this chip running can be produced are 10 corresponding signals.
7. chip as claimed in claim 1, wherein this output circuit is a parallel serial circuit that changes, it can be output in this output signal in regular turn with a plurality of positions that receive simultaneously.
8. chip as claimed in claim 1, wherein this radiating circuit is a differential amplifier circuit, is used for this output signal is converted to differential wave to outside the chip that sends.
9. chip as claimed in claim 1, wherein this receiving circuit is a differential receiving circuit, is used for receiving the differential wave that transfers to this chip to produce this received signal accordingly.
10. chip as claimed in claim 9, it also includes a whistle and suppresses pre-amplification circuit, it can suppress indicator signal to produce a whistle accordingly according to the differential wave that transfers to this chip, and it is right to be used for representing this receiving circuit whether to receive differential wave.
11. chip as claimed in claim 10, it also includes one second multi-channel conversion circuit; When this multi-channel conversion circuit made the output signal of this output circuit input to the input port of this input circuit, this second multi-channel conversion circuit can suppress indicator signal with the whistle that a default reference indicator signal replaces this whistle to suppress pre-amplification circuit.
12. chip as claimed in claim 1, wherein this input circuit includes:
One restoring circuit is connected electrically in this input port, is used for producing according to the signal of this input port the clock and a data-signal of a correspondence.
13. chip as claimed in claim 10, wherein this input circuit also includes:
One change-over circuit, it can be converted to the multi-bit parallel signal with each position of serial in this data-signal.
14. chip as claimed in claim 1, it is a chipset, and this output circuit, radiating circuit and this receiving circuit, input circuit are used for realizing the AFE (analog front end) under the advanced interconnection technique specification of serial.
15. the method for test one chip is provided with an output circuit, an input circuit and a radiating circuit and a receiving circuit in this chip; This output circuit is used to provide an output signal, and this output circuit is used for this output signal is sent to outside this chip; This receiving circuit is used for receiving the signal that transfers to this chip and the received signal of a correspondence is provided, and this input circuit has an input port, this input circuit can be received by the signal of this input port input also handled; And this method includes:
When testing, the output signal of this output circuit is inputed to the input port of this input circuit.
16. method as claimed in claim 15, it also includes:
When testing, produce a test signal, and make this output circuit produce this output signal according to this test signal; And
After this output signal is inputed to this input circuit, contrast this test signal and this input circuit and handle the signal that produces, and produce the check result of a correspondence.
17. method as claimed in claim 15, wherein this chip also can provide a whistle to suppress indicator signal, is used for representing this receiving circuit whether to receive signal; And this method also includes:
When testing, generation one suppresses indicator signal with reference to indicator signal to replace this whistle.
18. method as claimed in claim 15, wherein this chip is a chipset, and this output circuit, radiating circuit and this receiving circuit, input circuit are used for realizing the AFE (analog front end) under the advanced interconnection technique specification of serial.
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| CNB2005100672480A CN100412559C (en) | 2005-04-20 | 2005-04-20 | Chip testing method and relevant apparatus |
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| CNB2005100672480A CN100412559C (en) | 2005-04-20 | 2005-04-20 | Chip testing method and relevant apparatus |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101713813B (en) * | 2008-10-06 | 2012-06-06 | 中兴通讯股份有限公司 | SOC (system on chip) chip and method for testing same |
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| JP2802140B2 (en) * | 1990-04-06 | 1998-09-24 | 三菱電機株式会社 | How to design logic circuits |
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