CN1928575A - Chip testing mechanism and related method - Google Patents
Chip testing mechanism and related method Download PDFInfo
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- CN1928575A CN1928575A CN 200610136102 CN200610136102A CN1928575A CN 1928575 A CN1928575 A CN 1928575A CN 200610136102 CN200610136102 CN 200610136102 CN 200610136102 A CN200610136102 A CN 200610136102A CN 1928575 A CN1928575 A CN 1928575A
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Abstract
The related chip testing method comprises: building inner loop in interface circuit of high-speed bus, sending information for I/O testing, and receiving the information by former inner loop to validate the chip I/O function and time sequence. This invention can save cost greatly and fit to take full-function I/O testing even in wafer stage.
Description
Technical field
The present invention relates to a kind of chip testing mechanism and correlation technique, relate in particular to a kind of chip testing mechanism and the correlation technique that can realize being connected with a high-speed bus with low cost.
Background technology
In electronic system, can intercourse information between the different electronic installations with bus, making between each electronic installation can coordinated manipulation, and separately function is integrated, and finishes the allomeric function of electronic system.For instance, in computer system, central processing unit can bridge at other each peripheral device (similarly being hard disk drive, CD-ROM drive, graphics acceleration card or the like) via chipset, and can be connected to each other with bus between central processing unit, chipset and each peripheral device, make above-mentioned these electronic installations energy integrated operation.Certainly, in the advanced information society of being particular about efficient, the usefulness requirement of electronic system is also increased day by day.In order to promote the integrated operation usefulness of electronic system, except will improving electronic installation usefulness separately, the bus between electronic installation also can high speed operation, exchange message so more quickly, and then promote overall efficiency.For example, in the computer system in modern times, chipset can (HT, HyperTransport) bus be come and the central processing unit swap data, to assist to promote the overall efficiency of computer system with at a high speed hypervelocity transmission.Under hypervelocity transfer bus specification, cooperate 1GHz (1GHz=10
9Hz) time pulse and transmit data with the frequency of 2GHz is to satisfy the high-speed requirement of bus.
In order to ensure can be normally via the high-speed bus swap data between electronic installation, when manufacturing electronic installation, whether the electronic installation input/output function also will can normally receive and send messages via its high speed bus interface with testing electronic devices through test.When conventional art is wanted the input/output function of testing electronic devices, directly receive and dispatch detecting information with external tester, with the input/output function of testing electronic devices via the high speed bus interface of electronic installation.For example, when testing one when having the input/output function of chipset of hypervelocity transfer bus interface circuit, conventional art is the high speed bus interface circuit that an external tester is attached to chipset, and chipset just can send information or receive information by tester to tester via the high speed bus interface circuit like this.If the information sent of high speed bus interface circuit and tester actual reception to information be not inconsistent, represent that then the transfer function (sending the function of information) of chipset has problem; In like manner, if the information that tester sends can not normally be received deciphering by the high speed bus interface circuit, has problem with regard to the receiving function of representing chipset.According to this principle, just can carry out input/output test to chipset.
As previously mentioned, modern bus is all high-speed bus, therefore if want the input/output function of real testing electronic devices, conventional art just must adopt external high-frequency test device at a high speed, and the high frequency input/output signal that could handle the high speed bus interface circuit is to test.Yet external high-frequency test device is very expensive, and therefore, the production of electronic installation, manufacturing cost also will remain high.For example, test the chipset with hypervelocity transfer bus, its tester just needs to handle the high-frequency signal (because the hypervelocity transfer bus is to transmit data with 2GHz) of 2GHz, and the cost of this high-frequency test device is very high.
Summary of the invention
Given this, the object of the present invention is to provide a kind of chip input/output test mechanism and correlation technique; When the present invention ties up to chip carried out input/output test,, come the input/output function and the sequential of test chip, and need not use external high-frequency test device by setting up the inner looping of input/output test.Therefore, the technology of the present invention can significantly reduce the cost of input/output test, overcomes the shortcoming of conventional art.
According to an aspect of the present invention, a kind of chip testing mechanism is provided, in order to test the input/output function of this chip, wherein this chip one end is connected with a high-speed bus, one end connects at least one low speed bus, this chip testing mechanism includes a core circuit, in order to the coding/decoding of master control one data-signal access; An and high speed bus interface circuit, be connected between this core circuit and this high-speed bus, include a transmission mechanism and a reception mechanism, in order to transmitting this data-signal, or receive this data-signal that sends by this high-speed bus end to this high-speed bus end; Wherein when this chip of test, set up an inner looping in this high speed bus interface circuit, make a test signal to be transmitted by the transmission mechanism of this high speed bus interface circuit, the reception mechanism via this inner looping by this high speed bus interface circuit is received.
According to an aspect of the present invention, a kind of chip detecting method is provided in addition, in order to test the input/output function of a chip, wherein this chip one end connects a high-speed bus, one end links at least one low speed bus, this method comprises following steps: at first, set up an inner looping between the transmission mechanism of this chip and reception mechanism; Then utilize the transmission mechanism of this chip to transmit a test signal; And make this test signal be received by the reception mechanism of this chip via this inner looping.
Carry out input/output test via inner looping, the present invention just can be from the high frequency input/output function of the direct test chip of low frequency level of core circuit, and does not need the high external high-frequency test device of use cost.In general, with low frequency time pulse trigger action, its inner phase-locked loop (and frequency divider or the like) can produce the input and output time pulse and the data time pulse of high frequency according to a low frequency time pulse in the interface circuit.For example, under the specification of hypervelocity transfer bus, the frequency of bus input and output time pulse is 1GHz, and bus data input and output frequency is more up to 2GHz, yet its interface circuit only needs with 100MHz (1MHz=10
6Hz) low frequency time pulse triggers.And conventional art must be at the external bus input/output terminal place of interface circuit, utilize external tester to receive and dispatch the 2GHz data, so its tester must be handled the 2GHz electronic signal, its cost is very high.Under comparing, owing to be provided with inner looping in the high speed bus interface circuit of chip testing mechanism of the present invention, so the present invention can sentence the carrying out that 100MHz triggers input/output test at core circuit; Under the control of core circuit, core circuit can make transmission circuit send customizing messages, allow receiving circuit receive the information that transmission circuit sends, and pass back to from receiving circuit whether proofing chip can correctly receive this customizing messages the information of core circuit via inner looping.In other words, utilize test structure of the present invention, but whether the present invention only need normal with regard to high frequency (at a high speed) input/output function of proofing chip with the 100MHz low frequency level of core circuit.And the low frequency test environment of 100MHz has good cost benefit, makes the present invention finish the high frequency input/output test originally with cheap one-tenth.
More particularly, the present invention also can come the input/output test of control chip group via the interface of low frequency more.In chipset,,, the bus of low frequency also can be set, on chipset as the pci bus of 33MHz so the hypervelocity transfer bus of high frequency not only can be set because chipset is wanted bridge joint high speed central processing unit and other low speed peripheral device.In the time will carrying out input/output test to chipset with hypervelocity transfer bus interface circuit, the present invention just can will test the information transmission of usefulness to chipset via the pci bus of low speed, interface circuit by chipset control hypervelocity transfer bus makes this detecting information send to inner looping with the signal form of high frequency/high speed via core circuit-transmission circuit.Via inner looping, receiving circuit can receive this detecting information, and passes back to core circuit; Under the control of chipset, the detecting information of this passback just can send out via the low speed pci bus.Relatively whether this passback detecting information conforms to the previous detecting information that sends, and just can understand the input-output operation situation of this chipset, reaches the purpose of input/output test.Under this test structure, the present invention only need utilize low speed (low frequency) pci bus of 33MHz to carry out input/output test to the chipset of HT bus interface with 2GHz, so can significantly reduce the operating frequency demand of test environment, reduce the input/output test cost of chipset.
Because the present invention can utilize inner looping in the high speed bus interface circuit to carry out the high frequency input/output test of chip under the low frequency test environment, so the present invention can just directly carry out input/output test to the chip that cuts, do not encapsulate at wafer stage.As is known to the person skilled in the art, can come the circuit on the wafer is carried out functional test by Detection Techniques such as probes at wafer stage, but this kind Detection Techniques have the restriction on the operating frequency equally.If will directly receive and dispatch the high-frequency signal of 2GHz with these Detection Techniques, technical difficulty is obviously arranged, also need expensive test environment and instrument.Under comparing, because the present invention can carry out the input/output test of chip under the low frequency test environment, the present invention just can use existing low-cost low-frequency acquisition technology to finish the input/output test of the chip with high speed bus interface circuit.Carry out input/output test at wafer stage and can be in early days just the chip of fault be screened, and needn't carry out follow-up packaging and testing, can further save the manufacturing cost of chip (interface circuit) these failure chips.Carry out input/output test though it is emphasized that the present invention under the low frequency test environment, chip can really operate under the high frequency in the general operation, so the present invention can really test the high frequency input/output function of chip.Example as previously mentioned, the present invention can test the chip with hypervelocity transfer bus interface circuit under the environment of 100MHz; Though test environment is 100MHz, the transmission circuit in the high speed bus interface circuit/receiving circuit can really be received and dispatched high-frequency data with the high frequency of 2GHz, so the present invention can come the input/output function and the performance of test chip veritably with the standard of general operation.
Description of drawings
By the description of carrying out below in conjunction with the accompanying drawing that provides demonstrative example, above and other objects of the present invention and characteristics will become apparent, wherein:
Fig. 1 one has the synoptic diagram of the electronic installation of high speed bus interface circuit;
Fig. 2 is according to one embodiment of present invention, has a synoptic diagram of electronic installation of the high speed bus interface circuit of inner looping;
Fig. 3 is electronic installation of the present invention carries out input/output test via low speed bus a circuit diagram;
Fig. 4 is the synoptic diagram of each coherent signal waveform sequential in the high speed bus interface circuit; And
Fig. 5 is the circuit diagram of electronic installation of the present invention under general operation.
Embodiment
Below, describe embodiments of the invention in detail with reference to accompanying drawing.
Please refer to Fig. 1; Fig. 1 one has the synoptic diagram of the electronic installation 10 of high speed bus interface circuit.Electronic installation 10 includes a high speed bus interface circuit 12 and a core circuit 14.Electronic installation 10 can be a chip in the electronic system, for example is the chipset in the computer system, and high speed bus interface circuit 12 makes that electronic installation 10 can be via high-speed bus 24 and other electronic installation (not shown) exchange message and signal.Core circuit 14 is used for the master control coding/decoding relevant with bus access and control item (for example: receive access from bus require opportunity that whether the back decision will respond and respond etc.).In the present invention, high-speed bus 24 can be a hypervelocity transfer bus (Hyper TransportBus).Be provided with a transmission circuit 16 and a receiving circuit 18 in the high speed bus interface circuit 12, and form an input and output connection pad module by each connection pad circuit TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, RCAD0-RCAD7, on high-speed bus 24, to send/to receive data respectively.Wherein, transmission circuit 16 and receiving circuit 18 are used for realizing the signal transmission and the receiving function of physical layer respectively.The then actual high-speed bus 24 that is connected in of each connection pad circuit is so that the electronic signal form of being worked out with bus specification is come receiving and transmitting signal.
When electronic installation 10 will be sent data to high-speed bus 24, data to be transmitted can be via the code conversion of core circuit 14, and change these information into high-speed bus 24 acceptable electronic signals via transmission circuit 16, be sent to high-speed bus 24 by each connection pad circuit TCLK, TCTL and TCAD0-TCAD7 again.
At Fig. 1 is one to have in the example of synoptic diagram of electronic installation of high speed bus interface circuit, core circuit 14 can be the data-signal of 64-250MHz with information code conversion to be transmitted, and cooperates the time pulse signal of the control signal of one 8-250MHz and one 8-250MHz and should information to be transmitted be sent to transmission circuit 16.And in the transmission circuit 16 and walk to the data-signal that serial circuit 20 just can be converted to the data-signal of 64-250MHz 8-2GHz, with making also the control signal with 8-250MHz be converted to 1-2GHz control signal, the time pulse signal of 8-250MHz is converted to 1-1GH time pulse signal.Control signal, time pulse signal can be sent to high-speed bus 24 by connection pad circuit TCTL, TCLK respectively; Simultaneously, the data-signal of 8-2GHz also can be sent to high-speed bus 24 by 8 connection pad circuit TCAD0-TCAD7 respectively.
On the other hand, when having a stroke count number of it is believed that to be sent to electronic installation 10 on the high-speed bus 24, the data-signal of this 8-2GHz can cooperate the form of 1-2GHz control signal and data-signal to send with 1-1GHz time pulse signal equally.The data-signal of these 1-1GHz time pulse signals, 1-2GHz control signal and 8-2GHz can be sent to electronic installation 10 via high-speed bus 24.Connection pad circuit RCLK, RCTL on the high speed bus interface circuit 12 and RCAD0-RCAD7 can receive the data-signal of above-mentioned 1-1GHz time pulse signal, 1-2GHz control signal and 8-2GHz respectively.And in the receiving circuit 18 and walk to time pulse signal and the control signal that serial circuit 22 just can be converted to 1-1GHz time pulse signal, 1-2GHz control signal 8-250MHz, and 8-2GHz signal originally also can be converted into 32-250MHz signal.These signals can be back to core circuit 14, by core circuit 14 decodings, deciphering, make electronic installation 10 can receive the information that other electronic installation transmits via high-speed bus 24.
In order to guarantee the normal running of electronic installation 10, when manufacturing electronic installation 10, must carry out input/output test to electronic installation 10, whether can correctly receive and dispatch the signal that meets the high-speed bus specification with testing electronic devices 10.
But, because the restriction on the circuit framework, in the time will carrying out input/output test to electronic installation 10, external high-frequency test device must be connected on each input and output connection pad circuit TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, RCAD0-RCAD7 of high speed bus interface circuit 12, with the transmitting-receiving high-frequency signal, and know the input and output performance of electronic installation 10 by this.Yet, as previously mentioned, the formed bus IO interface of above-mentioned these connection pad circuit can be carried out signal transmitting and receiving at a high speed with the high frequency of 1GHz, 2GHz, so traditional input/output test technology also can only just can be carried out input/output test under high frequency, high velocity environment.And high-frequency test environment and employed high-frequency test device thereof are very expensive, and the cost of traditional electronic devices 10 is improved.
Therefore, the present invention proposes a kind of chip input/output test mechanism and correlation technique, has the electronic installation of high speed bus interface in order to test.
Fig. 2 is the circuit diagram in the electronic installation 30 of the present invention.Electronic installation 30 can be a chip in the electronic system, for example is the chipset in the computer system.Be provided with a high speed bus interface circuit 32 and a core circuit 34 in the electronic installation 30.Wherein, this high speed bus interface circuit 32 is used to make the electronic installation 30 can be via high-speed bus 46 and other electronic installation (not shown) exchange message and signal.And high-speed bus 46 can be a hypervelocity transfer bus, is used to make the electronic installation 30 into chipset can be via this high-speed bus 46 and central processing unit (not shown) swap data.Core circuit 34 is used for master control coding/decoding relevant with bus access and control item.
Be provided with a transmission circuit 36, a receiving circuit 38 in the high speed bus interface circuit 32, and by the circuit-formed connection pad module of the input and output connection pad of TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, RCAD0-RCAD7, in order on high-speed bus 46, to send/to receive data respectively.Wherein, 38 of transmission circuit 36 and receiving circuits are used for realizing signal transmission and receiving function respectively.
In Fig. 2 example of the present invention, suppose that high speed bus interface circuit 32 is a hypervelocity transfer bus interface circuit, then its core circuit 34 can provide 64-250MHz integrated signal (the CAD signal of a correspondence according to the specification of hypervelocity transfer bus, CAD represents Command-Address-Data), and cooperate one 8 control signals and one 8 bit time pulse signals (250Hz) to represent information to be transmitted.In the transmission circuit 36 and walk to the integrated signal that serial circuit 40 just can be converted to the integrated signal of 64-250MHz 8-2GHz, also change control, the time pulse signal of 8-250MHz into 1-2GHz control signal and 1-1GHz time pulse signal respectively simultaneously.
On the other hand, be serial to integrated signal, 1-2GHz control signal and the 1-1GH time pulse signals that 42 of parallel circuits can be received 8-2GHz by a receiving port 48 in the receiving circuit 38, and these signals are converted to the control signal of the integrated signal of 64-250MHz, 8-250MHz and the time pulse signal of 8-250MHz respectively, again the signal after these conversions is back to core circuit 34, understands the information of these signal representatives by core circuit 34.
Each connection pad circuit TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, the then actual high-speed bus 46 that is connected in of RCAD0-RCAD7 are so that the electronic signal form of being worked out with the high-speed bus specification is come receiving and transmitting signal.
For example, according to hypervelocity transfer bus specification, bus is that the signal with differential form carries information; In this bus specification, each output connection pad TCLK, TCTL, TCAD0-TCAD7 circuit can have two connection end points (two stitch) respectively on bus 46, transmit 1 signal with a pair of anti-phase each other differential wave.Therefore TCLK, TCTL and TCAD0-TCAD7 can send 1 bit time pulse signal, 1 control signal and 8 s' integrated signal to bus 46 respectively.Relatively, each imports connection pad circuit RCLK, RCTL and RCAD0-RCAD7 then can receive differential form respectively on bus 46 signal, and each connection pad circuit can take out one signal from the pair of differential signal.Therefore the signal of respectively importing connection pad circuit RCLK, RCTL and RCAD0-RCAD7 reception just becomes 1 bit time pulse signal, 1 control signal and 8 integrated signals respectively.In hypervelocity transfer bus specification, control signal can be used to indicate the feature of each information representative in the integrated signal, and time pulse signal then is used to refer to the sequential of control signal and integrated signal.For example, when control signal triggered (assert), representing what carry in the integrated signal was steering order and related data address (for example, from a certain data address request msg); When control signal did not trigger (de-assert), representing what carry in the integrated signal was data.
In order to realize input/output test technology of the present invention, between transmission circuit 36/ receiving circuit 38, form an inner looping in the high speed bus interface circuit 32 of the present invention, make to be received by receiving circuit 38 through inner looping by the signal that is sent in the transmission circuit 36.Receiving circuit 38 is provided with a multiplexing module 50 in addition, and via the control of this multiplexing module 50, high speed bus interface circuit 32 can be selected from high-speed bus 46 reception information, or receives the information that transmission circuit 36 is sent from inner looping.
In the application of Fig. 2, because the information D ATA1 that transmission circuit 36 sends includes time pulse signal CLK, control signal CMD and integrated signal CAD, so inner looping can take back the road to receiving circuit 38 with these three kinds of signals.And the multiplexing module 50 in the receiving circuit 38 includes multiplex electronics mux1, mux2 and mux3 is used for switching respectively information D ATA that is come by transmission circuit or the information D ATA ' that is transmitted through the connection pad circuit by high-speed bus 46.Wherein, multiplex electronics mux1 can switch, so that receiving end 48 optionally receives the integrated signal CAD that transmission circuit 36 transmits, or by the received integrated signal CAD ' of input connection pad circuit RCAD0-RCAD7.Multiplex electronics mux2 can switch, so that receiving end 48 optionally receives the control signal CMD that transmission circuit 36 transmits, or by the received time pulse signal CMD ' of input connection pad circuit RCLK.Multiplex electronics mux3 can switch, so that receiving end 48 optionally receives the time pulse signal CLK that transmission circuit 36 transmits, or by the received time pulse signal CLK ' of input connection pad circuit RCLK.
Utilize above-mentioned inner looping, the present invention just can directly carry out the input/output test of electronic installation 30 in high speed bus interface circuit 32, and need not use external high-frequency test device.
When carrying out input/output test of the present invention, multiplexing module 50 in the receiving circuit 38 (comprising multiplexer mux1-mux3) can switch, so that the information D ATA that transmission circuit 36 is sent transfers to (comprising time pulse signal CLK, control signal CMD and integrated signal CAD) receiving port 48 of receiving circuit 38 via inner looping.After this received information of the information that sent of transmission circuit 36 and receiving circuit 38 relatively more just can test out the input/output function of electronic installation 30.
When high speed bus interface circuit 32 will be operated usually, multiplexing module 50 just can stop the connection of inner looping, makes the receiving port 48 of transmission circuit 38 can be normally receive information on the high-speed bus 46 via each input connection pad circuit RCLK, RCTL and RCAD0-RCAD7.
By carrying out input/output test via inner looping, the present invention just can directly directly test the high frequency input/output function of transmission circuit 36/ receiving circuit 38 from the low frequency level of core circuit 34, and does not need the high external high-frequency test device of use cost to come from the bus input/output function of the bus input/output terminal test high frequency of high frequency.Example with Fig. 2, under hypervelocity transfer bus specification, though the time pulse signal of transmission circuit 36/ receiving circuit 38 transmission/receptions has the high-frequency of 1GHz, and control signal/integrated signal frequency is more up to 2GHz, yet high speed bus interface circuit 32 only needs with 100MHz (1MHz=10
6Hz) low frequency time pulse triggers.Interface circuit 32 is after the low frequency time pulse that has received 100MHz triggers, core circuit 34 just can be with frequency and transmission circuit 36/ receiving circuit 38 exchange messages (the just time pulse signal of 250MHz, control signal and integrated signal) of 250NHz, and transmission circuit 36/ receiving circuit 38 also just can come the information on the transceiver bus 46 with 1GHz time pulse signal and 2GHz control signal, integrated signal data.Therefore, the present invention only need utilize the test environment of 100MHz, just can know whether transmission circuit 36, receiving circuit 38 can correctly carry out the high frequency input and output of 2GHz via the operation of core circuit 34.
In traditional input/output test technology, conventional art must be at the external bus input/output terminal of high speed bus interface circuit, utilize external tester to receive and dispatch the 2GHz data, so its tester must be handled the 2GHz electronic signal, its cost is very high.Under comparing, owing to be provided with inner looping in the interface circuit of the present invention, so the present invention can trigger the carrying out of input/output test at the core circuit place with 100MHz; Under the control of core circuit, core circuit can make transmission circuit send customizing messages, and the information of utilizing receiving circuit to be back to core circuit verifies whether receiving circuit can correctly receive this customizing messages.In other words, utilize test structure of the present invention, the present invention only needs just can verify in the 100MHz of core circuit low frequency level whether the 2GHz high frequency/high speed input/output function of transmission circuit is normal.And the low frequency test environment of 100MHz has good cost benefit, makes the present invention finish the high frequency input/output test originally with cheap one-tenth.
In addition, the present invention also can control the input/output test of high-frequency bus interface circuit via the bus interface of low frequency more.
Because chipset is wanted bridge joint high speed central processing unit and other low speed peripheral device, so the hypervelocity transfer bus of high frequency not only can be set on chipset, the bus of low frequency also can be set, and similarly is the pci bus (PCI is Peripheral Communication Interconnect) of 33MHz.In the time will carrying out input/output test to the interface circuit of hypervelocity transfer bus, the information transmission that second embodiment of the invention can will be tested usefulness via the pci bus of low speed is to chipset, so that chipset can be tested the interface circuit of hypervelocity transmission control bus according to this detecting information.
Fig. 3 is electronic installation of the present invention carries out input/output test via low speed bus a circuit diagram, if electronic installation 30 is a chipset and is provided with a low speed bus 52 in addition (for example: the pci bus of 33MHz), the present invention just can be via this low speed bus 52 carry out input/output test at a high speed to electronic installation 30 hypervelocity transfer bus interface circuits 32.When interface circuit 32 is carried out input/output test, the present invention can be input in the chipset (being electronic installation 30) via the information (also can be described as test vector usually) that low speed bus 52 will be tested usefulness, this detecting information can be to read request instruction, and request electronic installation 30 reads the data of a certain address from high-speed bus 46.The detecting information that is input in the electronic installation 30 can be sent to core circuit 34 via bridgt circuit 54, and this core circuit 34 will send corresponding 250MHz time pulse signal, control signal and integrated signal to high speed bus interface circuit 32, correspondingly, the transmission circuit 36 in the high speed bus interface circuit 32 also will send time pulse/control/integrated signal of 1GHz/2GHz.
Time pulse/control/integrated signal that transmission circuit 36 sends can be back to the receiving port 48 of receiving circuit 38 via inner looping, forms time pulse/control/integrated signal of 250MHz again and is back to core circuit 34.If the input-output operation of transmission circuit 36, receiving circuit 38 is all normal, then this core circuit 34 should be able to be separated the request instruction that reads of reading a upstream (upstream).The deciphering result of core circuit 34 can be via bridgt circuit 54 and low speed bus 52 (33MHz) output.Relatively whether the detecting information of this passback meets the detecting information of previous input, and whether the input/output function that just can understand electronic installation 30 is normal, has also just understood the transceiving high speed signal whether high speed bus interface circuit 32 can be correct.
Under the test structure of Fig. 3, the present invention can directly adopt the low frequency test environment of 33MHz to control the input/output test of high-speed bus (transfer bus promptly exceeds the speed limit), the high-speed bus input/output test of high frequency is just finished in equivalence under the low frequency test environment.Therefore, the present invention can reduce the test environment requirement of high-speed bus input/output test, significantly reduces the cost of high-speed bus input/output test, and the high-effect of high-speed bus can be used by popular at large.
What be worth emphasizing is, though the present invention is the high-speed bus input/output test that carries out electronic installation 30 under the low frequency test environment, but the high speed bus interface circuit 32 of electronic installation 30 can really operate in the high frequency under the common operation, so the present invention can really test the high frequency input/output function of high speed bus interface circuit 32.Example as shown in Fig. 2, Fig. 3, the present invention can test the high speed bus interface circuit 32 of 2GHz hypervelocity transfer bus under 100MHz or the environment of 33MHz.Though test environment is the test environment of low frequencies such as 100MHz or 33MHz, but transmission circuit 36/ receiving circuit 38 in the high speed bus interface circuit 32 can really be received and sent messages with the high frequency of 2GHz, so the present invention can come the high frequency input/output function and the performance of testing electronic devices 30 veritably with the standard of common operation.
On the other hand, after the input/output function of having confirmed transmission circuit 36/ receiving circuit 38 with above-mentioned input/output test, the present invention can further test the function of each input and output connection pad circuit TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, RCAD0-RCAD7.Basically, because the function of these connection pad circuit only is that the signal of following transmission circuit 36/ receiving circuit 38 is operated, so can test with the mode of frequency reducing.For example, when test output connection pad circuit TCLK, TCTL and TCAD0-TCAD7, can make transmission circuit 36 send time pulse/control/integrated signal of 200MHz to these connection pad circuit, and receive the signal that these connection pad circuit are sent in the termination that connection pad circuit TCLK, TCTL and TCAD0-TCAD7 are connected with bus end 46, whether can correctly transfer to the signal of each connection pad circuit and send corresponding differential wave to test these connection pad circuit to bus 46 according to transmission circuit 36.In like manner, when connection pad circuit RCLK, RCTL and RCAD0-RCAD7 are respectively imported in test, also can use and test the receiving function of respectively importing the connection pad circuit than the signal of low frequency.So, just can finish complete input/output test to high speed bus interface circuit 32.
Because the present invention can utilize the inner looping in the high speed bus interface circuit to carry out electronic installation input/output test at a high speed under the low frequency test environment, so the present invention can just directly carry out input/output test to the electronic installation (chip) that cuts, do not encapsulate at wafer stage.As is known to the person skilled in the art, can utilize Detection Techniques such as probe to come the circuit on the wafer is carried out functional test at wafer stage, but this Detection Techniques have the restriction on the operating frequency equally.If will directly receive and dispatch the high-frequency signal of 2GHz with these Detection Techniques, technical difficulty is obviously arranged, also need expensive test environment and instrument.Under comparing, the present invention can directly use existing low-cost low-frequency acquisition technology to finish the high speed input/output test.Carrying out input/output test at wafer stage can just screen out of order chip in early days, and needn't carry out follow-up packaging and testing to these failure chips, can further save the manufacturing cost of chip.Certainly, at the chip of finishing encapsulation, still can also utilize inner looping technology of the present invention to carry out input/output test of the present invention.
The high frequency signals transmitted, the mutual sequential/phase relation between each signal is very important with order on high-speed bus.As in the example of Fig. 2, control signal and time pulse signal should be kept certain phase relation; Similarly, also should keep certain phase relation between each integrated signal and time pulse signal.
With reference to figure 4, be example with time pulse signal, control signal and integrated signal on connection pad circuit TCLK, TCTL and the TCAD0-TCDA7, shown in Figure 4 is exactly mutual relationship desirable between these signals.The transverse axis of Fig. 4 is the time.In the specification of hypervelocity transfer bus, the time pulse signal of 1GHz (being labeled as TCLK among Fig. 4) has 1000ps (1ps=10
(12)Second) cycle, in the time pulse signal every the rising edge of half period (500ps) and negative edge can be respectively in control signal (being labeled as TCTL) and each integrated signal (be labeled as TCAD[7:0]) data of triggering, so control signal, integrated signal are the signal of 2GHz.As is known to the person skilled in the art, in order to trigger stable signal/data sampling, the rising edge of time pulse signal and negative edge should be avoided the signal transition place of control signal/integrated signal.As shown in Figure 4, under ideal state, should there be the mistiming (phase differential just) of 1/4 cycle (250ps just) between the signal transition place of the rising edge/negative edge of time pulse signal and control/integrated signal.Certainly, when actual operation, still can tolerate sequential distortion (skew) to a certain degree between time pulse signal and the control signal/integrated signal.For example, if the rising/negative edge of time pulse signal and the mistiming that the rising/negative edge under the ideal state has 50ps, then its sequential degreeof tortuosity should be also within the tolerable scope.But if unusual excessive sequential distortion is arranged (for example between the rising/negative edge of time pulse signal and the control signal/integrated signal, have the above mistiming of 100ps between the rising/negative edge of time pulse signal and the rising/negative edge under the ideal state), the rising/negative edge of time pulse signal will be too near the signal transition place of control signal/integrated signal; So, just be difficult to the information of on bus, correctly transmitting.
In the present invention, when transmission circuit 36 operations, transmission circuit 36 should be able to be kept suitable mutual sequential/phase place according to foregoing description between time pulse signal/control signal/integrated signal.In like manner, receiving circuit 38 also should be able to be operated according to suitable mutual sequential/phase place.Therefore, when transmission circuit 36/ receiving circuit 38 to high speed bus interface circuit 32 carried out input/output test, test environment should not introduced between each signal of transmission circuit/receiving circuit the extra mistiming (sequential distortion just) yet.If when transmission circuit/receiving circuit is carried out input/output test, test environment itself will be introduced extra sequential distortion in each coherent signal (just time pulse signal and control signal/integrated signal), the operational circumstances that then just can't correctly reflect transmission circuit/receiving circuit makes test lose meaning.
Because the present invention constructs test environment with the inner looping in the high speed bus interface circuit 32, so test environment of the present invention can be considered the sequential balance between each signal (time pulse signal, control signal/integrated signal) with comparalive ease, avoid between each signal, introducing the unnecessary mistiming.Under comparing, the formation external loop carries out input/output test if (just be connected part at each input and output connection pad circuit with bus) with external tester outside high speed bus interface circuit 32, just is very easy to introduce the extra mistiming between each signal.As is known to the person skilled in the art, when wanting transmitting high-frequency signal, high-frequency signal can be influenced by the transmission line effect on the signal transmission path; Transmit if unlike signal has in length/characteristic on the different transmission path of difference, will between unlike signal, introduce the extra mistiming.Therefore, utilize external circuits to arrange that a good high frequency external loop test environment is very difficult.Under comparing, the present invention has just arranged the inner looping test structure within the high speed bus interface circuit, thus can reduce the ill effect on the inner looping transmission path as best one can, for the high frequency input/output signal of high-speed bus provides preferable test environment.
Fig. 5 is the circuit diagram of electronic installation 30 of the present invention in operating usually.When input/output test finishes and electronic installation 30 will normally operate usually the time, multiplexing module 50 can cut off inner looping (so being represented by dotted lines) in Fig. 5, make receiving circuit 38 normally receive the time pulse signal/control signal/integrated signal that transmits by high-speed bus 46, and stop to receive time pulse signal/control signal/integrated signal that transmission circuit 36 is sent by inner looping by each input connection pad circuit RCLK, RCTL and RCAD0-RCAD7.
In summary, compare with traditional external high frequency input/output test technology, the present invention is by at electronic installation (for example: in high speed bus interface circuit chip) inner looping is set, operation via high speed bus interface circuit medium and low frequency core circuit utilizes inner looping to carry out the input/output test of high frequency transmission circuit/receiving circuit.Therefore, the present invention can use the test environment of low frequency to finish the high frequency input/output test of electronic installation, to reduce the cost of test.Input/output test technology of the present invention can not only apply to encapsulate the chip of finishing, and can also not cut at chip, just carries out early stage global function input/output test when not encapsulating, and further saved the time and the cost of subsequent treatment.Be noted that in addition, though Fig. 2 to Fig. 5 be with the formal specification of the high speed bus interface circuit of 8 bit widths (8 integrated datas) hypervelocities transfer bus specification performance of the present invention, but spirit of the present invention can be widely used in the interface input/output test of the hypervelocity bus interface circuit (similarly being the hypervelocity bus of 16 bit widths) of other bit width and other various high-speed buses, express network, and is not limited to the transfer bus that exceeds the speed limit.
Though in above-mentioned, disclosed the present invention with preferred embodiment; when these preferred embodiments are not in order to limit scope of the present invention; those skilled in the art under the premise without departing from the spirit and scope of the present invention; can do various changes and retouching, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (13)
1, a kind of chip testing mechanism is used to test the input/output function of this chip, and wherein this chip one end is connected with a high-speed bus, and an end connects at least one low speed bus, and this chip testing mechanism comprises:
One core circuit is used for the coding/decoding of master control one data-signal access; And
One high speed bus interface circuit is connected between this core circuit and this high-speed bus, includes a transmission mechanism and a reception mechanism, is used to transmit this data-signal to this high-speed bus end, or receives this data-signal that is sent by this high-speed bus end;
Wherein when this chip of test, set up an inner looping in this high speed bus interface circuit, make a test signal to be transmitted by the transmission mechanism of this high speed bus interface circuit, the reception mechanism via this inner looping by this high speed bus interface circuit is received.
2, chip testing mechanism as claimed in claim 1, wherein this high speed bus interface circuit comprises:
One transmission circuit is connected to this core circuit, transmit this data-signal to this high-speed bus to be used to realize the transmission mechanism of this high speed bus interface circuit; And
One receiving circuit is connected to this core circuit, receives by this data-signal that this high-speed bus sent to be used to realize the reception mechanism of this high speed bus interface circuit.
3, chip testing mechanism as claimed in claim 2, wherein this receiving circuit includes a multiplexing module, is used to control the connection of this inner looping, wherein when this chip of test, makes this receiving circuit receive this test signal that is sent by this inner looping; And when this chip of normal running, make this receiving circuit receive this data-signal by this high-speed bus sent.
4, chip testing mechanism as claimed in claim 3, wherein this test signal and this data-signal all include an integrated signal, one control signal and a time pulse signal, wherein this multiplexing module includes: one first multiplexer is used for switching this integrated signal of this test signal or this data-signal; One second multiplexer is used for switching this control signal of this test signal or this data-signal; And one the 3rd multiplexer, be used for switching this time pulse signal of this test signal or this data-signal.
5, chip testing mechanism as claimed in claim 2, wherein this transmission circuit includes and walks to serial circuit in the lump, in order to will be converted to the acceptable data-signal of this high-speed bus by this data-signal that this core circuit sent; And including one, this receiving circuit is serial to parallel circuit, in order to will convert the acceptable data-signal of this core circuit to by the data-signal that this high-speed bus sent.
6, chip testing mechanism as claimed in claim 5, wherein this high-speed bus is a hypervelocity transfer bus, should and walk to serial circuit and convert the one 64-250MHz integrated signal that this core circuit provides to one 8-2GHz integrated signal, one 8-250MHz control signal converts the control signal of one 1-2GHz to, and one 8-250MHz time pulse signal converts the time pulse signal of one 1-1GHz to; And this is serial to parallel circuit and will converts one 64-250MHz integrated signal to by the one 8-2GHz integrated signal that this high-speed bus transmits, one 1-2GHz control signal converts one 8-250MHz control signal to, and one 1-1GHz time pulse signal converts the time pulse signal of one 8-250MHz to.
7, chip testing mechanism as claimed in claim 1 is wherein received this test signal by this low speed bus termination, and relatively whether transmit be normal with the operation of judging this chip with this test signal that receives.
8, chip testing mechanism as claimed in claim 1, wherein this chip testing mechanism also includes a plurality of connection pad circuit, places between this high speed bus interface circuit and this high-speed bus, is used for receiving and transmitting data signals.
9, a kind of chip detecting method is used to test the input/output function of a chip, and wherein this chip one end connects a high-speed bus, and an end connects at least one low speed bus, and the method comprising the steps of:
Between the transmission mechanism of this chip and reception mechanism, set up an inner looping;
Utilize the transmission mechanism of this chip to transmit a test signal; And
This test signal is received by the reception mechanism of this chip via this inner looping.
10, chip detecting method as claimed in claim 9 wherein utilizes the connection in this inner looping path of multiplexed mechanism control, and when this chip of test, this multiplexed mechanism activates the connection of this inner looping; And when this chip of normal running, this multiplexed mechanism is ended connection of this inner looping, but the transmission mechanism data signal that makes this chip to this high-speed bus end, the reception mechanism of this chip can be received data-signal by this high-speed bus termination.
11, chip detecting method as claimed in claim 9, wherein this test signal includes an integrated signal, a control signal and a time pulse signal.
12, chip detecting method as claimed in claim 9 is wherein received this test signal by this low speed bus termination; And this transmit of low speed bus end comparison and this test signal that receives, whether normal with the operation of judging this chip.
13, chip detecting method as claimed in claim 12, wherein this high-speed bus is a hypervelocity transfer bus.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106172A (en) * | 2013-02-26 | 2013-05-15 | 龙迅半导体科技(合肥)有限公司 | Chip and method testing chip |
| CN106844121A (en) * | 2017-02-15 | 2017-06-13 | 湖南长城银河科技有限公司 | The device for detecting performance and method of a kind of Feiteng processor |
| CN110021334A (en) * | 2019-04-19 | 2019-07-16 | 上海华虹宏力半导体制造有限公司 | A kind of crystal round test approach |
| CN112912329A (en) * | 2019-02-27 | 2021-06-04 | 三菱电机大楼技术服务株式会社 | Interface device with function of converting signals of elevator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3005250B2 (en) * | 1989-06-30 | 2000-01-31 | テキサス インスツルメンツ インコーポレイテツド | Bus monitor integrated circuit |
| JPH11219599A (en) * | 1998-02-03 | 1999-08-10 | Hitachi Ltd | Semiconductor memory |
| US6316933B1 (en) * | 1999-08-26 | 2001-11-13 | Broadcom Corporation | Test bus circuit and associated method |
| US6591369B1 (en) * | 1999-10-01 | 2003-07-08 | Stmicroelectronics, Ltd. | System and method for communicating with an integrated circuit |
| KR100594257B1 (en) * | 2004-02-26 | 2006-06-30 | 삼성전자주식회사 | System-on-chip having built-in self test circuits and self test method of the same |
| US20060218332A1 (en) * | 2005-03-25 | 2006-09-28 | Via Technologies, Inc. | Interface circuit, system, and method for interfacing between buses of different widths |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103106172A (en) * | 2013-02-26 | 2013-05-15 | 龙迅半导体科技(合肥)有限公司 | Chip and method testing chip |
| CN103106172B (en) * | 2013-02-26 | 2015-08-12 | 龙迅半导体科技(合肥)有限公司 | A kind of chip and test the method for this chip |
| CN106844121A (en) * | 2017-02-15 | 2017-06-13 | 湖南长城银河科技有限公司 | The device for detecting performance and method of a kind of Feiteng processor |
| CN112912329A (en) * | 2019-02-27 | 2021-06-04 | 三菱电机大楼技术服务株式会社 | Interface device with function of converting signals of elevator |
| CN112912329B (en) * | 2019-02-27 | 2022-08-19 | 三菱电机大楼技术服务株式会社 | Interface device with function of converting signals of elevator |
| CN110021334A (en) * | 2019-04-19 | 2019-07-16 | 上海华虹宏力半导体制造有限公司 | A kind of crystal round test approach |
| CN110021334B (en) * | 2019-04-19 | 2021-08-27 | 上海华虹宏力半导体制造有限公司 | Wafer testing method |
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| CN100460888C (en) | 2009-02-11 |
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