TWI289760B - An apparatus of multi-lanes serial link and the method thereof - Google Patents

Abstract

An apparatus of multi-lanes serial link and the method thereof. The embodiment of the invention includes a common clock generator and a plurality of transceivers. The common clock generator is used for generating at least a transmit clock and a plurality of receive clock. The transceiver serializes the transmit data and outputs a first transmit differential signal and a second transmit differential signal; and the transceiver also de-serializes the first receive differential signal and the second receive differential signal and outputs the receive data.

Description

1289760

TECHNICAL FIELD OF THE INVENTION The present invention relates to a #志方法, and more particularly to a multi-channel wide + seriai iink device and method. , multl-lanes serial connection device and [prior art] Due to the increasing speed of data transmission, the original > column transmission architecture, such as pci years old, P, 求W seeking to pay The original structure is the use of multiple connecting lines, and the squad is connected.

Under the speed of data transmission, for multiple links; the step is very difficult to achieve. j The current high-speed transmission system uses serial transmission, such as Universal Serial Bus (_). In the (4) 2 规格 size bus, it is transmitted at a rate of 480 Mbits/s, using a clock system of 240 MHz. For higher speed transmissions, such as greater than igHz, serialization/de-seriaHze SERDES transceivers are required. The serialization/deserialization transceiver component is applied, for example, to a PCI Express architecture.

Figure 1 is a block diagram of a conventional serialization/deserialization transceiver component. The serialization/deserialization transceiver component 100 includes a transmission unit 12A and a reception unit 14A for respectively transmitting and receiving signals. The operation of transmitting and receiving signals of the serialization/deserialization transceiver component 100 described above is performed in the form of a differentially driven pair, as shown in the figure.

1289760 -*------- V. Description of the invention (2) The 77 shown is the transmission pair TxP and ΤχΝ, and the receive pair RxP & RxN. The transmission unit 120 includes a transmission clock generator 122 and a transmitter 124. The transmission clock generator 122 generates a transmission clock tCLK and outputs it to the transmitter 124. The externally entered data t])ata, for example, is a parallel data in the computer. After the transmitter 124 receives the transmission clock tCLK and the parallel data tData, the parallel data tData is serialized and then the transmission pair signals ΤχΡ and 产生 are generated to perform an output operation. As for the 'receiving unit 1404', it consists of a receiver 1 4 2 Clock Data Recovery Unit (CDR) 144. After the receiver 142 receives the receive pair signals RxP and RxN, the receive pair signals Rxp and RxN are deserialized and output to the clock data restorer 1 44. After receiving the deserialized signal, the clock data recoverer 1 44 performs correlation processing with the clock signal generated by the internal clock generator 146, for example, using a phase-tracking method to reply the received signal. The clock and data, while the output receives the data rData. Since the PCI high-speed architecture connected in series is connected to peripheral devices, a multi-channel structure is often used, that is, a plurality of serial connection channels are simultaneously used to achieve the required transmission and reception rate of peripheral devices. However, the serialization/deserialization transceiver components required for a channel shown in Figure 1 must have two sets of clock generators, so for a multi-channel column line, more clock generators, In this way, it will take up the wafer area of the stone and s, and it is quite power-consuming and uneconomical.

1289760 V. SUMMARY OF THE INVENTION (3) SUMMARY OF THE INVENTION In view of the above, the multi-channel (multiy) of the pulse generator of the present invention is provided in accordance with the present invention. And method. Serial connection dream, sentence iiitm multi-lanes (multi-lanes) transceiver components: shared clock generation and f serialization / deserialization data serialization processing 7T out of the clock, will want ... The clock will receive the receiving pair _ #二° r, and according to the receiving data. After the “de-serialization of the tiger, the output receives the pulse output ί ί 2: mention t; ί道串连连The line method is generated by the shared clock generator when the sharing is performed; the tank can be used to perform the serialization of the clock; and the one of the receiving materials is generated and transmitted. For the signal, the pair of k is received, and the receiving clock is used to perform the serialization process, and the # is generated. The effect of the incoming signal to solve the number of receiving clocks is to receive the clock-to-transmission pair of the transmission clocks. One bit interval of the signal: = the effect of the signal on the signal, respectively Signals and controls to achieve power saving. Brothers agree that the above objectives, features, and advantages can be more obvious. The following is a special example - the preferred embodiment, with the drawings, for details Said IHin^Sg Page 7 TO135F (VIA).ptd 1289760 V. Description of invention (4) ---- Ming as follows: [Embodiment] Two-speed configuration (PCI express architecture) is connected in series (serai 1 Link) is connected to the peripheral device. Each serial connection includes at least one lane, and each channel is controlled by the foregoing serialization/deserialization transceiver component. It can be increased according to the required transmission and reception rate of the peripheral device. Referring to FIG. 2, a block diagram of a multi-channel serial connection device according to a preferred embodiment of the present invention is shown. A serial connection device can be designed with multiple channels to increase transmission to peripheral devices. The rate, for example, a serial connection device with 6 channels is 16 times faster than a serial connection device with one channel. As shown in Fig. 2, the multi-channel serial connection device 2〇〇 A shared clock generator 210 is included A plurality of serializer/de-serializer (SERDES) transceiver components 220. The second diagram illustrates a two-channel serial connection device as an example, but is not limited to only two channels. The shared clock generator 210 generates a transmission clock tCLK1-m and a reception clock rCLK1-n, where m and n are integers at least equal to or greater than 1 to be supplied to the respective SERDES transceiver elements 220. Each SERDES transceiver element 2 2 0 is used to serialize the parallel data tData to be transmitted according to the transmission clock t CL Κ1 - m, and then output the transmission pair signals TxP and ΤχΝ. Each of the SERDES transceiver elements 220 outputs the data rData after the received differential pair signals RxP and RxN are deserialized according to the reception clock rCL1U-η.

TW1135F (VIA).ptd Page 8 1289760

Each SERDES transceiver component 220 includes an enabling unit 231, a wheel feeder 2 41, and a receiver 2 51 time-of-day data recovery unit 253. The enabling unit 2 3^" 1 determines whether to receive the transmission clock tCLKl-m and the reception clock rCLKl-n according to the control of the transmission enable signal ΕΝΐ and the reception enable signal Εηι. Therefore, if the SERDES transceiver component 220 does not have any receiving or transmitting action, the transmission enable signal ENt and the reception enable signal Enr can be used to suspend the supply of the clock to save power. The enabling unit 231 can be simply designed to be composed of AND gates A1 and A2. The gate A1 determines whether or not to output the reception clock rCL1U-η to the clock data restorer 253 based on the reception enable signal ENr. The gate A2 determines whether to transmit the transmission clock tCLin-m according to the transmission enable signal ENt. Since the enabling unit 231 can control the output of the clock, it is possible to effectively save power.

The transmitter 241 receives the transmission clock tcLjn and the transmitted parallel data tData ', and generates a transmission pair signal ΤχΡ and ΤχΝ output. After receiving the pair signals r χ ρ and r χ ν, the receiver 2 5 1 converts them into parallel data and outputs them to the clock data recoverer 2 5 3 . The clock data restorer 253' does not need to have a clock generator internally because it utilizes the receive clock rCLK丨-^ output by the shared clock generator 210, and is transmitted by the control unit 231 control. The receiving clock rCLK1_n and the receiver 251 send the parallel data, perform correlation processing to reply the clock and data of the received signal, and rotate the receiving data rData. Since the clock data recovery unit 2 5 3 does not have a clock generator inside, this can effectively reduce the area on the wafer. 8 Guardian > Material Recoverer 253 is multi-sampling (〇ver-sampling)

1289760 V. Inventive Note (6), the technology 'requires a multi-phase receiving clock rCLlU-η, that is, multiple sampling in one bit interval during operation, and then determines the content of this bit π as 1 Or 〇. Since the oversampling technique is digital, it can be easily designed in a small area with a small area and has better accuracy. In addition, the shared clock generator 210 generates the transmission clock tCLm-m and the reception clock rCLIH-n, for example, a phase-locked loop (multi phase phase l〇ck l〇〇p) that can generate a plurality of phase clocks, which can be simultaneously generated. At least 3 to 40 clocks of different phases. With the clock data recovery device 253 is a multi-sampling technique, so the receiving clock rCLk of multiple phases is required. For example, we can set n = 3m here, indicating that the shared clock generator 2 generates a transmission clock tCLKl. At the same time, three corresponding receiving clocks rCLK 1-3 are generated, so that the clock data recoverer 253 internally samples three times in one bit interval. The multi-channel tandem wiring device disclosed in the above embodiments of the present invention has the following advantages: 1. These transceiver components share a common clock generator, which simplifies the circuit, is easy to design, and reduces the chip area. Second, each channel has an enabling unit to control the input of the clock, thus saving power. Third, the multi-sampling technology of the clock data restorer is achieved by digital technology, so not only can save electricity and can effectively reduce the area. In view of the above, the present invention has been described above with reference to a preferred embodiment. However, it is not intended to limit the invention, and any changes and effects can be made in the spirit and scope of the present invention.

1289760 V. INSTRUCTIONS (7) The scope of protection of the present invention is defined by the scope of the appended claims. 1^1135? (VIA).ptd Page 11 1289760

BRIEF DESCRIPTION OF THE DRAWINGS [Simplified Schematic] FIG. 1 is a block diagram of a conventional serialization/deserialization transceiver component. Figure 2 is a block diagram of a multi-lanes serial wiring device in accordance with a preferred embodiment of the present invention. Schematic Description 1 0 0 · Serialization/Deserialization Transceiver Element 120 122 124 140 142 144 146 200 220 231 241 251 253 Transmission Unit Transmission Clock Generator Transmitter Receiver Unit Receiver Clock Data Responder Clock Generation Multi-channel serial connection device serialization/deserialization (SERDES) transceiver component enabling unit transmitter receiver clock data restorer

Page 12 TW1135F (VIA).ptd

Claims (1)

1289760 6. Patent application scope 1. A multi-lanes serial connection device, including an eight-in-one pulse generator, generating at least one transmission clock and several receiving clocks; and a plurality of strings And de-serializing the transceiver component, each of the serialization/deserialization transceiver components is configured to serialize one of the transmission data to be transmitted according to any one of the transmission clocks, and output an output pair to the letter tiger, and According to the receiving clocks, one of the receiving signals is deserialized, and then a received data is output. The multi-channel tandem connection device described in the above-mentioned patent scope of the patent application, wherein the serialization/deserialization transceiver component comprises: The consistency unit determines whether to output the transmission clock and the reception clocks according to a transmission enable signal and a reception k-number; the threshold element is based on the transmission clock output by the enabling unit, After the transmission_beacon serialization process, the transmission pair signal is output; the r unit 'according to the received pair of received signals; and the received clocks, the received data is output. 3. The multi-channel tandem connection as described in claim 2, wherein the enabling unit comprises ··, " a first gate, which is determined according to the receiving enable signal . The multi-channel serial connection device described in the second paragraph of claim 2, wherein the enabling unit comprises: 'a first gate, determining whether to rotate the input according to the transmission enable signal Clock. ~ 5·Multi-channel tandem connection as described in item 2 of the patent application scope TW1135F (VIA). Ptd 1289760 6. Patent application range, wherein the receiving unit comprises: y a receiver' for receiving the received pair signal, de-serializing the output, and outputting a side-by-side data; And outputting the received data according to the parallel data and the receiving clocks that are turned on by the enabling unit. 6. The multi-channel tandem connection as described in claim 5, wherein the clock data restorer employs a multi-sampling technique. 7. The multi-channel tandem connection as described in claim 1 wherein the shared clock generator is a multi-phase phase-locked loop. 8 . A multi-channel serial connection method, controlled by a shared clock generator, comprising the steps of: providing at least one transmission clock and a plurality of receiving clocks, wherein the transmission clock is the same as the receiving clocks The shared clock generator generates; and transmits data to one of the transmissions, and performs a serialization process by using the transmission clock to generate a transmission pair signal, and receives one of the received signals to receive the clock signals After the deserialization process, a received data is generated. 9. The multi-channel tandem connection method as described in claim 8 wherein the number of received clocks is an integer multiple of the number of transmission clocks. 10. The multi-channel tandem connection method of claim 9, wherein the receive clocks multisample the one bit interval of the transmission pair signal. 11·Multi-channel serial connection party as described in item 8 of the patent application scope Η Page 14 TO135F (VIA). ptd 1289760 6. Patent application scope method, wherein the transmission clock and a plurality of receiving clocks respectively act on the transmission data and the receiving pair signal, respectively, by a first enabling signal and a The second enable signal is controlled. TW1135F (VIA).ptd第15页