TWI289760B - An apparatus of multi-lanes serial link and the method thereof - Google Patents
An apparatus of multi-lanes serial link and the method thereof Download PDFInfo
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Description
12897601289760
【發明所屬之技術領域】 本發明是有關於一 #志 方法,特別是-種多通道广+ 連線(seriai iink)裝置及 方法。 、道(multl —lanes)串列連線裝置及 【先前技術】 由於對資料傳輸有愈來愈高速的需求,使得原有> 列傳輸架構,例如pci年槿,P、豕W求使付原有之並 架構係使用多條連接線,曰命伙连丨—广J 亚夕j得輪TECHNICAL FIELD OF THE INVENTION The present invention relates to a #志方法, and more particularly to a multi-channel wide + seriai iink device and method. , multl-lanes serial connection device and [prior art] Due to the increasing speed of data transmission, the original > column transmission architecture, such as pci years old, P, 求W seeking to pay The original structure is the use of multiple connecting lines, and the squad is connected.
在尚速的資料傳輸下,對多條連接線; 步則是非常難以達成。 j 一般現行之高速傳輸係採用串列傳輸,例如是通用串 列匯流排(Universal Serial Bus,_)。以㈣ 2 〇 規格 的匯流排來說其係以480Mbits/s的速率進行傳輸,採用的 時脈係為240MHz。若要更高速率的傳輸,例如大於igHz 時,則需採用串化/解串化(serialize/de_seriaHze SERDES)收發元件(transceiver)。其中串化/解串化收發 元件例如是應用於PCI高速架構(PCI Express architecture) °Under the speed of data transmission, for multiple links; the step is very difficult to achieve. j The current high-speed transmission system uses serial transmission, such as Universal Serial Bus (_). In the (4) 2 规格 size bus, it is transmitted at a rate of 480 Mbits/s, using a clock system of 240 MHz. For higher speed transmissions, such as greater than igHz, serialization/de-seriaHze SERDES transceivers are required. The serialization/deserialization transceiver component is applied, for example, to a PCI Express architecture.
第1圖疋習知的串化/解串化收發元件方塊圖。串化/ 解串化收發元件100包括傳輸單元12〇及接收單元14〇,用 以分別進行傳輸信號及接收信號。上述串化/解串化收發 元件1 0 0之傳輸信號及接收信號的運作係以差動對 (differentially driven pair)的形式進行,如第丨圖上Figure 1 is a block diagram of a conventional serialization/deserialization transceiver component. The serialization/deserialization transceiver component 100 includes a transmission unit 12A and a reception unit 14A for respectively transmitting and receiving signals. The operation of transmitting and receiving signals of the serialization/deserialization transceiver component 100 described above is performed in the form of a differentially driven pair, as shown in the figure.
1289760 -*------- 五、發明說明(2) 所示77別為是傳輸對信號(transmit pair)TxP及ΤχΝ,與 接收對信號(receive pair)RxP &RxN。 口 其中’傳輸單元120包括由傳輸時脈產生器122及傳輸 器124構成。傳輸時脈產生器122產生傳輸時脈tCLK,並輸 出到傳輸器124。外部所輸入的資料t])ata,例如是電腦中 的以並列形式的資料。當傳輸器124接收到傳輸時脈tCLK 與並列的資料tData後,對並列的資料tData進行串化處 理’然後產生傳輸對信號ΤχΡ和ΤχΝ,而進行輸出的動作。 至於’接收單元1 4 0包括由接收器1 4 2及時脈資料回復 器(Clock Data Recovery Unit,CDR)144 構成。當接收器 142接到接收對信號RxP與RxN後,對接收對信號Rxp與RxN 進行解串化處理,再輸出至時脈資料回復器1 44。時脈資 料回復器1 44接收到解串化後之信號後與内部的一時脈產 生器146所產生的時脈信號,進行相關處理,例如使用相 位追蹤(Phase-tracking)方式來回復接收之信號的時脈及 資料,而輸出接收資料rData。 由於以串列連線之PCI高速架構與周邊裝置連接,往 往是使用多通道結構,即有多數個串列連線之通道方式同 時使用,來達到周邊裝置所需的收發速率。然而,在第ι 圖所示的一個通道所需的串化/解串化收發元件,須具有 兩組時脈產生器,因此對於一個多通道的列線則〃 更多個時脈產生器,如此將佔去相者 運線則需有 石和s大的晶片面積,並且 相當耗電而不經濟。1289760 -*------- V. Description of the invention (2) The 77 shown is the transmission pair TxP and ΤχΝ, and the receive pair RxP & RxN. The transmission unit 120 includes a transmission clock generator 122 and a transmitter 124. The transmission clock generator 122 generates a transmission clock tCLK and outputs it to the transmitter 124. The externally entered data t])ata, for example, is a parallel data in the computer. After the transmitter 124 receives the transmission clock tCLK and the parallel data tData, the parallel data tData is serialized and then the transmission pair signals ΤχΡ and 产生 are generated to perform an output operation. As for the 'receiving unit 1404', it consists of a receiver 1 4 2 Clock Data Recovery Unit (CDR) 144. After the receiver 142 receives the receive pair signals RxP and RxN, the receive pair signals Rxp and RxN are deserialized and output to the clock data restorer 1 44. After receiving the deserialized signal, the clock data recoverer 1 44 performs correlation processing with the clock signal generated by the internal clock generator 146, for example, using a phase-tracking method to reply the received signal. The clock and data, while the output receives the data rData. Since the PCI high-speed architecture connected in series is connected to peripheral devices, a multi-channel structure is often used, that is, a plurality of serial connection channels are simultaneously used to achieve the required transmission and reception rate of peripheral devices. However, the serialization/deserialization transceiver components required for a channel shown in Figure 1 must have two sets of clock generators, so for a multi-channel column line, more clock generators, In this way, it will take up the wafer area of the stone and s, and it is quite power-consuming and uneconomical.
1289760 五、發明說明(3) 【發明内容】 有鑑於此,本發明的目的 脈產生器的多通道(multiy ,疋在拎供一種可以共用時 根據本發明的目#,接屮列連線裝置及方法。 串列連線梦置,句iiitm 種多通道(multi-lanes) 收發元件:共用時脈產生與f個串化/解串化 輸資料串化處理後7T出時脈,將欲… 時脈,將接到的接收對_ #二° r,亚且依據此些接收 資料。 對“虎進行解串化處理後,輸出接收 脈產ί ί二:提t括;ί道串列連線方法,以-共用時 該共用時脈產生器產生;、妾罐^ 該傳輸時脈作用來進行串化處轰】 #輸貝料,以 並將接收之一接收料产咕 後產生—傳輸對信號, 接收對k號,以該些接收時脈作用來進行姐 串化處理後,產生#。 作用來進灯解 上述接收時脈數目係為該些傳輸時脈 得接收時脈對傳輸對信號之一個位元區間進:= 收對信號作用,分別由一第一致能信號與 控制,以達到省電的作用。 弟一致此l唬 懂,ίϊΙΓ月f上述目的、特徵、和優點能更明顯易 下文特舉-較佳實施例,並配合所附圖式,作詳細說 IHin^Sg 第7頁 TO135F(威盛).ptd 1289760 五、發明說明(4) ---- 明如下: 【實施方式] 兩速•構(PCI express architecture)係以串列 連線(serai 1 link)與周邊裝置連接。每個串列連線包括 至少一通道(lane),每個通道即為前述的串化/解串化收 發元件所控制。依據周邊裝置所需的收發速率而可以增加 通道數。 明參照第2圖’其繪示依照本發明一較佳實施例的一 種多通道串列連線裝置方塊圖。一個串列連線裝置可以設 計具有多個通道以增加對周邊裝置傳輸速率,例如有丨6個 通道的串列連線裝置即比有一個通道的串列連線裝置有快 16倍的傳輸速率。如第2圖所示,多通道串列連線裝置2〇〇 包括一個共用時脈產生器210及多個串化/解串化 (serailizer/de-serializer,SERDES)收發元件220。第2 圖示係以兩個通道的串列連線裝置為例做說明,然並不限 於僅有兩個通道。共用時脈產生器210產生傳輸時脈 tCLKl-m及接收時脈rCLKl-n,其中m與η為至少等於或大於 1之整數,以提供給各個SERDES收發元件220。各SERDES收 發元件2 2 0用以依據傳輸時脈t C L Κ1 - m,來將欲傳輸之並列 資料tData進行串化處理後,才輸出傳輸對信號TxP與 ΤχΝ。各SERDES收發元件220並且依據接收時脈rCLlU-η, 來將接收之差動對信號RxP與RxN進行解串化處理後,才輸 出資料rData。1289760 V. SUMMARY OF THE INVENTION (3) SUMMARY OF THE INVENTION In view of the above, the multi-channel (multiy) of the pulse generator of the present invention is provided in accordance with the present invention. And method. Serial connection dream, sentence iiitm multi-lanes (multi-lanes) transceiver components: shared clock generation and f serialization / deserialization data serialization processing 7T out of the clock, will want ... The clock will receive the receiving pair _ #二° r, and according to the receiving data. After the “de-serialization of the tiger, the output receives the pulse output ί ί 2: mention t; ί道串连连The line method is generated by the shared clock generator when the sharing is performed; the tank can be used to perform the serialization of the clock; and the one of the receiving materials is generated and transmitted. For the signal, the pair of k is received, and the receiving clock is used to perform the serialization process, and the # is generated. The effect of the incoming signal to solve the number of receiving clocks is to receive the clock-to-transmission pair of the transmission clocks. One bit interval of the signal: = the effect of the signal on the signal, respectively Signals and controls to achieve power saving. Brothers agree that the above objectives, features, and advantages can be more obvious. The following is a special example - the preferred embodiment, with the drawings, for details Said IHin^Sg Page 7 TO135F (VIA).ptd 1289760 V. Description of invention (4) ---- Ming as follows: [Embodiment] Two-speed configuration (PCI express architecture) is connected in series (serai 1 Link) is connected to the peripheral device. Each serial connection includes at least one lane, and each channel is controlled by the foregoing serialization/deserialization transceiver component. It can be increased according to the required transmission and reception rate of the peripheral device. Referring to FIG. 2, a block diagram of a multi-channel serial connection device according to a preferred embodiment of the present invention is shown. A serial connection device can be designed with multiple channels to increase transmission to peripheral devices. The rate, for example, a serial connection device with 6 channels is 16 times faster than a serial connection device with one channel. As shown in Fig. 2, the multi-channel serial connection device 2〇〇 A shared clock generator 210 is included A plurality of serializer/de-serializer (SERDES) transceiver components 220. The second diagram illustrates a two-channel serial connection device as an example, but is not limited to only two channels. The shared clock generator 210 generates a transmission clock tCLK1-m and a reception clock rCLK1-n, where m and n are integers at least equal to or greater than 1 to be supplied to the respective SERDES transceiver elements 220. Each SERDES transceiver element 2 2 0 is used to serialize the parallel data tData to be transmitted according to the transmission clock t CL Κ1 - m, and then output the transmission pair signals TxP and ΤχΝ. Each of the SERDES transceiver elements 220 outputs the data rData after the received differential pair signals RxP and RxN are deserialized according to the reception clock rCL1U-η.
TW1135F(威盛).ptd 第8頁 1289760TW1135F (VIA).ptd Page 8 1289760
各SERDES收發元件220包括致能單元231、傳輪器 2 41、接收器2 51及時脈資料回復器2 5 3。致能單元2 3^" 1分別 依據傳輸致能信號ΕΝΐ及接收致能信號Εηι·的控制,而決定 是否接收傳輸時脈tCLKl-m及接收時脈rCLKl-n。因此,若 SERDES收發元件220在無任何收或發的動作,則可利用傳 輸致能信號ENt及接收致能信號Enr來達到暫停供給時脈以 節省電源。其中,致能單元231可簡單設計成由及閘(and gate)Al與A2構成。及閘A1依據接收致能信號ENr決定是否 讓接收時脈rCLlU-η輸出至時脈資料回復器253。及閘A2依 據傳輸致能信號ENt決定是否讓傳輸時脈tCLin-m輸出。由 於致能單元231可以控制時脈的輸出,因此可以有效地節 省電源。Each SERDES transceiver component 220 includes an enabling unit 231, a wheel feeder 2 41, and a receiver 2 51 time-of-day data recovery unit 253. The enabling unit 2 3^" 1 determines whether to receive the transmission clock tCLKl-m and the reception clock rCLKl-n according to the control of the transmission enable signal ΕΝΐ and the reception enable signal Εηι. Therefore, if the SERDES transceiver component 220 does not have any receiving or transmitting action, the transmission enable signal ENt and the reception enable signal Enr can be used to suspend the supply of the clock to save power. The enabling unit 231 can be simply designed to be composed of AND gates A1 and A2. The gate A1 determines whether or not to output the reception clock rCL1U-η to the clock data restorer 253 based on the reception enable signal ENr. The gate A2 determines whether to transmit the transmission clock tCLin-m according to the transmission enable signal ENt. Since the enabling unit 231 can control the output of the clock, it is possible to effectively save power.
傳輸器241接收傳輸時脈tcLjn 與傳輸之並列資料 tData ’進行串化處理後,產生傳輸對信號ΤχΡ與ΤχΝ輸 出。接收器2 5 1接到接收對信號r χ ρ及r χ ν後,將他們轉為 並列資料’再輸出給時脈資料回復器2 5 3。時脈資料回復 器253 ’在此内部並不需要具有時脈產生器,因其利用共 用時脈產生器210所輸出的接收時脈rCLK丨―^,在配合致能 單凡231控制所傳送過來的接收時脈rCLK1—η與接收器251 ,送過來的並列資料,進行進行相關處理以回復接收之信 號的時脈及資料,而輪出接收資料rData。由於時脈資料 回復器2 5 3内部不具有時脈產生器,因此此可以有效降低 在晶片上的面積。 8守脈> 料回復器253係採用多重取樣(〇ver— sampling)The transmitter 241 receives the transmission clock tcLjn and the transmitted parallel data tData ', and generates a transmission pair signal ΤχΡ and ΤχΝ output. After receiving the pair signals r χ ρ and r χ ν, the receiver 2 5 1 converts them into parallel data and outputs them to the clock data recoverer 2 5 3 . The clock data restorer 253' does not need to have a clock generator internally because it utilizes the receive clock rCLK丨-^ output by the shared clock generator 210, and is transmitted by the control unit 231 control. The receiving clock rCLK1_n and the receiver 251 send the parallel data, perform correlation processing to reply the clock and data of the received signal, and rotate the receiving data rData. Since the clock data recovery unit 2 5 3 does not have a clock generator inside, this can effectively reduce the area on the wafer. 8 Guardian > Material Recoverer 253 is multi-sampling (〇ver-sampling)
1289760 五、發明說明(6) ,技術’因此需要多種相位的接收時脈rCLlU-η,也就是 操作時在個位元區間中進行多次取樣,然後再據以決定 此位π的内容為1或〇。由於過取樣技術係為數位式,因此 可以很方便以較小的面積設計於晶片中,並且有較佳的準 確性。此外’共用時脈產生器210產生傳輸時脈tCLm-m及 接收時脈rCLIH-n例如是可產生多種相位時脈的鎖相回路 (multi phase phase l〇ck l〇〇p),可同時產生至少3〇一40 個不同相位的時脈。配合時脈資料回復器253係採用多重 取樣的技術,因此需要多種相位的接收時脈rCLk,例如在 此處我們可以設定n = 3m,表示共用時脈產生器2丨〇產生一 個傳輸時脈tCLKl,則同時有3個對應不同的接收時脈 rCLK 1-3產生,使得時脈資料回復器253内部會對一個位元 區間中則進行三次取樣。 本發明上述實施例所揭露之多通道串列連線裝置具 以下優點: 一、 此些通運的收發元件係共享一個共用時脈產生 器,可以簡化電路,易於設計,並縮小晶片面積。 二、 各通道具有致能單元以控制時脈的輸入,因此 以省電。 三、 利用多重取樣技術的時脈資料回復器,係為數位 技術達成,因此不但可以省電且可有效減小面積。 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明,任何熟習此 本發明之精神和範圍内,當可作各種之更動與潤t =1289760 V. Inventive Note (6), the technology 'requires a multi-phase receiving clock rCLlU-η, that is, multiple sampling in one bit interval during operation, and then determines the content of this bit π as 1 Or 〇. Since the oversampling technique is digital, it can be easily designed in a small area with a small area and has better accuracy. In addition, the shared clock generator 210 generates the transmission clock tCLm-m and the reception clock rCLIH-n, for example, a phase-locked loop (multi phase phase l〇ck l〇〇p) that can generate a plurality of phase clocks, which can be simultaneously generated. At least 3 to 40 clocks of different phases. With the clock data recovery device 253 is a multi-sampling technique, so the receiving clock rCLk of multiple phases is required. For example, we can set n = 3m here, indicating that the shared clock generator 2 generates a transmission clock tCLKl. At the same time, three corresponding receiving clocks rCLK 1-3 are generated, so that the clock data recoverer 253 internally samples three times in one bit interval. The multi-channel tandem wiring device disclosed in the above embodiments of the present invention has the following advantages: 1. These transceiver components share a common clock generator, which simplifies the circuit, is easy to design, and reduces the chip area. Second, each channel has an enabling unit to control the input of the clock, thus saving power. Third, the multi-sampling technology of the clock data restorer is achieved by digital technology, so not only can save electricity and can effectively reduce the area. In view of the above, the present invention has been described above with reference to a preferred embodiment. However, it is not intended to limit the invention, and any changes and effects can be made in the spirit and scope of the present invention.
1289760 五、發明說明(7) 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 1^1135?(威盛).ptd 第11頁 12897601289760 V. INSTRUCTIONS (7) The scope of protection of the present invention is defined by the scope of the appended claims. 1^1135? (VIA).ptd Page 11 1289760
圖式簡單說明 【圖式簡單說明】 第1圖是習知的串化/解串化收發元件方塊圖。 弟2圖繪示依照本發明一較佳實施例的一種多通道 (multi-lanes)串列連線裝置方塊圖。 圖式標號說明 1 0 0 ·串化/解串化收發元件 120 122 124 140 142 144 146 200 220 231 241 251 253 傳輸單元 傳輸時脈產生器 傳輸器 接收單元 接收器 時脈資料回復器 時脈產生器 多通道串列連線裝置 串化/解串化(SERDES)收發元件 致能單元 傳輸器 接收器 時脈資料回復器BRIEF DESCRIPTION OF THE DRAWINGS [Simplified Schematic] FIG. 1 is a block diagram of a conventional serialization/deserialization transceiver component. Figure 2 is a block diagram of a multi-lanes serial wiring device in accordance with a preferred embodiment of the present invention. Schematic Description 1 0 0 · Serialization/Deserialization Transceiver Element 120 122 124 140 142 144 146 200 220 231 241 251 253 Transmission Unit Transmission Clock Generator Transmitter Receiver Unit Receiver Clock Data Responder Clock Generation Multi-channel serial connection device serialization/deserialization (SERDES) transceiver component enabling unit transmitter receiver clock data restorer
第12頁 TW1135F(威盛).ptdPage 12 TW1135F (VIA).ptd
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TWI332757B (en) | 2006-06-14 | 2010-11-01 | Realtek Semiconductor Corp | Circuit and method for reducing mismatch between signal converters |
US20150032931A1 (en) * | 2013-07-26 | 2015-01-29 | Broadcom Corporation | Synchronous Bus Width Adaptation |
JP6303513B2 (en) * | 2014-01-14 | 2018-04-04 | 富士通株式会社 | Multilane retimer circuit and multilane transmission system |
CN114503454A (en) * | 2019-09-27 | 2022-05-13 | 华为技术有限公司 | Wireless transceiver integrated with common clock phase-locked loop |
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US4963839A (en) * | 1989-09-01 | 1990-10-16 | Westinghouse Electric Corp. | Wide bandwidth phase locked loop circuit with sliding window averager |
AU627953B2 (en) * | 1989-11-15 | 1992-09-03 | Digital Equipment Corporation | Integrated communications link having dynamically allocatable bandwidth and a protocol for transmission or allocation information over the link |
US5714904A (en) * | 1994-06-06 | 1998-02-03 | Sun Microsystems, Inc. | High speed serial link for fully duplexed data communication |
US6259693B1 (en) * | 1997-08-28 | 2001-07-10 | Ascend Communications, Inc. | Cell combination to utilize available switch bandwidth |
JP3109588B2 (en) * | 1998-03-12 | 2000-11-20 | 日本電気株式会社 | Oversampling type clock recovery circuit |
KR100371300B1 (en) * | 1999-06-21 | 2003-02-06 | 샤프 가부시키가이샤 | Bit synchronizing circuit |
US6546496B1 (en) * | 2000-02-16 | 2003-04-08 | 3Com Corporation | Network interface with power conservation using dynamic clock control |
US7054310B1 (en) * | 2000-09-14 | 2006-05-30 | Ciena Corporation | Methods and apparatuses for providing multiple services from any slot in a SONET system having multiple slots |
US7200767B2 (en) * | 2002-12-27 | 2007-04-03 | Texas Instruments Incorporated | Maintaining synchronization of multiple data channels with a common clock signal |
-
2003
- 2003-07-07 TW TW092118534A patent/TWI289760B/en not_active IP Right Cessation
-
2004
- 2004-05-14 US US10/846,764 patent/US20050007966A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW200502771A (en) | 2005-01-16 |
US20050007966A1 (en) | 2005-01-13 |
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