200819771 九、發明說明： • 【發明所屬之技術領域】 — 本發明係提供一種晶片測試機制與相關方法，尤指一種 旎以低成本實現連接有一高速匯流排的晶片測試機制與相 關方法。 【先前技術】 • 在電子系統中，不同的電子裝置間會以匯流排來互相交 換資訊，使各電子裝置間能協調運作，將各自的功能整合 起來，達成電子系統的整體功能。舉例來說，在電腦系統 中’中央處理器會經由晶片組而橋接於其他各個周邊裝置 (像是硬碟機、光碟機、繪圖加速卡等尊），而中央處理器、 晶片組與各周邊裝置間就會以匯流排來互相連接，使上述 這些電子裝置能整合運作。當然，在講究效率的現代資訊 社會’對電子系統的效能要求也日益增高。為了增進電子 _ 系統的整體運作效能，除了要提高電子裝置各自的效能之 外，電子裝置間的匯流排也會以高速來運作，這樣才能更 快速地交換資訊，進而提升整體效能。譬如說，在覌代的 電腦系統中，晶片組會以高速的超速傳輸（Ητ， HyperTmnsport)匯流排來和中央處理器交換資料，以協助 提升電腦系統的整體效忐。在超速傳輸匯流排規格下，是 -配合舰以⑴如赠叫的日夺脈而以2孤 . 傳輸資料，以滿足匯流排的高速需求。 200819771 料，在生產間能正常地經由高逮匯流排交換資 介面收發資訊。當地經由其高速匯流排 時，是以外接的測試器直』=謂嫌出:功; 面收發測試資1 、甩衣置的尚速匯以1排；丨 當要測試-且^以測試電子裝置的輸出入功能。譬如說， 入功能時，速傳輸輕排介面魏㈣片組的輸出 片組的高逮匯術中，係將—外接的測試器連結到晶 流排介面電路向測：如此晶片組便 高速匯流排介面電路：：：訊或由測試器接收資訊。若 訊不符，代表晶片纽:傳2貢訊與測試器實際接收到的資 正常運作；同理，若測試芯=(發出資訊的功能）無法 介面電路正常地接收解讀，不能被高速匯流排 正吊運作。根據此肋，就⑽__行輸^^試。 如前所逑，高速匯流排係已告、 因此若要實際測試電子裝置私目田廣泛使用的匯流排， 中，必須採用高速的外接高類二功：，在先前技術 排介面電路的高頻輸出’才能處理高速匯流 頻測試器非常昂貴，連帶地、=進二測試°然而，外接高 也就會居高不下。譬如說，、于衣置的生產、製造成本 晶片組，其測試器必須具備有卢】式/、有超速傳輪匯流排的 义理2GHZ高頻訊號（因為 200819771 超速傳輸匯流排是以2GHz來傳輸資料）的能力，但此種 • 南頻測試器的成本十分焉昂。 【發明内容】 本發明之目的，即是要提出一種晶片輸出入功能測試機 制及相關方法；本發明係在對晶片進行輸出入功能測試 時，通過建立輸出入功能測試的内回路，來測試晶片的輸 出入功能與時序，而不需使用外接高頻測試器。因此，本 ® 發明技術可大幅減少輸出入功能測試的成本，克服習知技 術的缺點。 本發明提供一種晶片測試機制，用以測試該晶片之輸出 入功能，其中該晶片一端連結有一高速匯流排，一端連接 至少一低速匯流排，該晶片測試機制包含有一核心電路， 用以主控一資料訊號存取之編碼/解碼；以及一高速匯流排 0 介面電路，連接於該核心電路與該高速匯流排間，包含有 一傳輸機制以及一接收機制，用以傳送該資料訊號至該高 速匯流排端，或接收由該高速匯流排端傳送過來之該資料 訊號；其中當測試該晶片時，於該高速匯流排介面電路中 建立一内迴路，使得一測試訊號可由該高速匯流排介面電 路之傳輸機制所傳輸，經由該内迴路而由談高速匯流排介 面電路之接收機制所接收。 200819771 本發明另外提供一種晶片測試方法，用以測試一晶片之 輸出入功能，其中該晶片一端連結一高速匯流排，一端連 結至少一低速匯流排，該方法包含如下步驟：首先，於該 晶片之傳輸機制與接收機制間建立一内迴路；而後用該晶 片之傳輸機制傳送一測試訊號；以及使得該測試訊號經由 該内迴路而由該晶片之接收機制所接收。 本發明亦提供一種晶片操作方法，該晶片一端連結有一 高速匯流排，該方法包含如下步驟：於該晶片之傳輸機制 與接收機制間建立一内迴路；當測試該晶片時，啟動該内 迴路之連結，使得一測試訊號可由該晶片之傳輸機制傳 輸，經由該内迴路由該晶片之接收機制接收；以及當正常 操作該晶片時，中止該内迴路之連結，使得該晶片之傳輸 機制可傳送資料訊號至該高速匯流排端，該晶片之接收機 制可由該高速匯流排端接收資料訊號。 【實施方式】 請參考第1圖；第1圖為一電子裝置10的電路架構示 意圖。電子裝置10包含有一高速匯流排介面電路12與一 核心電路14。電子裝置10可為一電子系統下的一個晶片， 譬如說是一電腦糸統中的晶片組’而南速匯流排介面電路 12使得電子裝置10可經由高速匯流排24而和其他電子裝 置（未繪出）交換資訊與訊號。核心電路Μ用來主控匯流 200819771 排存取的相關編碼/解碼與控制程序。舉例來說，在由高速 ' 匯流排24接收到存取要求後，核心電路14決定是否要回 、 應’並決定回應之時機等。高速匯流排24可為一超速傳輸 匯流排(Hyper Transport Bus)。高速匯流排介面電路12中 設有一傳輸電路16及一接收電路18，並以複數個揍墊電 路 TCLK、TCTL、TCAD0_TCAD7、RCLK、RCTL、 RCAD0_RCAD7形成一輸出入接墊模組，以分別經由高速 匯流排24發出或接收資料。其中，傳輸電路16及接收電 馨 路18分別用來實現實體層的訊號傳輸與接收功能。各接墊 .電路則實際連接於高速匯流排24,以使用高速匯流排規格 所制訂的電子訊號形式來收發訊號。 當電子裝置10要送出資料到高速匯流排24時，待傳輸 資料會經過核心電路14之編碼轉換，並經由傳輸電路16 將已進行編碼轉換之待傳輸資料轉變為高速匯流排24可 • 接受的電子訊號，再由各接墊電路TCLK、TCTL及 TCAD0-TCAD7發送至高速匯流排24。 在第1圖所示的電子裝置10中，核心電路14會將待 傳輸資訊編碼轉換為64位元-250MHz的資料訊號，並配合 一 8位元-250MHz的控制訊號及一 8位元-25〇]\^1^的時脈 訊號而將該待傳輸資料傳送至傳輸電路16。而傳輸電路16 中的並列至串列電路2〇就可將64位元-250MHz的資料訊 200819771 號轉換為8位元_2GHz的資料訊號，同時也將8位元 * _250MHz之控制訊號轉成1位元-20沿控制訊號，將8位 ' 元_250MHz之時脈訊號轉成1位元-1GH時脈訊號。因此控 制訊號、時脈訊號就能分別由接墊電路TCTL、TCLK發送 至尚速匯流排24 ;同時，8位元-2GHz的資料訊號也會分 別由8個揍墊電路tCAD0_TCAD7發送至高速匯流排24。 另一方面，當高速匯流排24上有一筆8位元-2GHz的 馨資料訊號要發送至電子裝置10時，該資料訊號同樣會和i 位元_1GHz的時脈訊號配合1位元_20沿的控制訊號一起 發送。這些1位元-1GHz時脈訊號、1位元-2GHz控制訊號 與8位元-2GHz的資料訊號會經由高速匯流排24發送至電 子裝置10。鬲速匯流排介面電路12上的接塾電路rclK、 RCTL及RCAD0_RCAD7會分別接收上述之丨位元·iGHz 時脈訊號、1位元_2GHz控制訊號以及8位元-2GHz的資料 _ 訊號。而接收電路18中的並列至串列電路22就能將1位 το -1 GHz時脈訊號、i位元_2GHz控制訊號轉變為8位元 -25〇MHz之時脈訊號與控制訊號，而原本的8位元-2GHz 訊號也會被轉變為32位元-250MHz訊號。這些訊號會回傳 至核心電路14，由核心電路14解碼、解讀，使電子裝置 1 〇能接收到其他電子裝置經由高速涯流排24傳來的資气。 铢 、 為了要確保電子裝置10的正常運作，在生產製造電子 200819771 裝置ίο時，勢必要對電子裝置1〇進行輸出入功能測試， - 以測試電子裝置10是否能正確地收發符合高速匯流排規 …格的訊號。 不過，由於電路架構上的限制，當要對電子裝置10進 行輸出入功能測試時，必須要以外接高頻測試器連接於高 速匯流排介面電路12的各輸出入接墊電路tclk、TCTL、 TCAD0-TCAD7、RCLK、RCTL·、RCAD0-RCAD7^^^上 收發南頻訊號，並藉此來瞭解電子裝置1〇的輸出入功能是 否可正常運作。然而，如前所述，上述這些接墊電路所形 成的匯流排輸出入介面會以1GHz、2GHz的高頻來進行高 速的訊號收發，故習知輸出人功能測試技術也只能在高 頻、高速環境下才能進行輸出入功能測試。但理想的高頻 測試環境不易建立，且所使用的高頻測試器十分昂貴，連 帶地也使傳統電子裝置10的成本提高。 ' >因1’本發明提出一種晶片輸出入功能測試機制及相關 方法，用以測試具有高速匯流排介面的電子裝置。 第2圖為本發韻提供之—電子裝置列之—第—每 例的電路示意圖。電子裝置30可為-電子系統Μ 二，譬如，是一電腦系統中的晶片級。電子裝置30 _ -南速匯流排介面電路32與一核心電路％。其中，該: 11 200819771 速匯流排介面電路32用來使電子裝置3〇可經由高速匿流 • 排46而和其他電子裝置(未繪出）交換資料與訊號。高速 • 匯流排46可為一超速傳輸匯流排，使晶片組之電子裝置 30可經由高速匯流排46和中央處理器（未圖示）交換資 料。核心電路34用來主控匯流排存取的相關編碼/解碼與 控制程序。 高速匯流排介面電路32中設有一傳輸電路36、一接收 馨 電路38，以及由輪出入揍墊電路TCLK、TCTL、 TCAD0-TCAD7、RCLK、RCTL、RCAD0-RCAD7 形成之 一接墊模組，用以分別在高速匯流排46上發出或接收資 料。其中，傳輸電路36及接收電路38分別用來實現訊號 之傳輸與接收功能。 中在第2圖中所圖示的電子裝置30中，假設高速匯流 _ 排介面電路32為一超速傳輸匯流排介面電路，則其核心電 路34會依據超速傳輸匯流排的規格而提供一對應的64位 元-250MHz 綜合訊號（係為一 cAD(Command_Address_Data) 訊號），並配合一 8位元_25〇MHz控制訊號及一 8位元 -250MHz時脈訊號來代表待傳輸資料。而傳輸電路％中的 並列至串列電路40就可將64位元-250MHz的綜合訊號轉 換為8位元-2GHz的综合訊號，同時也將8位元_25〇]^1^ .之控制、時脈訊號分別轉變為1位元-2GHz控制訊號與1 12 200819771 位元-1GHz時脈訊號。 . 另一方面，接收電路38中的串列至並列電路42則可由 一接收埠48接收8位元-20!^的综合訊號、1位元-2〇1^ 控制訊號與1位-1GH時脈訊號，並將這些訊號分別轉換為 64位元-250MHz的綜合訊號、8位元_250MHz的控制訊號 與8位元-250MHz的時脈訊號，再將這些轉換後訊號回傳 至核心電路34,由核心電路34解讀這些訊號所代表的資訊。 馨 至於各接墊電路 TCLK、TCTL、TCAD0-TCAD7、 RCLK、RCTL、RCAD0-RCAD7則實際連接於高速匯流排 46，以便用高速匯流排規格所制訂的電子訊號形式來收發 訊號。 譬如說，在超速傳輸匯流排規格下，匯流排是以差動 φ 形式的訊號来攜載資訊的；在此種匯流排規格下，每一個 輸出接墊TCLK、TCTL、TCAD0-TCAD7電路可分別在匯 流排46上具有兩個連接端點（兩個針腳），以一對互為反 相的差動訊號來傳輸1位元的訊號。而TCLK、TCTL及 TCAD0-TCAD7就可向匯流排46分別發出1位元時脈訊 5虎、1位元控制訊號及8位元的綜合訊號。相對地，各輸 入接墊電路RCLK、RCTL及RCAD0-RCAD7則可由匯流 排46上分別接收差動形式的訊號，每一接墊電路可由一對 13 200819771 差動訊號中取出一位元的訊號。而各輸入接墊電路 ’ RCLK、RCTL及RCAD0-RCAD7接收的訊號就分別成為工 '位元時脈訊號、1位元控制訊號及8位元綜合訊號。在超 速傳輸S流排規格下，控制訊號可甩來指減合訊號中各 訊息所代表的性質，時脈訊號則用來指示控制訊號及综合 ail號的日卞序g如说，當控制訊號觸發(assert)時，代表综 合訊號中攜載的是控制指令及相關資料位址（譬如說是要 馨從某一貧料位址要求資料之存取）；當控制訊號不觸發 (de-assert)時，代表綜合訊號中攜載的是資料。 為了實現本發明的輸出入功能測試技術，本發明所提供 之咼速匯流排介面電路32在傳輸電路36/接收電路38之間 係形成一内迴路，使得由傳輪電路36中所發出的訊號經過 ㈣路可由接收電路38所接收。另外接收電路38設有一 多工模組50,經由該多工模組5〇的控制，高速匯流排介 •面電路32可選擇由高速匯流排弘接收資訊，或是由内迴 路接收傳輸電路36所發出的資訊。 在第2圖的實施例中，由於傳輸電路36發出的資訊 DATA1包含有時脈訊號CLK、控制訊號CMD及綜合訊號 CAD ’故内迴路會將這三種訊號接迴路至接收電路％。而 . 接收％路38中的多工模組50包含有多工電路muxi、mux2 ， 及mux3用來分別切換由傳輸電路過來之資訊data或是 14 200819771 由高速匯流排46經過接墊電路所傳送之資訊〇^，。其 - 中工電路咖外可切換使接收璋48選擇性地接收 -電路36傳送的综合訊號CAD，或是由輸入接塾電路输 RCAD0-RCAD7所接收到的綜合訊號CAD，。乡工電略 nrnx2可切換使接收埠48選擇性地接收傳輸電路％傳送 控制訊唬CMD，或是由輸入接墊電路RCTL所接收到的萨 脈訊號CMD，。多工電路聰3可切換使接收璋48選擇^ 地接收傳輸電路36傳送的時脈訊號CLK，或是由輸入接墊 電路RCLK所接收到的時脈訊號CLK，。 利用上述的内迴路’本發明就可在高速匯流排介面電路 32中直接進行電子裝置3〇_出入功能測言式，不需使用 外接的高頻測試器。 在進行本發明之輸出入功能測試時，接收電路38中的 夕工模組5〇 (包括多工器muxl_mux3)可切換使傳輸電路 36所發送之資訊D ATA(包括時脈訊號CLK、控制訊號CMD 及练合讯唬CAD)經由内迴路傳輸至接收電路的接收 埠48之後再比較傳輸電路％所發送之資訊與接收電路 38所接收到的資訊，就可以測試出電子裝置3〇的輸出入 功能。 當尚速匯流排介面電路32要進行一般運作時，多工模組5〇 15 200819771 就可終止内迴路的連接，使傳輸電路38之接收琿48能正常地藉 • 各輸入接墊電路rCLK、RCTL及RCAD0-RCAD7而接收高速 、 匯流排46上的資訊。 經由内迴路進行輸出入功能測試，本發明就可以直接從 核心電路34的低頻階層直接測試傳輸電路36與接收電路 38的高頻輸出入功能，不需使用成本高昂的外接高頻測試 •器來從高頻的匯流排輸出入端測試高頻的匯流排輸出入功 能。以第2圖的例子來說，在超速傳輸匯流排規格下，雖然傳輸 電路36/接收電路38發送/接收的時脈訊號具有1GHz的高頻 率，且控制訊號/綜合訊號頻率更高達2GHz，然而，高速 匯流排介面電路32僅需以100MHz ( 1MHz=106Hz)的低 頻時脈觸發。高速匯流排介面電路32在接受100MHz的低 頻時脈觸發後，核心電路34就能以250MHz的頻率與傳輸 電路36和接收電路38交换資訊（也就是250MHz的時脈 _ 訊號、控制訊號與綜合訊號），而傳输電路36和接收電路 38也就能以1GHz時脈訊號與2GHz控制訊號、綜合訊號 來收發麗流排46上的資料。因此，本發明僅需以1 的測試環境，就可經由核心電路34的運作來確認傳輸電路 36、接收電路38是否能正確地進行2GHz的高頻輸出入功能。 - 在習知的輸出入功能測試技術中，習知技術必須在高速 ， 匯流排介面電路對外的匯流排輸出入端以外接高頻測試器 16 200819771 來收發2GHz資料’故其測試器必須要能處理2GHz電子訊 -號，且成本十分高昂。相較之下，由於本發明所提^之^ -速匯流排介面電路32中設有内迴路，故本發明之電子擎^ 30可在核心電路34以100MHz來觸發輸出入功能測& 進仃，在核心電路34的控制下，核心電路34可使傳輪電 路36發出特定資訊’並從接收電路％回傳至核心電路^ 的資訊中驗證接收電路38是否能正確地接收到該特定資 鲁訊。換句話說’利用本發明所提供之電子裝置3〇，僅需在 核心電路34的1〇〇河沿低頻階層即可驗證傳輸電路3=與 接收電路38的2GHz高頻/高速輪出入功能是否正常。而' 100MHz的低頻測試環境所耗費的成本低廉，使得本發明 所提供之電子裝置能在低成本的條件下完成高頻輸出入功 能測試。 此外，本發明還可藉由更低頻的匯流排介面來控制高 _ 頻匯流排介面電路的輸出入功能測試。 由於晶片組要橋接高速中央處理器及其他的低速周邊 裝置’故在晶片組上不僅會設置高頻的超速傳輸匯流排， 也會設置低頻的匯流排，像是33MHz的PCI ( Peripheral Communication Interconnect)匯流排。當要對超速傳輸匯 ， 排之介面電路進行輸出入功能测試時，根據本發明所提 供之電子裝置30之一第二實施例，可經由低速的Ρα匯流 17 200819771 排將測試用的資料傳輸至晶片組，使晶片組能依據測試資 - 料測試超速傳輸控制匯流排之介面電路的輸出入功能。 第3圖為本發明所提供之電子裝置如之弟一實施例的 示意圖，其中電子裝置30可為〆晶片組，並另外設有一低 速匯流排52。請注意，低速匯流排52可為33MHz的PCI 匯流排。本發明所提供之電子裝置3〇可經由低速匯流排 52而對電子裝置30包含之高速匯流排介面電路32進行高 _ 速的輸出入功能測試。在對高速匯流排介面電路32進行輸 出入功能測試時，本發明所提供之電子裝置30可經由低速 匯流排52將測試用的資料（可稱為測試向量）輸入至晶片 組（即電子裝置30)，而此測試資料可以是一讀取要求指 令，要求電子裝置30從高速匯流排46上讀取某一位址的 資料。輸入至電子裝置30的測試資料會經由橋接電路54 而傳達至核心電路34，而該核心電路34就會發出對應的 2 5 0MHz時脈訊號、控制訊號及綜合訊號至高速匯流排介 面電路32，連帶地，高速匯流排介面電路32中的傳輸電 路36也就會發出1GHZ/2GHZ的時脈/控制/綜合訊號。 傳輸電路36發出的時脈/控制/綜合訊號會經由内迴路 回傳至接收電路38的接收埠48，再形成25_z的時脈/ .控制/綜合訊號並_至核心電路34。如果傳輸電路％、 接收電路38的輸出入功能皆運作正常，核心電路34應能 200819771 解讀出一上傳(upstream)的讀取要求指令。核’心電路34的 — 解讀結果可經由橋接電路54及低速匯流排52(在使用頻率 乂 為33MHz的狀況下）輸出。比較此回傳之測試資料是否符 合先如輸入之測试負料’就能確認電子裝置3 0的輸出入功 ... . · 能是否正常，亦即確認高速匯流排介面電路32是否可以正 確的收發高頻訊號。 . - ： - 癱 在第3圖所示之電子裝置3〇的第二實施例所應用輸出 入功能測試機制下，本發明可直接採用33MHz的低頻測試 環境來操控高速匯流排（即超速傳輪匯流排）的輸出入功 能測試，等效上，也就是在低頻測試環境下完成高頻的高 速匯流排輸出入功能測試。也因此，本發明可以降低高速 匯流排輸出入功能測試的測試環境要求，大幅減少高速匯 流排輸出入功能測試的成本，使高逮匯流排的高效能可普 遍為大眾所蓮用。 • 需要強調的是，本發明所提供之電子裝置3〇的第二實 施例雖是在低頻測試環境下進行電子裝置30的高速匯流' 排输出入功能測試，但電子裝置3〇的高速匯流排介面電路 32會實際運作於-般所定義之高頻，故本發明能真正測試 到高速匯流排介面電路32的高頻輪出入功能。如第2圖、 ' 第3圖中所圖示之電子裝置30的第一實施例與第二實施 * 例’本發明可在100MHz或是33MHz的環境下測試2GHz 19 200819771 超速傳輸匯流排的而速匯流排介面電路32。雖然測試環境 ， 是100ΜΉΖ或是33MHz等低頻的測試環境，但高速匯流排 . 介面電路32中的傳輸電路36/接收電路38實際上是以 2GHz的高頻來收發資料，故本發明能真正地以一般高頻運 作之標準來測試電子裝置30的高頻輪出入功能與效能。 另一方面，在以上述輸出入功能測試確認傳輸電路36 與接收電路38的輸出入功能後，本發a月可進一步测試各輸 ® 出入接墊電路 TCLK、TCTL、TCAD0-TCAD7、RCLK、 RCTL、RCAD0-RCAD7的功能。基本上，由於這些接墊電 路的功能僅是跟隨傳輸電路36與接收電路38的訊號運 作，故可以用降頻的方式來測試。譬如說，在測試輸出接 墊電路TCLK、TCTL及TCADO-TCAD時，可使傳輸電路 36向這些接墊電路發出2〇〇mhz之時脈/控制/綜合訊號， 並在接墊電路TCLK、TCTL及TCAD0-TCAD7與匯流排端 _ 46連接的一端接收這些揍墊電路所發出的訊號，以測試這 些接墊電路是否能正確地依據傳輸電路36傳輸至各接墊 電路的訊號向匯流排46發出對應的差動訊號。同理，在測 試各輸入接墊電路RCLK、RCTL及RCAD0-RCAD7時， 也可以使用較低頻的訊號來測試各輸入接墊電路的接收功 旎。這樣一來，就能完成對高速匯流排介面電路32的完整 ，輸出入功能測試。 20 200819771 由於本發明能在低頻測試環境下以高速匯流排介面電 ^ 32中的内迴路來進行電子裝置3〇高速的輸出入功能測 "式故本發明能在晶圓階段就直接對未切割、未封褒的電 子裝置（晶片）進行輸出入功能測試。如熟悉本發明所屬 =域者所週知，在晶圓擬即可由探輕制技術來對 晶圓上的電路進行功能測試’但此種探測技術同樣有運作 頻，均限制。若要以此制技術來直接收發2GHz的高 頻^ ’顯然有技術上的困難’也需要昂貴的測試環境與 ' 相車乂之下，本發明能直接運用現行的低成本低頻探 測技=來完成高速輸出人功能測試。在晶圓階段進行輸出 ^功^収以在早期就將故障的晶片篩選出來，不必對這 :故障曰曰片進行後續的封裝測試，可進一步節省晶片的產 製成本田然，針對已經完成封裝之晶片，仍然可以利用 本I月所提供之電子裝置3〇包含之高速匯流排介面電路 32應用之内迴路技術來進行輸出入功能測試。 士對阿逮匯流排上所傳輸的高頻訊號來說，各訊號間的相 互了序/相位關係與秩序是非常重要的。例如在第2圖所示 電 裝署^ 3 0 ίΑ 、 的弟一實施例中，控制訊號與時脈訊號應維 、有疋的相位關係；同樣地，各綜合訊號與時脈訊號間 也應維持-定的她_。 請參考第4圖 以接墊電路TCLK、TCTL與1^八00-10)八7 21 200819771 上的時脈訊號、控制訊號與綜合訊號為例子，第4圖係為這此 v 〇 • 在超速傳輪匯流排的規格下，1GHz的時脈訊號（第4圖中 標記為TCLK)具有1000ps (lps=i〇12秒）的週期，時脈 訊號中每隔半週期（ 500ps)的升緣與降緣可分別在控制訊 號（抓δ己為TCTL)與各綜合訊號（標記為TCAD[7:0])中 觸發一筆資料，故控制訊號、综合訊號為2GHz#訊號。 響 如^習本發明所屬之領域者所週知，為了要能觸發穩定的 訊號及資料取樣，時脈訊號的升緣與降緣應該要避開控制 訊號及綜合訊號的訊號轉變處。如第4圖中所示，在理想 狀況下，時脈訊號的升緣/降緣與控制/綜合訊號的訊號轉變 處之間應有1/4週期（也就是250ps)的時間差（也就是相 位差）。當然，在實際實作時，時脈訊號與控制訊號/綜合 訊號間還是可以容忍一定程度的時序扭曲（skew)。譬如 說，若時脈訊號之升/降緣與理想狀況下的升/降緣有50ps _ 的時間差，則其時序扭曲程度應該還在可容忍範圍内。但 若時脈訊號之升/降緣與控制訊號/綜合訊號之間有不正常 的過度時序扭曲（譬如說，時脈訊號之升/降緣與理想狀況 下的升/降緣有lOOps以上的時間差），時脈訊號之升/降緣 就會太接近控制訊號/综合訊號的訊號轉變處；這樣一來， 就難以在匯流排上正確地傳遞資訊了。 _ 在本發明中，當傳輸電路36運作時，傳輸電路36可依 22 200819771 據上述描“在時脈訊號㈣㈣制帛合訊賴維 的相互時序/相位。同理，接收電路38亦可依據適: 互時序/相位而運作。連帶地，在對高速匯流排介面電 的傳輸電I%/接㈣路3S進行輸“魏賴時，、則 壞境不可在傳輸電路/接收電路的各訊號間引入額外的日^ 間差（也就是時序扭曲）。若在對傳輸電路/接收電路進_ 輸出入功能測試時’測輯境本身在各相關訊號（也就: 時脈訊號與控制訊號/綜合訊號）中引入額外的時序扭曲疋 就無法正確地反映傳輸電路/接收電路的運作情形，使轸也 入功能測試失去其作用。^ ^ ^ ^ , 由於本發明是以高速匯流排介面電路32内的内迴路 來構築測試環境，故本發明之測試環境能比較容易地顧及 各訊號（時脈訊號、控制訊號/综合訊號）間的時序平衡， 避免在各訊號間引入不必要的時間差。相較之下，若是以 肇 外接測試器在高速匯流排介面電路32之外（也就是在各輸 出入接墊電路與匯流排連接之處）形成外迴路而進行輸^ 入功能測試，就非常容易在各訊號間引入額外的時間差。 如熟習本發明所屬之領域者所週知，當要傳輸高頻訊號 時，高頻訊號會受訊號傳輸路徑上的俸輸線影響；若不同 訊號在長度/特性有差異的不同傳輸路徑上傳輸，就會在不 ‘ 同訊號間引入額外的時間差。因此，要以外接電路來布置 • 一個良好的高頻外迴路測試環境是非常困難的。相較之 23 200819771 下，本發日月是在高速匯流排介面電路32内布置了内迴路以 - 輔助輸出入功能測試’故可充分的減少傳輪路徑對於各訊號的影 c 響’為南速匯流排的南頻輸出入訊號提供較隹的、、則1广产 第5圖示意的是第2圖所示之電子裝置30進行一般運 作時的情形。當輸出入功能測試結束，且電子裝置3〇要進 行一般運作時，多工模組50會切斷内迴路（故在第5圖中 癱以虛線表示），使接收電路38能正常地由各輸入接塾電路 RCLK、RCTL與RCAD0_RCAD7接收由高速匯流排省傳 來的時脈訊號/控制訊號/综合訊號，而停止由内迴路接收傳 輸電路36所發出的時脈訊號/控制訊號/綜合訊號。 總結來說’相較於先前技術在電子裝置上外接高頻輪出 入功能測試機制，本發明係在電子裝置（例如：晶片）的高 速匯流排介面電路中設置内迴路，藉由高速匯流排介面^ _路中低頻核心電路的運作，以内迴路來進行高頻傳輪電路/ 接收^的輸出入功能測試。因此，本發明能運用低頻的 測忒％丨兄来几成電子裝置的高頻輸出入功能測試，以降低 測。式的成本。本發明輸出入功能測試技術不僅能運用於封 衣儿成的日日片，還能在晶片未切割、未封裝時就進行早期 的兀整輸出入功能測試，進一步節省後續處理的時間與成 '本。另外要說明的是，雖然第2圖至第5圖是以8位元寬 聲 度又8位疋综合資料）與超速傳輸匯流排規格之高速匯流 24 200819771 上jL -t* v l -*v>___200819771 IX. Description of the Invention: • [Technical Field of the Invention] The present invention provides a wafer testing mechanism and related methods, and more particularly to a wafer testing mechanism and related method for connecting a high speed bus bar at a low cost. [Prior Art] • In an electronic system, different electronic devices exchange information with busbars, so that electronic devices can operate in coordination, and integrate their functions to achieve the overall functions of the electronic system. For example, in a computer system, the central processing unit is bridged to other peripheral devices (such as a hard disk drive, a CD player, a graphics accelerator card, etc.) via a chipset, and the central processing unit, the chipset, and the peripherals. The devices are connected to each other by busbars, so that the above electronic devices can be integrated. Of course, in the modern information society where efficiency is concerned, the efficiency requirements for electronic systems are also increasing. In order to enhance the overall operational efficiency of the electronic system, in addition to improving the respective performance of the electronic devices, the busbars between the electronic devices will also operate at a high speed, so that information can be exchanged more quickly, thereby improving overall performance. For example, in the computer system of the Sui Dynasty, the chipset will exchange data with the central processor with a high-speed ultra-speed transmission (Ητ, HyperTmnsport) bus to help improve the overall efficiency of the computer system. Under the specification of the overspeed transmission busbar, it is - cooperate with the ship to transmit data to meet the high-speed demand of the busbar by (1) if the gift is called the day of the pulse. 200819771 It is expected that information can be sent and received normally through the high-frequency bus exchange interface between productions. When the local high-speed bus is connected via the high-speed bus, it is an external tester. ??? 嫌 : : 功 功 功 谓 : : 功 功 功 功 功 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面The output function of the device. For example, in the high-capture operation of the output film set of the fast transmission light-distribution interface Wei (four) chipset, the external tester is connected to the crystal flow channel interface circuit test: the chip set is high-speed bus Interface circuit::: or receive information from the tester. If the information does not match, on behalf of the chip New Zealand: pass 2 Gongxun and the tester actually received the normal operation of the capital; similarly, if the test core = (the function of sending information) can not interface the circuit to properly receive the interpretation, can not be high-speed bus Hang operation. According to this rib, the (10)__ line is tested. As mentioned before, the high-speed busbar system has been reported, so if you want to actually test the busbars that are widely used in the private field of electronic devices, you must use high-speed external high-class two-function: the high-frequency of the circuit in the prior art The output 'can handle the high-speed bus frequency tester is very expensive, with the ground, = two test. However, the external high will also remain high. For example, in the production and manufacturing cost of the clothing set, the tester must have a high-efficiency 2GHZ high-frequency signal with a speed-transmitting bus (because the 200819771 ultra-fast transmission bus is transmitted at 2GHz). The ability to data, but this • The cost of the IF tester is very high. SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer input-input function testing mechanism and related method; the present invention tests a wafer by establishing an inner loop of an input-output functional test when performing an input-output functional test on a wafer. The input and output functions and timing, without the need for an external high frequency tester. Therefore, this ® technology can significantly reduce the cost of input and output functional testing and overcome the shortcomings of the prior art. The present invention provides a wafer testing mechanism for testing the input and output functions of the wafer, wherein one end of the wafer is coupled to a high speed bus bar, and one end is connected to at least one low speed bus bar. The chip testing mechanism includes a core circuit for controlling one Encoding/decoding of data signal access; and a high speed bus 0 interface circuit connected between the core circuit and the high speed bus, including a transmission mechanism and a receiving mechanism for transmitting the data signal to the high speed bus End, or receiving the data signal transmitted by the high speed bus terminal; wherein when testing the chip, an inner loop is established in the high speed bus interface circuit, so that a test signal can be transmitted by the high speed bus interface circuit The mechanism transmits, and is received by the receiving mechanism of the high speed bus interface circuit via the inner loop. 200819771 The present invention further provides a wafer testing method for testing an input/output function of a wafer, wherein one end of the wafer is coupled to a high speed bus bar and one end is coupled to at least one low speed bus bar. The method includes the following steps: First, the chip is An internal loop is established between the transmission mechanism and the receiving mechanism; then a test signal is transmitted by the transmission mechanism of the chip; and the test signal is received by the receiving mechanism of the chip via the inner loop. The present invention also provides a wafer operation method, the wafer is coupled to a high speed bus bar at one end, the method comprising the steps of: establishing an inner loop between the transfer mechanism and the receiving mechanism of the wafer; and when testing the wafer, starting the inner loop Linking, such that a test signal can be transmitted by the transfer mechanism of the chip, received by the receiving mechanism of the chip via the inner loop; and when the wafer is normally operated, the connection of the inner loop is suspended, so that the transfer mechanism of the wafer can transmit data The signal is sent to the high speed bus, and the receiving mechanism of the chip can receive the data signal from the high speed bus. [Embodiment] Please refer to FIG. 1; FIG. 1 is a schematic diagram showing the circuit architecture of an electronic device 10. The electronic device 10 includes a high speed bus interface circuit 12 and a core circuit 14. The electronic device 10 can be a chip under an electronic system, such as a chip set in a computer system, and the south speed bus interface circuit 12 allows the electronic device 10 to pass through the high speed bus bar 24 and other electronic devices (not Draw) exchange information and signals. The core circuit is used to control the associated encoding/decoding and control procedures of the 200819771 access. For example, after receiving the access request from the high speed 'bus bar 24, the core circuit 14 decides whether to return, should, and decide the timing of the response. The high speed bus 24 can be an overspeed transport bus (Hyper Transport Bus). A high-speed bus interface circuit 12 is provided with a transmission circuit 16 and a receiving circuit 18, and an input/output pad module is formed by a plurality of pad circuits TCLK, TCTL, TCAD0_TCAD7, RCLK, RCTL, RCAD0_RCAD7, respectively, for high-speed convergence Row 24 sends or receives data. The transmission circuit 16 and the receiving circuit 18 are respectively used to implement signal transmission and reception functions of the physical layer. Each pad. The circuit is actually connected to the high speed bus bar 24 to transmit and receive signals using the electronic signal format developed by the high speed bus bar specification. When the electronic device 10 is to send data to the high speed bus bar 24, the data to be transmitted is encoded and converted by the core circuit 14, and the data to be transmitted which has been encoded and converted is converted into the high speed bus bar 24 via the transmission circuit 16. The electronic signal is sent to the high speed bus bar 24 by the pad circuits TCLK, TCTL and TCAD0-TCAD7. In the electronic device 10 shown in FIG. 1, the core circuit 14 converts the information to be transmitted into a 64-bit-250 MHz data signal, and cooperates with an 8-bit-250 MHz control signal and an 8-bit-25. The data to be transmitted is transmitted to the transmission circuit 16 by the clock signal of 〇]\^1^. The parallel-to-serial circuit 2 in the transmission circuit 16 converts the 64-bit-250 MHz data signal 200819771 into an 8-bit-2 GHz data signal, and also converts the 8-bit*_250 MHz control signal into The 1-bit-20 along the control signal converts the 8-bit_250MHz clock signal into a 1-bit-1GH clock signal. Therefore, the control signal and the clock signal can be sent to the speed-up bus 24 by the pad circuits TCTL and TCLK respectively. Meanwhile, the 8-bit-2GHz data signal is also sent to the high-speed bus by the eight pad circuits tCAD0_TCAD7. twenty four. On the other hand, when an 8-bit-2 GHz sensible data signal is sent to the electronic device 10 on the high-speed bus bar 24, the data signal is also matched with the i-bit_1 GHz clock signal by 1 bit _20. The control signals along the edge are sent together. These 1-bit-1 GHz clock signals, 1-bit-2 GHz control signals, and 8-bit-2 GHz data signals are transmitted to the electronic device 10 via the high speed bus 24. The interface circuits rclK, RCTL and RCAD0_RCAD7 on the idle bus interface circuit 12 respectively receive the above-mentioned · bit · iGHz clock signal, 1-bit 2 GHz control signal and 8-bit-2 GHz data _ signal. The parallel-to-serial circuit 22 in the receiving circuit 18 can convert the 1-bit το -1 GHz clock signal and the i-bit 2 GHz control signal into the 8-bit-25 〇 MHz clock signal and the control signal. The original 8-bit-2GHz signal will also be converted to a 32-bit-250MHz signal. These signals are passed back to the core circuit 14, which is decoded and interpreted by the core circuit 14, so that the electronic device 1 can receive the resources transmitted by the other electronic devices via the high-speed stream. In order to ensure the normal operation of the electronic device 10, when manufacturing the electronic 200819771 device ίο, it is necessary to perform an input-output function test on the electronic device 1 - to test whether the electronic device 10 can correctly transmit and receive the high-speed bus gauge ...the signal of the grid. However, due to limitations in the circuit architecture, when the input/output function test is to be performed on the electronic device 10, the external high-frequency tester must be connected to the output/input circuit of the high-speed bus interface circuit 12, tclk, TCTL, TCAD0. -TCAD7, RCLK, RCTL·, RCAD0-RCAD7^^^ send and receive south frequency signals, and use this to understand whether the input and output functions of the electronic device 1〇 can work normally. However, as described above, the bus output interface formed by the above-mentioned pad circuits performs high-speed signal transmission and reception at a high frequency of 1 GHz and 2 GHz. Therefore, the conventional output function test technology can only be used at high frequencies. The input and output function test can be performed in a high speed environment. However, the ideal high frequency test environment is not easy to establish, and the high frequency tester used is very expensive, and the cost of the conventional electronic device 10 is also increased. '>1' The present invention proposes a wafer input/output functional testing mechanism and related method for testing an electronic device having a high speed bus interface. Figure 2 is a schematic diagram of the circuit of each of the electronic devices provided in the present invention. The electronic device 30 can be an electronic system, for example, a wafer level in a computer system. The electronic device 30 _ - the south speed bus interface circuit 32 and a core circuit %. Wherein: 11 200819771 The quick bus interface circuit 32 is used to enable the electronic device 3 to exchange data and signals with other electronic devices (not shown) via the high-speed stream drain 46. High Speed • Bus 46 can be an overspeed transmission bus that allows the electronics of the chipset 30 to exchange data via the high speed bus 46 and a central processing unit (not shown). The core circuit 34 is used to control the associated encoding/decoding and control procedures for bus access. The high-speed bus interface circuit 32 is provided with a transmission circuit 36, a receiving circuit 38, and a pad module formed by the wheel-in and out pad circuits TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, and RCAD0-RCAD7. The data is sent or received on the high speed bus 46, respectively. The transmission circuit 36 and the receiving circuit 38 are respectively used to implement signal transmission and reception functions. In the electronic device 30 illustrated in FIG. 2, assuming that the high speed sink_bank interface circuit 32 is an overspeed transmission bus interface circuit, the core circuit 34 provides a corresponding according to the specification of the overspeed transmission busbar. The 64-bit-250MHz integrated signal (which is a CAD (Command_Address_Data) signal) is combined with an 8-bit _25〇MHz control signal and an 8-bit-250MHz clock signal to represent the data to be transmitted. The parallel-to-serial circuit 40 in the transmission circuit % can convert the 64-bit-250 MHz integrated signal into an 8-bit-2 GHz integrated signal, and also control the 8-bit _25 〇]^1^. The clock signal is converted into a 1-bit-2GHz control signal and a 1 12 200819771 bit-1GHz clock signal. On the other hand, the serial-to-parallel circuit 42 in the receiving circuit 38 can receive the 8-bit -20!^ integrated signal, 1-bit-2〇1^ control signal and 1-bit-1 GHz when receiving 埠48. The signal signals are converted into a 64-bit-250 MHz integrated signal, an 8-bit_250 MHz control signal, and an 8-bit-250 MHz clock signal, and the converted signals are transmitted back to the core circuit 34. The core circuit 34 interprets the information represented by these signals. As for the pad circuits TCLK, TCTL, TCAD0-TCAD7, RCLK, RCTL, and RCAD0-RCAD7 are actually connected to the high-speed bus 46 to transmit and receive signals in the form of electronic signals developed by the high-speed bus bar specifications. For example, under the overspeed transmission busbar specification, the busbar carries information in the form of differential φ; under this busbar specification, each output pad TCLK, TCTL, TCAD0-TCAD7 circuit can be separately There are two connection terminals (two pins) on the bus bar 46, and a 1-bit signal is transmitted by a pair of mutually inverted differential signals. TCLK, TCTL and TCAD0-TCAD7 can respectively send a 1-bit time pulse signal 5 tiger, 1 bit control signal and 8-bit integrated signal to the bus bar 46. In contrast, each of the input pad circuits RCLK, RCTL, and RCAD0-RCAD7 can receive signals in a differential form from the bus bar 46, and each pad circuit can take a bit signal from a pair of 13 200819771 differential signals. The signals received by the input pad circuits ’ RCLK, RCTL and RCAD0-RCAD7 become the 'bit clock signal, 1-bit control signal and 8-bit integrated signal respectively. Under the overspeed transmission S-flow specification, the control signal can refer to the nature of each message in the down-converted signal. The clock signal is used to indicate the control signal and the date of the integrated ail number, as described in the control signal. When asserted, it means that the control signal and related data address are carried in the integrated signal (for example, it is required to access the data from a poor material address); when the control signal is not triggered (de-assert) At the time, the information carried on behalf of the comprehensive signal is information. In order to implement the input-output functional test technique of the present invention, the idle bus interface circuit 32 provided by the present invention forms an inner loop between the transmission circuit 36/receiving circuit 38 such that the signal emitted by the transmission circuit 36 The (four) way can be received by the receiving circuit 38. In addition, the receiving circuit 38 is provided with a multiplex module 50. Through the control of the multiplex module 5, the high speed bus bar interface circuit 32 can select to receive information from the high speed bus, or receive the transmission circuit from the inner loop. 36 information sent. In the embodiment of FIG. 2, since the information DATA1 sent by the transmission circuit 36 includes the time pulse signal CLK, the control signal CMD, and the integrated signal CAD', the inner loop loops the three signals to the receiving circuit %. The multiplex module 50 in the receiving % channel 38 includes multiplex circuits muxi, mux2, and mux3 for respectively switching the information data transmitted by the transmission circuit or 14 200819771 transmitted by the high speed bus bar 46 through the pad circuit. Information 〇^,. The - the integrated circuit circuit can be switched so that the receiving port 48 selectively receives the integrated signal CAD transmitted by the circuit 36, or the integrated signal CAD received by the input interface circuit RCAD0-RCAD7. The rural power system nrnx2 can be switched so that the receiving port 48 selectively receives the transmission circuit % transmission control signal CMD, or the channel signal CMD received by the input pad circuit RCTL. The multiplex circuit Cong 3 can switch the receiving port 48 to receive the clock signal CLK transmitted by the transmission circuit 36 or the clock signal CLK received by the input pad circuit RCLK. By using the above-mentioned inner loop', the present invention can directly perform the electronic device 3〇_input function test mode in the high speed bus bar interface circuit 32, without using an external high frequency tester. In performing the input-output function test of the present invention, the evening module 5〇 (including the multiplexer muxl_mux3) in the receiving circuit 38 can switch the information D ATA (including the clock signal CLK and the control signal) sent by the transmission circuit 36. After the CMD and the training (CAD) are transmitted to the receiving circuit of the receiving circuit via the inner loop, and then comparing the information transmitted by the transmitting circuit % with the information received by the receiving circuit 38, the output of the electronic device 3 can be tested. Features. When the speed-up bus interface circuit 32 is to be generally operated, the multiplex module 5〇15 200819771 can terminate the connection of the inner loop, so that the receiving port 48 of the transmission circuit 38 can normally borrow the input circuit rCLK, The RCTL and RCAD0-RCAD7 receive the information on the high speed, bus bar 46. Through the input and output function test through the inner loop, the present invention can directly test the high frequency input and output functions of the transmission circuit 36 and the receiving circuit 38 directly from the low frequency layer of the core circuit 34, without using a costly external high frequency tester. The high-frequency bus output function is tested from the high-frequency bus output. In the example of FIG. 2, under the overspeed transmission busbar specification, although the clock signal transmitted/received by the transmission circuit 36/receiving circuit 38 has a high frequency of 1 GHz, and the control signal/integrated signal frequency is as high as 2 GHz, The high speed bus interface circuit 32 only needs to be triggered by a low frequency clock of 100 MHz (1 MHz = 106 Hz). After receiving the low frequency clock trigger of 100 MHz, the high speed bus interface circuit 32 can exchange information with the transmission circuit 36 and the receiving circuit 38 at a frequency of 250 MHz (that is, the clock signal of the 250 MHz signal, the control signal and the integrated signal). The transmission circuit 36 and the receiving circuit 38 can also transmit and receive data on the sleek line 46 with the 1 GHz clock signal and the 2 GHz control signal and the integrated signal. Therefore, the present invention can confirm whether the transmission circuit 36 and the reception circuit 38 can correctly perform the high-frequency input/output function of 2 GHz through the operation of the core circuit 34 only by the test environment of 1. - In the conventional input-output functional test technology, the conventional technology must be connected to the high-frequency tester 16 200819771 to send and receive 2 GHz data at the high-speed, bus-out interface circuit external bus output terminal, so the tester must be able to Handling 2GHz e-signal, and the cost is very high. In contrast, since the internal circuit is provided in the buffer bus interface circuit 32 of the present invention, the electronic engine 30 of the present invention can trigger the input/output function measurement at the core circuit 34 at 100 MHz. That is, under the control of the core circuit 34, the core circuit 34 can cause the transmitting circuit 36 to issue specific information 'and return the information from the receiving circuit % to the core circuit ^ to verify whether the receiving circuit 38 can correctly receive the specific resource. Lu Xun. In other words, by using the electronic device 3 provided by the present invention, it is only necessary to verify that the transmission circuit 3=the 2 GHz high-frequency/high-speed wheel access function of the transmission circuit 38 is normal with the low-frequency layer of the core circuit 34. . The low cost of the '100 MHz low frequency test environment makes the electronic device provided by the present invention capable of performing high frequency input and output function tests under low cost conditions. In addition, the present invention can also control the input-output functional test of the high-frequency bus interface interface circuit by using a lower-frequency bus interface. Since the chipset is to bridge the high-speed central processing unit and other low-speed peripheral devices, not only the high-frequency overspeed transmission busbars but also the low-frequency busbars, such as the 33MHz PCI (Peripheral Communication Interconnect), are set on the chipset. Bus bar. In the second embodiment of the electronic device 30 provided by the present invention, the data transmission for testing can be transmitted through the low-speed Ρα bus stream 17 200819771 when the input/output function test is performed on the over-speed transmission sink and the interface circuit. To the chipset, the chipset can test the input and output functions of the interface circuit of the overspeed transmission control bus according to the test materials. FIG. 3 is a schematic diagram of an embodiment of an electronic device according to the present invention, wherein the electronic device 30 can be a silicon wafer set and additionally provided with a low speed bus bar 52. Note that the low speed bus 52 can be a 33 MHz PCI bus. The electronic device 3 provided by the present invention can perform a high-speed input-output function test on the high-speed bus interface interface circuit 32 included in the electronic device 30 via the low-speed bus bar 52. When performing the input-output function test on the high-speed bus interface circuit 32, the electronic device 30 provided by the present invention can input the test data (which can be referred to as a test vector) to the chipset via the low-speed bus bar 52 (ie, the electronic device 30). And the test data may be a read request command, and the electronic device 30 is required to read the data of a certain address from the high speed bus bar 46. The test data input to the electronic device 30 is transmitted to the core circuit 34 via the bridge circuit 54, and the core circuit 34 sends a corresponding 250 MHz pulse signal, control signal and integrated signal to the high speed bus interface circuit 32. Incidentally, the transmission circuit 36 in the high speed bus interface circuit 32 also issues a clock/control/synthesis signal of 1 GHz/2 GHz. The clock/control/synthesis signal from the transmission circuit 36 is transmitted back to the receiving port 48 of the receiving circuit 38 via the inner loop to form a 25_z clock/.control/synthesis signal and to the core circuit 34. If the transmission circuit % and the input/output function of the receiving circuit 38 are all functioning properly, the core circuit 34 should be able to read an upstream read request command from 200819771. The result of the interpretation of the core 'heart circuit 34' can be output via the bridge circuit 54 and the low speed bus bar 52 (in the case where the frequency of use 乂 is 33 MHz). Comparing whether the returned test data conforms to the test material input as before, can confirm the output of the electronic device 30. ... · Whether it can be normal, that is, whether the high speed bus interface circuit 32 can be correct Send and receive high frequency signals. - : - 瘫 In the second embodiment of the electronic device 3 shown in FIG. 3, the input and output function test mechanism is applied, and the present invention can directly control the high speed bus (ie, the overspeed transfer wheel) by using the 33 MHz low frequency test environment. The input and output function test of the busbar is equivalent to, that is, the high-frequency high-speed bus output function test is completed in the low-frequency test environment. Therefore, the present invention can reduce the test environment requirement of the high-speed bus output function test, greatly reduce the cost of the high-speed bus output function test, and make the high-efficiency of the high-carrying bus bar widely available to the public. It should be emphasized that the second embodiment of the electronic device 3 provided by the present invention performs the high-speed convergence 'output function test of the electronic device 30 under the low-frequency test environment, but the high-speed bus of the electronic device 3〇 The interface circuit 32 will actually operate at the high frequency defined by the general purpose, so that the present invention can truly test the high frequency wheel access function of the high speed bus interface interface circuit 32. As shown in FIG. 2, 'the first embodiment and the second embodiment of the electronic device 30 illustrated in FIG. 3', the present invention can test the 2GHz 19 200819771 overspeed transmission bus in an environment of 100 MHz or 33 MHz. The quick bus interface circuit 32. Although the test environment is a low-frequency test environment such as 100 ΜΉΖ or 33 MHz, the high-speed bus. The transmission circuit 36/receiving circuit 38 in the interface circuit 32 actually transmits and receives data at a high frequency of 2 GHz, so the present invention can truly The high frequency wheel access function and performance of the electronic device 30 are tested in accordance with the standard of high frequency operation. On the other hand, after confirming the input and output functions of the transmission circuit 36 and the reception circuit 38 by the above-described input/output function test, the input and output pads circuit TCLK, TCTL, TCAD0-TCAD7, RCLK, The functions of RCTL and RCAD0-RCAD7. Basically, since the function of these pad circuits is only to follow the signal operation of the transmission circuit 36 and the receiving circuit 38, it can be tested by down-conversion. For example, when testing the output pad circuits TCLK, TCTL and TCADO-TCAD, the transmission circuit 36 can send 2 〇〇mhz clock/control/synthesis signals to these pad circuits, and in the pad circuit TCLK, TCTL And the end of the TCAD0-TCAD7 connected to the bus bar _ 46 receives the signals from the pad circuits to test whether the pad circuits can correctly transmit the signals transmitted to the pad circuits according to the transmission circuit 36 to the bus bar 46. Corresponding differential signal. Similarly, when testing the input pad circuits RCLK, RCTL and RCAD0-RCAD7, the lower frequency signals can also be used to test the receiving power of each input pad circuit. In this way, the complete, input-output functional test of the high-speed bus interface circuit 32 can be completed. 20 200819771 The present invention can perform the high-speed input/output function measurement of the electronic device 3 in the low-frequency test environment by the internal loop of the high-speed bus interface interface 32. Therefore, the present invention can directly or not at the wafer stage. The cut and unsealed electronic device (wafer) performs an input/output function test. As is well known to those skilled in the art of the present invention, it is known that the wafers can be functionally tested by the light-sensing technique on the wafers. However, such detection techniques also have operational frequencies and are limited. To use this technology to directly send and receive 2GHz high-frequency ^ 'apparently technical difficulties' also requires expensive test environment and 'phase car, the invention can directly use the current low-cost low-frequency detection technology = Complete high-speed output human function test. In the wafer stage, the output is processed to screen out the faulty chips at an early stage. It is not necessary to perform subsequent package testing on this: the defective chip can further save the wafer production and make the Honda Ran. The chip can still be used for the input/output function test by using the internal loop technology of the high-speed bus interface circuit 32 included in the electronic device 3 provided in this month. It is very important for the high-frequency signals transmitted on the bus to be arrested. The order/phase relationship and order between the signals are very important. For example, in the embodiment of the electrical equipment department shown in Fig. 2, the control signal and the clock signal should have a dimensional relationship with each other; similarly, the integrated signal and the clock signal should also be Maintain - set her _. Please refer to Figure 4 for the timing signal, control signal and integrated signal on the pad circuit TCLK, TCTL and 1^8-10-10) 八7 21 200819771. Figure 4 is for this v 〇 • in overspeed Under the specification of the transmission bus, the 1GHz clock signal (labeled TCLK in Figure 4) has a period of 1000ps (lps=i〇12 seconds), and the rising edge of the clock signal every half cycle (500ps) The falling edge can trigger a data in the control signal (the TCTL is TCTL) and each integrated signal (labeled as TCAD[7:0]), so the control signal and the integrated signal are 2GHz# signals. As is well known in the art to which the present invention pertains, in order to be able to trigger stable signal and data sampling, the rising and falling edges of the clock signal should avoid the signal transition of the control signal and the integrated signal. As shown in Figure 4, under ideal conditions, there should be a 1/4 cycle (ie 250 ps) time difference (ie, phase) between the rising/falling edge of the clock signal and the signal transition of the control/synthesis signal. difference). Of course, in actual implementation, a certain degree of timing skew can be tolerated between the clock signal and the control signal/integrated signal. For example, if the rising/falling edge of the clock signal has a time difference of 50ps _ from the rising/falling edge under ideal conditions, the timing distortion should be within the tolerable range. However, if there is an abnormal excessive timing distortion between the rising/falling edge of the clock signal and the control signal/integrated signal (for example, the rising/falling edge of the clock signal and the rising/falling edge of the ideal condition have more than lOOps. The time difference), the rising/falling edge of the clock signal will be too close to the signal transition of the control signal/integrated signal; thus, it is difficult to correctly transmit information on the bus. In the present invention, when the transmission circuit 36 is in operation, the transmission circuit 36 can be based on the above-mentioned timing/phase in the clock signal (4) (4) according to the above description. Similarly, the receiving circuit 38 can also be based on Appropriate: Inter-time/phase operation. In conjunction with the transmission of power to the high-speed bus interface interface I% / connection (four) way 3S to lose "Wei Lai, then the environment can not be in the transmission circuit / receiving circuit signal Introduce an extra difference between the days (that is, the timing distortion). If the transmission circuit/receiver circuit is tested for input and output functions, the measurement itself cannot be correctly reflected in the introduction of additional timing distortions in the relevant signals (ie: clock signal and control signal/combined signal). The operation of the transmission circuit/receiving circuit loses its function in the functional test. ^ ^ ^ ^ , since the present invention constructs a test environment by means of an inner loop in the high speed bus interface circuit 32, the test environment of the present invention can more easily take into account the respective signals (clock signal, control signal/comprehensive signal). Timing balance to avoid introducing unnecessary time differences between signals. In contrast, if the external tester is used to form an external loop outside the high-speed busbar interface circuit 32 (that is, where each of the input/output pad circuits and the busbar is connected), the input function test is very It is easy to introduce an extra time difference between the signals. As is well known in the art to which the present invention pertains, when a high frequency signal is to be transmitted, the high frequency signal is affected by the transmission line on the signal transmission path; if different signals are transmitted on different transmission paths having different length/characteristics , will introduce an extra time difference between the same signal. Therefore, it is necessary to arrange the external circuit. • A good high-frequency external circuit test environment is very difficult. Compared with 23 200819771, this issue is equipped with an inner loop in the high-speed bus interface circuit 32 to assist the input-output function test, so that the transmission path can be sufficiently reduced for each signal. The south frequency input and output signal of the speed slewing row is provided in a relatively simple manner, and the first mega product is shown in Fig. 5, which is a case where the electronic device 30 shown in Fig. 2 performs a general operation. When the input/output function test ends and the electronic device 3 is to perform a general operation, the multiplex module 50 cuts off the inner loop (so indicated by a broken line in FIG. 5), so that the receiving circuit 38 can normally be The input interface circuits RCLK, RCTL and RCAD0_RCAD7 receive the clock signal/control signal/synthesis signal transmitted by the high speed bus, and stop receiving the clock signal/control signal/synthesis signal from the inner circuit receiving transmission circuit 36. In summary, the present invention provides an internal loop in a high-speed bus interface circuit of an electronic device (eg, a wafer) by means of an external high-frequency bus-in/out function test mechanism on an electronic device, with a high-speed bus interface. ^ _ The operation of the low-frequency core circuit in the road, using the inner loop to perform the function test of the high-frequency transmission circuit/receiver ^. Therefore, the present invention can use the low-frequency measurement of the high frequency input and output functional test of the electronic device to reduce the measurement. Cost. The input and output function testing technology of the invention can be applied not only to the day-to-day film formed by the seal, but also to perform the early adjustment and input-in function test when the wafer is not cut or unpackaged, thereby further saving the time of subsequent processing and becoming ' this. In addition, although the second picture to the fifth picture are 8-bit wide-degree sound and 8-bit 疋 comprehensive data) and the high-speed convergence of the overspeed transmission busbar specification 24 200819771 on jL -t* vl -*v> ___
但本發明所使甩之 立元見度的超速匯流排）， 高速網路的介面_人功_ τ廣乏運用於其他位元寬度的 16位元官疮AAm_ . 試，並不限於上述之超速傳輪匯流拂。 “ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 _ 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖示意的一具有高速匯流排介面電路的電子裝置。 第2圖示意的是本發明一具有内迴路之高速匯流排介面電 路的電子裝置。 第3圖示意的是本發明一經由低速匯流排測試電子裝置的情形。 第4圖是高速匯流排介面電路各相關訊號波形時序的示意圖。 •第5圖為本發明電子裝置在_般運作下的情形。 【主要元件符號說明】 、3〇電子裝置 12、32高速匯流排介面電路 14、34核心電路 16、36傳輸電路 18 ' 38接收電路 — 20、40串列至並列電路 • 22、42並列至串列電路 25 200819771 24 南速匯流排 46 低速匯流排 48 接收埠 50 多工模組 52 低速匯流排 54 橋接電路 muxl、mux2、mux3 多工電路 TCLK > TCTL - TCAD0-TCAD7 ^ RGLK λ RCTL - RCAD0-RCAD7 m 胃接墊電路 26However, the ultra-fast busbar of the invention of the invention, the interface of the high-speed network _ human power _ τ is widely used for other bit width 16-bit official sore AAm_. The test is not limited to the above The speeding pass is converging. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the patent application scope of the present invention are within the scope of the present invention. An electronic device having a high speed bus interface circuit. Fig. 2 is a view showing an electronic device of the present invention having a high speed bus interface circuit of an inner loop. Fig. 3 is a view showing a low speed bus of the present invention. The case of testing the electronic device. Fig. 4 is a schematic diagram of the timing of each relevant signal waveform of the high speed bus interface circuit. Fig. 5 is a view of the electronic device of the present invention under the general operation. [Main component symbol description], 3〇 electronic Device 12, 32 high speed bus interface circuit 14, 34 core circuit 16, 36 transmission circuit 18 '38 receiving circuit - 20, 40 serial to parallel circuit • 22, 42 juxtaposed to serial circuit 25 200819771 24 South speed bus 46 Low speed bus 48 receiving 埠 50 multiplex module 52 low speed bus 54 bridge circuit muxl, mux2, mux3 multiplex circuit TCLK > TCTL - TCAD0-TCAD7 ^ RGLK λ RCTL - RCAD0-RCAD7 m Gastric pad circuit 26