1221974 玖、發明說明： 【發明所屬之技術領域】 本發明係有關於快速周邊元件互連介面(Ρα Express)，特別有關於 一種快速周邊元件互連介面之通道整序方法及其相關裝置。 、 【先前技術】 個人電腦之周邊裝置所使用之標準匯流排，由早期之ISA介面、 EISA介面、PCI33介面、不斷演進到pCI66介面以及pcn33介面，尤 其是PCI系狀鮮介面更是近幾年絲最為盛行之周邊裝置之標準 連接介面。 快速周邊元件互連(Peripheral Component Interconnect Express，簡 稱PCI Express，或簡稱快速PCI)介面，極有希望成為下一世代之標^ 介面，快速PCI採用點對點傳輸，而對每個端點而言，每個快速 之通道(lane)分別具有傳送訊號對和接收訊號對，以目前已知之規格來 說，快速PCI差動訊號傳輸速度達2_5Gbps，就傳收資料而言僅需四根 實體訊號，其他共用之控制訊號則不予贅述，相較於ρα，快速ρα 可以較少之硬體腳位實現更高之傳輸速率。快速ρα亦規範了單通道、 四通道、八通道、十六通道、以及三十二通道等不同硬體規格，以符 合不同周邊裝置制之頻寬需求，舉例而言，_卡需要極大之傳輸 頻寬’適合以二十二通道之快速PCI介面實現；快速ρα介面在主機 板上可以貫施於北橋晶片或者南橋晶片。 快速PCI規袼規範了接收器(receiver)與傳送器⑽麵丨㈣之終端 狀態(tenmnatKm)，包括阻抗(impedance)與共模電壓㈣麵⑽m〇de voltage)等等。快速PCI規格規範了兩種通道順序··正通道順序(n〇rmal lane order)以及反通道順序(reverse lane沉㈣；圖一顯示具有四通道之 快速pci之反通道順序連接示意圖，左侧的四個快速pci通道以反順 序連接右側的四個快速PCI通道，兩端可以藉由四通道之快速ρα插 槽1〇〇進行耦接，亦即，四通道之快速PCI之反通道順序為[通道〇、 通道1、通道2、通道3]對應耦接右側的四個快速ρα通道[通道3、通 5 1221974 通道1通C ]’另種硬體福接方式則為左側的四個快速pci 通道以[通道0、通道1、通道2、通道3】依序對應墟右侧的四個快速 PCI通道[通道0、通道1、通道2、通道3]，兩種快速ρα通道之麵接 方式皆可為快速PCI規袼所接受；但是，在晶片組設計廠商、主機板 設計廒商以及周邊裝置設計廠商等不同麟_設計之τ，仍然有可 能發生設計上的錯誤，而導致周邊裝置無法運作。 【發明内容】 本發明揭示一種快速周邊元件互連介面之通道整序方法，包含下 列步驟·發出複數個有關快速pCI通道序列之封包告知周邊裝置，周 邊裝置回《數财Μ邊敍讀速Ρα通道序狀封包，根據該 些回覆封包判斷周邊裝置之快速PCI通道序列是否正確，以及若周邊 裝置之通道序列不正確則適當地調整快速pCI通道之順序。 本發明揭示亦揭示一種快速周邊元件互連介面之通道整序方法， 包含下列步驟·發出複數個有關快速PCI通道序列之封包告知周邊裝 置，周邊裝置根據該些有關快速PCI通道序列之封包適當地調整快速 PCI通道之一順序’以及重置並重新初始化快速pCI通道，使得經過調 整後之快速PCI通道之對應關係符合正通道順序或反通道順序，而其 中重置步驟可藉由發出重置封包或者改變共模電壓之位準以重置個人 電月1¾之橋接晶片組。 本發明揭示進一步揭示一種快速PCI通道之整序裝置，包含：控 制匯流排，用以傳輸複數個控制訊號；以及整序電路，用以輸入第一 複數個快速PCI通道及輸出第二複數個快速PCI通道，其中整序電路 將第一該些快速PCI通道路由至第二該些快速PCI通道，以回應於控 制訊號’使得第一該些快速PCI通道與第二該些快速PCI通道之間形 成一對一之對應連接關係。 【實施方式】 圖二顯示根據本發明之一具體實施例之通道整序電路方塊圖，適 合實施於晶片200中，例如於個人電腦之橋接晶片（例如北橋晶片、南 6 1221974 橋曰曰片）或者裝置端之晶片内，於此具體實施例中，橋接晶片200内部 提供快速PCI通道〇、通道1、通道2、通道3，經過一整序裝置21〇 之後’才實際提供對外之硬體連接，例如是金屬腳位或者金屬球狀接 點；於此具體實施例中，主機板設計廠商將電腦橋接晶片2〇〇對外實 施為連接快速PCI通道3、通道1、通道2、通道〇，電源開啟後，電 腦橋接晶片200與周邊裝置會依照快速pci之規格發出一連串之訓練 序列(training sequence)，首先，電腦橋接晶片2〇〇會預設周邊裝置之配 置順序也是通道0、通道1、通道2、通道3之依序對應耦接，電腦橋 接晶片200端會先發出有關自己通道序列(〇rdering)之封包告知周邊裝 置，周邊裝置會回覆電腦橋接晶片200有關周邊裝置之序列之封包， 電腦橋接晶片200於收到有關周邊裝置之通道序列之封包後，若電腦 橋接晶片200發現周邊裝置之通道序列不符規袼時，電腦橋接晶片2〇〇 可透過控制匯流排220控制整序裝置210，適當地調整電腦橋接晶片 2〇〇内快速PCI通道之順序，於此具體實施例中，透過整序裝置21〇調 整電腦橋接晶片200内快速PCI通道之順序為快速pci通道3、通道1、 通道2、通道〇，舉例來說，整序裝置21〇包含四個選擇器(select〇r)212、 214、216、218，各選擇器用以將電腦橋接晶片200内之快速PCI通道 擇一對應搞接至外部快速PCI通道，在硬體設計階段，可以利用狀態 機器(state machine)設計，透過控制匯流排220發出適當訊號改變整序 裝置210中選擇器212、214、216、218之路由路徑，使得電腦橋接晶 片200内之快速pci[通道〇、通道1、通道2、通道习正確地路由至外 部PCI[通道〇、通道丨、通道2、通道3]，或者，反相整序為將電腦橋 接晶片200内之快速pci[通道〇、通道1、通道2、通道3]路由至外部 PCI[通道3、通道2、通道1、通道0]，其中，每個通道包含四條訊號 線；然後，電腦橋接晶片200可以重置雙方之初始化程序，舉例而言， 電腦橋接晶片200可發出重置封包或者藉由改變共模電壓，致使雙方 重新開始初始化程序，也就是說，重新發出一連串之訓練序列，確保 雙方之外部PCI通道順序之正確性，並允許系統廠商在電路佈局上之 7 最佳彈性，其巾重㈣包可以齡錄(assert)於訓練相巾之熱重置控 制位元超過一次以上而實現。應注意到，整序裝置210之設&亦適二 實施於裝置端之⑼中，當线端告知裝置端之晶片其通道順序後: 裝置端之晶片即對應調整晶片内部快速PCI通道之順序，然後，裝置 端之晶片可重置雙方之初始化程序，以便利系統廠商之電路佈^設 汁，並提高快速PCI通道之高速訊號傳輸品質。 圖三顯示根據本發明之一具體實施例之通道整序方法流程圖，從 步驟300開始，進入參驟31〇，由電腦橋接晶片端發出冑關自己通道序 列之封包告知周雜置；於步驟⑽，周邊裝置會哺電麵接晶片有 關周邊裝置通道序狀封包給賴橋接晶片，舉絲說，各個通道回 覆之封包包含複數個位元組，其中一位元組會顯示其通道順序號為 何；於步驟330，判斷通道序列是否正確；若通道序列不正確，則於步 驟332適當地調整電腦橋接晶片内快速ρα通道之順序，使得經過通 道整序後之快速PCI通道之對應關係符合正通道順序或者反通道順 序，然後由步驟334重新初始化快速PCI之鏈結。 圖四顯示根據本發明之一具體實施例之具有快速PCI通道整序電 路之周邊裝置晶片之相關系統方塊圖，周邊裝置晶片4〇〇以介面卡之 I式插置於快速PCI插槽420上，福接至主機板上之晶片組440，晶片 組440之左側依序提供快速ρα通道〇、通道丨、通道2、通道3，以 搞接快速PCI插槽420;周邊裝置晶片400提供四個外部快速PCI通道 412、414、416、418，如果以習知技藝之實施方式，四個快速pci通 道412、414、410、418分別對應周邊裝置晶片400之快速Ρα通道之 通道0、通道1、通道2、通道3，則主機板廠商只要將周邊裝置晶片 400順時針旋轉45度，便可直接以最短距離及跡線(trace)轉折數，耗接 快速PCI插槽420，但若四個快速ρα通道412、414、416、418分別 對應周邊裝置晶片400之快速PCI通道之通道3、通道2、通道1、通 道〇 ;而當此周邊裝置晶片400受到主機板上眾多元件擺置之排擠，迫 使無法如圖四般，將周邊裝置晶片400與晶片組440擺置成一左一右 1221974 之相對關係，適必造成跡線轉折數增多以及路線增長之結果，導致阻 抗以及電感電容效應增加，而快速PCI所傳輪之速率至少高達 2.5Gbps，對於如此高頻訊號之傳輸極為不利，實施本發明正可克服此 重大缺點。 於此具體實施例中，周邊裝置晶片400具有整序裝置4〇2，類似圖 -之整序裝置210 ’周邊裝置晶片4〇〇 0之電路設計提供四個快速ρα 通道404、406、408、410，依序對應快速ρα通道之通道〇、通道i、 通道2、通道3，系統廠商可以依照自己需求將外部快速ρα通道4i2、 414 416、418對應佈局至快速pci插槽420端，首先，晶片組44〇向 周邊裝置晶片400發出有關自己通道序列之封包，當周邊裝置晶片4〇〇 根據晶片組之快速PCI通道序列之封包，魏其快速ρα通道序列不 正確時，則發訊整序裝置4〇2，適當調整周邊裝置晶片_内部四個快 速PCI通道404、406、408、410之對應關係，以完成快速ρα通道之 正確耦接關係，然後重新初始化快速PQ之鏈結；當然，若晶片組之 快速PCI通道序列正確時，則周邊裝置晶片_無須做整序調整與重 新初始化快速PCI之鏈結之動作。 上述具體實施例係以四個快速PCI通道做為說明。相較於先前技 藝’以目前北橋晶為例，其北邊連接中央處理器匯流排，右邊連接 動態隨機存取記顏，南邊連接南橋晶片，左邊連接AGP(advanced graphic port)匯流排；根據快速ρα通道之規格將 排’例如為三十二通道之快速PCI，而北橋晶片長久以來就是—種接塾 數限制(pad 之晶片，北橋晶片本身之出腳(或者出球，Μ㈣ 受到嚴重_ ’而主機板軸在其域板上也需擺置衫元件，因此 不論是主機板上的相關晶片或者快速PCI插槽之跡線佈局都將受到嚴 重限制與彼此辟，而且，快速PCI正是為高軌賴輸所制定，過 長之跡線與騎，或者強迫某些鱗穿過其他金朗以酬其他跡 線’都將影響到減傳輸品質以及跡線所佔據之主機板面積。 縱上所述，本發明揭示一種快速周邊元件互連介面(簡稱快速吻 9 之通道整序方法，包含下列麵：發出複數個有_速ρα通道序列 之封包告知周邊裝置，周邊裝置回覆複數個有關周邊裝置之快速阳 通道序列之封包，根據該些回覆封包判斷周邊裝置之快速PCI通道序1221974 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a fast peripheral component interconnect interface (Pα Express), and more particularly, to a channel sorting method for a fast peripheral component interconnect interface and related devices. [Previous technology] The standard bus used in peripheral devices of personal computers has evolved from the early ISA interface, EISA interface, PCI33 interface, pCI66 interface and pcn33 interface, especially the PCI-based fresh interface in recent years. Standard connection interface for most popular peripheral devices. The Peripheral Component Interconnect Express (PCI Express, or PCI Express for short) interface is very promising to become the standard of the next generation ^ Interface, fast PCI uses point-to-point transmission, and for each endpoint, each Each fast lane (lane) has a transmission signal pair and a reception signal pair. According to the currently known specifications, the fast PCI differential signal transmission speed reaches 2_5Gbps, and only four physical signals are required for data transmission. Others share The control signal will not be described in detail. Compared with ρα, fast ρα can achieve a higher transmission rate with fewer hardware pins. Fast ρα also regulates different hardware specifications such as single-channel, four-channel, eight-channel, sixteen-channel, and thirty-two channels to meet the bandwidth requirements of different peripheral device systems. For example, _cards require great transmission The bandwidth is suitable to be implemented with a 22-channel fast PCI interface; the fast ρα interface can be applied to the north bridge chip or the south bridge chip on the motherboard. The fast PCI specification specifies the terminal state (tenmnatKm) of the receiver and transmitter, including impedance and common mode voltage (mode voltage), and so on. The fast PCI specification specifies two channel sequences: positive lane order (n0rmal lane order) and reverse lane order (reverse lane); Figure 1 shows a schematic diagram of the reverse lane sequence connection of a fast PCI with four lanes. The four fast PCI lanes are connected to the four fast PCI lanes on the right in reverse order, and the two ends can be coupled through the four lanes of fast ρα slot 100, that is, the reverse lane order of the four lanes of fast PCI is [ Channel 0, Channel 1, Channel 2 and Channel 3] are coupled to the four fast ρα channels on the right side [Channel 3, Pass 5 1221974 Channel 1 and Pass C] 'Another hardware connection method is the four fast pci on the left Channels [Channel 0, Channel 1, Channel 2, Channel 3] correspond to the four fast PCI channels on the right side of the market in sequence [Channel 0, Channel 1, Channel 2, Channel 3]. Both can be accepted by the fast PCI specification; however, in different design groups such as chipset designers, motherboard design vendors, and peripheral device designers, design errors may still occur, causing peripheral devices to fail. [Invention Contents] The present invention discloses a channel ordering method for a fast peripheral component interconnect interface, which includes the following steps: Send a plurality of packets related to the fast pCI channel sequence to notify the peripheral device, and the peripheral device returns to the "Number of Money M Side Reading Speed Pα Channel Sequence" A packet is used to determine whether the fast PCI channel sequence of the peripheral device is correct according to the reply packets, and the sequence of the fast pCI channel is appropriately adjusted if the channel sequence of the peripheral device is incorrect. The invention also discloses a fast peripheral component interconnect interface. The channel ordering method includes the following steps: Send a plurality of packets related to the fast PCI channel sequence to inform the peripheral device, and the peripheral device appropriately adjusts an order of the fast PCI channel according to the packets related to the fast PCI channel sequence ', and reset and Re-initialize the fast pCI channel so that the corresponding relationship of the adjusted fast PCI channel conforms to the positive channel sequence or the reverse channel sequence, and the reset step can reset the individual by sending a reset packet or changing the level of the common mode voltage The bridge chipset of the electric month 1¾. The present invention is further disclosed A sequence device for a fast PCI channel includes: a control bus for transmitting a plurality of control signals; and a sequence circuit for inputting a first plurality of fast PCI channels and outputting a second plurality of fast PCI channels, wherein The reordering circuit routes the first and second PCI lanes to the second and second PCI lanes in response to the control signal, so that a one-to-one relationship is formed between the first and second PCI lanes. Corresponding connection relationship. [Embodiment] FIG. 2 shows a block diagram of a channel ordering circuit according to a specific embodiment of the present invention, which is suitable for implementation in chip 200, such as a bridge chip of a personal computer (such as a North Bridge chip, South 6 1221974 bridge). In the specific embodiment, the bridge chip 200 internally provides a fast PCI channel 0, channel 1, channel 2, channel 3, and it is actually provided to the outside after a sequence device 2110. The hardware connection is, for example, a metal pin or a metal ball contact. In this specific embodiment, the motherboard design manufacturer connects the computer bridge chip with 200 pairs. The implementation is to connect the fast PCI channel 3, channel 1, channel 2 and channel 0. After the power is turned on, the computer bridge chip 200 and peripheral devices will issue a series of training sequences according to the specifications of the fast PCI. First, the computer bridge chip 2 〇〇 Preset the peripheral device configuration order is also the corresponding corresponding coupling of channel 0, channel 1, channel 2, channel 3, the computer bridge chip 200 will first send a packet about its channel sequence (〇rdering) to inform the peripheral device The peripheral device will reply to the packet of the peripheral device sequence of the computer bridge chip 200. After receiving the packet of the channel sequence of the peripheral device, the computer bridge chip 200 finds that the channel sequence of the peripheral device is out of order. The computer bridge chip 2000 can control the sequencing device 210 through the control bus 220, and appropriately adjust the order of the fast PCI channels in the computer bridge chip 200. In this specific embodiment, the computer bridge is adjusted through the sequence device 21 The sequence of the fast PCI lanes in chip 200 is fast PCI lane 3, lane 1, lane 2, lane 0, for example The sequence device 21 includes four selectors 212, 214, 216, and 218, each of which is used to select one of the fast PCI channels in the computer bridge chip 200 and connect to the external fast PCI channel. In the hardware design stage, the state machine design can be used to control the bus 220 to send appropriate signals to change the routing paths of the selectors 212, 214, 216, and 218 in the sequencing device 210, so that the computer bridges the chip in the chip 200 quickly. pci [Channel 0, Channel 1, Channel 2, Channel Xi is routed to the external PCI [Channel 0, Channel 丨, Channel 2, Channel 3] correctly, or the reverse order is the fast pci [ Channel 0, Channel 1, Channel 2, Channel 3] are routed to the external PCI [Channel 3, Channel 2, Channel 1, Channel 0], where each channel contains four signal lines; then, the computer bridge chip 200 can reset both sides The initialization procedure, for example, the computer bridge chip 200 can issue a reset packet or change the common-mode voltage to cause the two parties to restart the initialization procedure, that is, to re-issue a series of training sequences. To ensure the correctness of the sequence of the external PCI channels on both sides, and to allow system manufacturers to achieve the 7 best flexibility in circuit layout, and its weight package can be asserted in the thermal reset control bit of the training phase towel more than once This is achieved. It should be noted that the design of the sequencing device 210 is also implemented in the device side. When the line terminal informs the chip on the device side of its channel order: the chip on the device side correspondingly adjusts the order of the fast PCI channels inside the chip. Then, the chip on the device side can reset the initialization procedure on both sides to facilitate the system layout of the system manufacturer and improve the high-speed signal transmission quality of the fast PCI channel. FIG. 3 shows a flow chart of a channel reordering method according to a specific embodiment of the present invention. Starting from step 300, entering step 31, a computer bridge chip sends out a packet about its own channel sequence to notify Zhou Zaoji; at step Alas, the peripheral device will feed the chip and connect the peripheral device channel sequence packets to the Lai bridge chip. For example, the reply packet of each channel contains multiple bytes, and one byte will show the channel sequence number. At step 330, determine whether the channel sequence is correct. If the channel sequence is incorrect, then at step 332, adjust the order of the fast ρα channels in the computer bridge chip appropriately so that the corresponding relationship of the fast PCI channels after the channel ordering conforms to the positive channel. Sequence or reverse channel sequence, and then re-initialize the fast PCI link in step 334. FIG. 4 is a block diagram of a related system chip with a fast PCI channel sequencing circuit according to a specific embodiment of the present invention. The peripheral device chip 400 is inserted into the fast PCI slot 420 with an I-type interface card. Fuse is connected to the chipset 440 on the motherboard. The left side of the chipset 440 provides fast ρα channel 0, channel 丨, channel 2, channel 3 in order to connect the fast PCI slot 420. The peripheral device chip 400 provides four The external fast PCI channels 412, 414, 416, and 418. If implemented in a conventional technique, the four fast PCI channels 412, 414, 410, and 418 correspond to channels 0, 1, and 1 of the fast Pα channel of the peripheral device chip 400, respectively. Channel 2 and channel 3, as long as the motherboard manufacturer rotates the peripheral device chip 400 clockwise by 45 degrees, it can directly use the shortest distance and the number of trace turns to consume the fast PCI slot 420. ρα channels 412, 414, 416, and 418 correspond to channel 3, channel 2, channel 1, and channel 0 of the fast PCI channel of the peripheral device chip 400, respectively; when this peripheral device chip 400 is crowded out by many components on the motherboard It is impossible to place the peripheral device chip 400 and the chipset 440 in a left-to-right relationship of 1221974 as shown in Figure 4. This will inevitably result in an increase in the number of trace turns and an increase in the route, leading to an increase in impedance and inductance and capacitance effects. And the speed of the fast PCI transfer wheel is at least 2.5Gbps, which is extremely disadvantageous for the transmission of such high frequency signals. The implementation of the present invention can overcome this major disadvantage. In this specific embodiment, the peripheral device chip 400 has a sequencing device 402, similar to the circuit design of the sequencing device 210 'in the figure-the peripheral device chip 4000's circuit design provides four fast ρα channels 404, 406, 408, 410, corresponding to channel 0, channel i, channel 2 and channel 3 of the fast ρα channel in sequence. System manufacturers can arrange external fast ρα channels 4i2, 414 416, 418 to the fast PCI slot 420 according to their own needs. First, The chipset 44 sends a packet about its own channel sequence to the peripheral device chip 400. When the peripheral device chip 400 according to the packet of the chipset's fast PCI channel sequence, Wei Qi's fast ρα channel sequence is incorrect, then the whole sequence is sent. Device 402, appropriately adjust the corresponding relationship of the four fast PCI channels 404, 406, 408, 410 inside the peripheral device chip to complete the correct coupling relationship of the fast ρα channel, and then re-initialize the fast PQ link; of course, If the fast PCI channel sequence of the chipset is correct, the peripheral device chip_ does not need to perform sequence adjustment and re-initialize the action of the fast PCI link. The above specific embodiment is described by using four fast PCI lanes. Compared with the previous technique, taking the current Northbridge as an example, the north side is connected to the CPU bus, the right side is connected to the dynamic random access memory, the south side is connected to the southbridge chip, and the left side is connected to the AGP (advanced graphic port) bus; according to the fast ρα The specifications of the channel will rank 'for example, 32 lanes of fast PCI, and the Northbridge chip has long been a kind of limit on the number of connections (pad chip, Northbridge chip itself (or out of the ball, Μ㈣ suffered serious _') and The motherboard axis also needs to place shirt components on its domain board. Therefore, regardless of the relevant chip on the motherboard or the trace layout of the fast PCI slot, it will be severely restricted and cut off from each other. Moreover, the fast PCI is very high. The track is determined by the loss, too long traces and rides, or forcing certain scales to pass through other Jinlang to pay for other traces will affect the transmission quality and the area of the motherboard occupied by the traces. As mentioned above, the present invention discloses a fast peripheral component interconnection interface (referred to as the method of channel ordering of the fast kiss 9), including the following: sending a plurality of packets with a _speedρα channel sequence to inform the surroundings Position, a plurality of related peripheral devices respond to the male quick packet channel sequences peripheral device, the PCI Express packet channel sequence is determined according to the plurality of peripheral device replies
列是否正確，以及若周邊裝置之通道序列不正確則適當地調整快迷PCI 通道之順序。 本發明揭示亦揭示一種快速周邊元件互連介面之通道整序方法， 包含下列步驟··發出複數個有關快速PCI通道序列之封包告知周邊裝 置，周邊裝置根據該些有速ρα通道相之封包適當地調整快速 PCI通道之一順序，以及重置並重新初始化快速PCI通道，使得經過調 整後之快速PCI通道之職隱符合正通道順序姐通道順序，而其 中重置步驟可藉由發出重置封包或者改變共模電壓之位準以重置個人 電腦之橋接晶片組。 本發明揭示進一步揭示一種快速pci通道之整序裝置，包含：控 制匯流排，用以傳輸複數個控制訊號；以及整序電路，用以輸入第一 複數個快速PCI通道及輪出第二複數個快速PCI通道，其中整序電路 將第一該些快速PCI通道路由至第二該些快速ρα通道，以回應於控 制訊號，使得第-該些快速PCI通道與第二該些快速PCI通道之間形 成一對一之對應連接關係。 以上所揭示之具體實施例之說明及圖式，係為便於闡明本發明之 技術内容及技術手段，並不欲拘限本發明之齡。舉凡_切針對本發 明之結構細部修飾、變更，或者是元件之等效替代、置換，當不脫離 本發明之發明精神及範_，其範隨由以下之中請專利範圍來界定之。 【圖式簡單說明】 圖一顯示具有四通道之快速PCI之反通道順序連接示意圖； 圖二顯示根據本發明之一具體實施例之通道整序電路方塊圖； 圖三顯示根據本發明之一具體實施例之通道整序方法流程圖；以 及 圖四顯不根據本發明之一具體實施例之具有快速PCI通道整序電 1221974 路之周邊裝置晶片之相關系統方塊圖。 【元件符號簡單說明】 100快速PCI插槽 200晶片 210整序裝置 212〜218選擇器 220控制匯流排 400周邊裝置晶片 402整序裝置 404〜418快速PCI通道 _ 420快速PCI插槽 440晶片組If the sequence is correct, and if the channel sequence of the peripheral device is incorrect, adjust the order of the PCI channels. The present disclosure also discloses a channel ordering method for a fast peripheral component interconnect interface, which includes the following steps: sending a plurality of packets related to the fast PCI channel sequence to notify the peripheral device, and the peripheral device is appropriate according to the packets with the speed ρα channel phase To adjust one of the sequences of fast PCI lanes, and reset and re-initialize the fast PCI lanes, so that the adjusted position of the fast PCI lanes conforms to the positive lane sequence and the lane sequence, and the reset step can be performed by sending a reset packet Or change the level of the common mode voltage to reset the bridge chipset of the personal computer. The present invention further discloses a sequence device for a fast PCI channel, comprising: a control bus for transmitting a plurality of control signals; and a sequence circuit for inputting a first plurality of fast PCI channels and rotating a second plurality Fast PCI lanes, where the sequencing circuit routes the first fast PCI lanes to the second fast ρα lanes in response to the control signal, so that between the first to the second fast PCI lanes and the second to the second fast PCI lanes Form a one-to-one corresponding connection relationship. The descriptions and drawings of the specific embodiments disclosed above are for the convenience of clarifying the technical content and technical means of the present invention, and are not intended to limit the age of the present invention. For example, if you want to modify or change the structural details of the present invention, or the equivalent replacement or replacement of components, without departing from the spirit and scope of the present invention, the scope is defined by the following patent scope. [Brief description of the diagram] FIG. 1 shows a reverse channel sequence connection diagram of a fast PCI with four lanes; FIG. 2 shows a block diagram of a lane ordering circuit according to a specific embodiment of the present invention; The flowchart of the channel sequencing method of the embodiment; and FIG. 4 shows a block diagram of a related system chip with a fast PCI channel sequencing circuit 1221974 circuit according to a specific embodiment of the present invention. [Simple description of component symbols] 100 fast PCI slots 200 chips 210 sequence devices 212 ~ 218 selector 220 control bus 400 peripheral device chips 402 sequence devices 404 ~ 418 fast PCI channels _420 fast PCI slots 440 chip sets
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