TW200506618A - Lane sequencing method for PCI express and the associated devices - Google Patents

Lane sequencing method for PCI express and the associated devices

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Publication number
TW200506618A
TW200506618A TW092121315A TW92121315A TW200506618A TW 200506618 A TW200506618 A TW 200506618A TW 092121315 A TW092121315 A TW 092121315A TW 92121315 A TW92121315 A TW 92121315A TW 200506618 A TW200506618 A TW 200506618A
Authority
TW
Taiwan
Prior art keywords
pci express
lane
peripheral devices
order
sequencing method
Prior art date
Application number
TW092121315A
Other languages
Chinese (zh)
Other versions
TWI221974B (en
Inventor
zhi-rong Lin
Original Assignee
Genesys Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genesys Logic Inc filed Critical Genesys Logic Inc
Priority to TW92121315A priority Critical patent/TWI221974B/en
Application granted granted Critical
Publication of TWI221974B publication Critical patent/TWI221974B/en
Publication of TW200506618A publication Critical patent/TW200506618A/en

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Abstract

The present invention provides a lane sequencing method for PCI express and the associated device, wherein the method includes the following steps: issuing a plurality of packets relating to PCI express lane sequence to notify the peripheral devices, and the peripheral devices reply a plurality of packets relating to the PCI express lane sequence of the peripheral devices; determining if the PCI express lane order of the peripheral devices is correct based on these replied packets; if the lane sequence of the peripheral devices is not correct, appropriately adjusting the order of the PCI express lanes to make the correlation of the PCI express lanes after adjustment being compliant with the normal lane order or the reverse lane order; and, resetting and re-initializing the PCI express lane.
TW92121315A 2003-08-05 2003-08-05 Lane sequencing method for PCI express and the associated devices TWI221974B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92121315A TWI221974B (en) 2003-08-05 2003-08-05 Lane sequencing method for PCI express and the associated devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92121315A TWI221974B (en) 2003-08-05 2003-08-05 Lane sequencing method for PCI express and the associated devices

Publications (2)

Publication Number Publication Date
TWI221974B TWI221974B (en) 2004-10-11
TW200506618A true TW200506618A (en) 2005-02-16

Family

ID=34432997

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92121315A TWI221974B (en) 2003-08-05 2003-08-05 Lane sequencing method for PCI express and the associated devices

Country Status (1)

Country Link
TW (1) TWI221974B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109697181A (en) * 2017-10-23 2019-04-30 联发科技股份有限公司 Method and related electronic device for multi-path sequence adjust automatically

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060081522A (en) * 2005-01-10 2006-07-13 삼성전자주식회사 Method of compensating byte skew for pci express and pci express physical layer receiver for the same
US10585831B2 (en) * 2017-01-27 2020-03-10 Hewlett Packard Enterprise Development Lp PCIe connectors

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109697181A (en) * 2017-10-23 2019-04-30 联发科技股份有限公司 Method and related electronic device for multi-path sequence adjust automatically

Also Published As

Publication number Publication date
TWI221974B (en) 2004-10-11

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MM4A Annulment or lapse of patent due to non-payment of fees