TW202415972A - Embedded chip test device for wafer stack structure - Google Patents

Abstract

The present application discloses an embedded chip test device for wafer stack structure, which connects to a functional circuit. The embedded chip test device for wafer stack structure comprises a processing circuit and a signal conversion circuit. The signal conversion circuit is connected to the functional circuit and the processing circuit. The processing circuit executes a boundary scan program, and generates a testing signal according to the boundary scan program. And the processing circuit transmits the testing signal to the functional circuit through the signal conversion circuit. The functional circuit thereby generates a test result. By the functional test of the embedded chip test device for wafer stack structure, the functional circuit can avoid affecting the overall test rate due to the physical limit of the probe and the transmission speed of the input/output interface of the test machine, so as to achieve the purpose of improving the test efficiency.

Description

Embedded Chip Test Equipment

The present invention relates to a chip testing device, in particular to an embedded chip testing device.

Electronic products are changing with each passing day. To take into account the convenience of users carrying them, their size is gradually shrinking. However, as it is more convenient for users to carry electronic products, their dependence on electronic products has greatly increased, requiring electronic products to provide faster computing capabilities.

Currently, the realization of the functions of electronic products mainly relies on the electrical connection between components to transmit signals through the electrical connection between each other. In order to confirm that the functions of each component can operate normally, before each component is assembled, a test machine must be provided according to the function of each component. The test machine has an input/output interface. Then, after a probe is connected to the input/output interface, the probe is further brought into contact with the test point of the corresponding component so that the test machine can send a test signal to the component through the probe. Then, the component will transmit a test result to the test machine through the probe according to the test signal, and the test machine will analyze whether the component can operate normally according to the test result.

However, as electronic products become smaller and smaller and require faster computing, the test points of each circuit on the chip will be closer to each other. When testing a test point, the probe of the test machine is limited by physical limitations. If the test point is still tested through the probe, it may contact the test points of other circuits on the chip, which will cause test errors and affect the overall test efficiency. In addition, since it is necessary to ensure that the components can function normally before assembly, each component must be tested, which takes a lot of time. The test speed of the test machine is limited by the transmission speed of the input/output interface, which also affects the test efficiency.

Therefore, the prior art is indeed in need of further providing a more improved solution.

In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is to provide an embedded chip testing device that avoids the physical limitations of the probe and the transmission speed of the input/output interface of the testing machine through internal testing technology to achieve the purpose of improving testing efficiency.

To achieve the above purpose, the main technical means adopted by the present invention is to make the embedded chip test device electrically connected to a functional circuit. The embedded chip test device includes: A processing circuit; A signal conversion circuit electrically connected to the functional circuit and the processing circuit; Wherein, the processing circuit executes a boundary scanning program, generates a test signal according to the boundary scanning program, and sends it to the functional circuit through the signal conversion circuit to generate a corresponding test result.

Through the above structure, the embedded chip test device is directly electrically connected to the line of the functional circuit, so that the embedded chip test device can directly send the test signal to the functional circuit according to the boundary scanning program to test whether the functional circuit is normal. In this way, the functional test of the functional circuit directly performed by the embedded chip test device can avoid the overall test rate being affected by the physical limitations of the probe and the transmission speed of the input/output interface of the test machine, thereby achieving the purpose of improving the test efficiency.

The following is a description of the implementation of the present invention through specific embodiments. People skilled in the art can understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

As shown in FIG. 1 , the embedded chip test device 10 of the present invention is directly electrically connected to a functional circuit 20 to test the functional circuit 20 to confirm whether the function is normal.

In the present embodiment, as shown in FIG. 2 , a wafer stacking structure is formed by a wafer on wafer (WOW) process, and the wafer stacking structure includes a substrate 30, a logic circuit layer 40, and a memory crystal layer 50. The substrate 30 is electrically connected to the logic circuit layer 40 through a plurality of first connection pads 31, and the logic circuit layer 40 is electrically connected to the memory crystal layer 50 through a plurality of second connection pads 41. The embedded chip test device 10 and the functional circuit 20 are disposed in the logic circuit layer 40.

In addition, in this embodiment, the functional circuit 20 can also be set in the memory crystal layer 50, and the embedded chip test device 10 transmits signals with the functional circuit 20 through the plurality of second connection pads 41. Since the width of each of the first connection pads 31 and the second connection pads 41 in the wafer stacking structure is less than 1µm, the embedded chip test device 10 of the present invention can more easily test the logic circuit layer 40 or the memory crystal layer 50, avoiding the physical limit of the probe and the transmission speed of the input/output interface of the test machine, so as to achieve the purpose of improving the test efficiency.

Regarding a specific embodiment of the embedded chip test device 10 of the present invention, as shown in FIG3 , the embedded chip test device 10 includes a processing circuit 11 and a signal conversion circuit 12, the signal conversion circuit 12 is electrically connected to the functional circuit 20 and the processing circuit 11, the processing circuit 11 executes a boundary scan program, generates a test signal according to the boundary scan program, and sends the test signal to the functional circuit 20 via the signal conversion circuit 12 to generate a test result. In this embodiment, the functional circuit 20 can be a plurality of functional circuits, the functional circuits 20 are different functions (for example: wireless communication function, memory function), and the functional circuits 20 are electrically connected to the processing circuit 11 respectively.

In this embodiment, as shown in FIG. 4 , the embedded chip test device 10 is further electrically connected to a power supply circuit 60 , and the power supply circuit 60 is electrically connected to the processing circuit 11 and the functional circuit 20 , respectively, to provide a power signal to the processing circuit 11 and the functional circuit 20 .

In the present embodiment, as shown in FIG5 , the embedded chip test device 10 further includes a signal switch 13, the signal switch 13 is electrically connected to the signal conversion circuit 12, the signal switch 13 selectively receives the test signal from the signal conversion circuit 12 to test the functional circuit 20, and further, in order to integrate an external test device (not shown), the signal switch 13 is separately connected to the external test device to obtain an external test signal of the external test device. At this time, when the external test signal of the external device is obtained, the signal switch 13 will switch to connect to the external device, so that the functional circuit 20 can receive the external test signal of the external test device, so as to test the functional circuit 20 according to the external test signal to generate the test result. In this embodiment, the signal switch 13 can be a multiplexer.

In this embodiment, still referring to FIG. 5 , the embedded chip test device 10 further includes the non-volatile memory 14, the non-volatile memory 14 is electrically connected to the processing circuit 11, and the non-volatile memory 14 stores the boundary scanning program. In this embodiment, the non-volatile memory 14 can be a flash memory or a read-only memory (ROM).

In this embodiment, as shown in FIG. 6 , the processing circuit 11 includes a processor 110, an advanced high performance bus (AHB) 111, and a bridge 112. The processor 110 is electrically connected to the advanced high performance bus 111, and the advanced high performance bus 111 is electrically connected to the bridge 112. The processor 110 executes the boundary scanning program and generates the test signal according to the boundary scanning program, and transmits the test signal through the advanced high performance bus. In this embodiment, the bridge 112 is further electrically connected to the non-volatile memory 14 to obtain the boundary scanning program from the non-volatile memory 14 and send the boundary scanning program to the processor 210 through the advanced high-performance bus 111. In this embodiment, the processor 110 can be a RISC-V architecture, an ARM architecture or an eFPGA.

In this embodiment, still referring to FIG. 6 , the signal conversion circuit 12 includes a signal test function module 120 and a volatile memory 121. The signal test module 120 is electrically connected to the function circuit 20, the advanced high-performance bus 111 and the bridge 112. The volatile memory 121 is electrically connected to the function circuit 20 and the advanced high-performance bus 111. In this embodiment, the volatile memory 121 can be a random access memory (RAM).

In this embodiment, as shown in FIG. 7 , the bridge 112 further includes a queued serial peripheral interface (QSPI) 113 and a general-purpose input/output (GPIO) 114. The queued serial peripheral interface 113 is electrically connected to the non-volatile memory 14 and the advanced high-performance bus 111, respectively, and the general-purpose input/output (GPIO) 114 is electrically connected to the advanced high-performance bus 111 and the signal test function module 120, respectively.

In the above-mentioned embodiment, the boundary scanning procedure includes a short circuit/open circuit test procedure, a DC voltage signal test procedure, a chip logic function test procedure, an AC signal test procedure or a mixed circuit function test procedure. In this embodiment, the processor 110 sends the test signal in accordance with different test procedures of the test procedure. For example, when the processor 110 wants to execute the short circuit/open circuit test procedure on the functional circuit 20, the test signal sent accordingly is the short circuit/open circuit test signal to the functional circuit 20. Then, after the functional circuit 20 receives the short circuit/open circuit test signal, the test result is generated and transmitted to the volatile memory 121 for storage, so as to provide the test personnel with information on whether the functional circuit 20 has a short circuit/open circuit from the volatile memory 121.

In summary, the embedded chip test device 10 is directly electrically connected to the line of the functional circuit 20, so that the embedded chip test device 10 can directly send the test signal to the functional circuit 20 according to the boundary scanning program to test whether the functional circuit 20 is normal. In this way, the functional test of the functional circuit 20 directly performed by the embedded chip test device 10 can avoid the overall test rate being affected by the physical limit of the probe and the transmission speed of the input/output interface of the test machine, thereby achieving the purpose of improving the test efficiency.

The above embodiments are merely illustrative of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify and alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the patent application described below.

10: Embedded chip test device 11: Processing circuit 110: Processor 111: Advanced high-performance bus 112: Bridge 113: Queued serial peripheral interface 114: General-purpose input/output pins 12: Signal conversion circuit 120: Signal test function module 121: Volatile memory 13: Signal switch 14: Non-volatile memory 20: Functional circuit 30: Substrate 31: First connection pad 40: Logic circuit layer 41: Second connection pad 50: Memory crystal layer 60: Power supply circuit

FIG1 is a block diagram of the present invention applied to a system on a chip; FIG2 is a cross-sectional block diagram of a wafer stack of the present invention; FIG3 is a block diagram of a specific embodiment of an embedded test device of the present invention; FIG4 is a block diagram of the present invention connected to a power supply circuit; FIG5 is a block diagram of another specific embodiment of an embedded test device of the present invention; FIG6 is a block diagram of another specific embodiment of an embedded test device of the present invention; and FIG7 is a block diagram of yet another specific embodiment of an embedded test device of the present invention.

10:Embedded chip testing equipment

20: Functional circuit

Claims (9)

An embedded chip test device is electrically connected to a functional circuit, and includes: a processing circuit; and a signal conversion circuit electrically connected to the functional circuit and the processing circuit; wherein the processing circuit executes a boundary scanning program, generates a test signal according to the boundary scanning program, and sends the test signal to the functional circuit via the signal conversion circuit to generate a corresponding test result. An embedded chip test device as described in claim 1, wherein the embedded chip test device further comprises: a signal switch electrically connected to the signal conversion circuit; and wherein the signal switch selectively receives the test signal from the signal conversion circuit. An embedded chip test device as described in claim 1, wherein the embedded chip test device comprises: A non-volatile memory electrically connected to the processing circuit and storing the boundary scanning program. An embedded chip test device as described in claim 3, wherein the processing circuit includes: a processor that executes the boundary scanning program; an advanced high-performance bus that is electrically connected to the processor; and a bridge that is electrically connected to the advanced high-performance bus. The embedded chip test device as described in claim 4, wherein the signal conversion circuit includes: a signal test function module electrically connected to the function circuit, the advanced high-performance bus and the bridge; and a volatile memory electrically connected to the function circuit and the advanced high-performance bus. An embedded chip testing device as described in claim 5, wherein the non-volatile memory is electrically connected to the bridge. An embedded chip test device as described in claim 6, wherein the bridge includes: A queued serial peripheral interface electrically connected to the non-volatile memory and the advanced high-performance bus. The embedded chip test device as described in claim 6, wherein the bridge further comprises: A universal input/output pin electrically connected to the advanced high-performance bus and the signal test function module. An embedded chip testing device as described in any one of claims 1 to 8, wherein the boundary scanning program includes a short circuit/open circuit test program, a DC current voltage signal test program, a chip logic function test program, an AC signal test program or a mixed circuit function test program.

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