CN111579974B - Embedded system for realizing boundary scan test and test method - Google Patents
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- CN111579974B CN111579974B CN202010516136.3A CN202010516136A CN111579974B CN 111579974 B CN111579974 B CN 111579974B CN 202010516136 A CN202010516136 A CN 202010516136A CN 111579974 B CN111579974 B CN 111579974B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
Abstract
The invention belongs to the technical field of digital circuit testing, and discloses a tested module, an embedded system and a testing method for realizing boundary scan testing, which are used for performing boundary scan testing on a digital circuit module. The system of the invention comprises an embedded boundary scan test controller and a tested module, which are interconnected through a JTAG bus: the controller comprises an FPGA and a peripheral chip; the FPGA comprises an ARM and a JTAG control logic module; the JTAG control logic module is used for realizing JTAG signal input and output control; the ARM receives and analyzes the boundary scan test command, generates a boundary scan test sequence, accesses the tested module through the JTAG bus, and recovers test response data after the tested module executes the boundary scan test; the tested module comprises a JTAG routing chip and a system function circuit which needs to carry out boundary scan test. The invention can solve the problems of on-line test and fault diagnosis of the radar related digital circuit module.
Description
Technical Field
The invention belongs to the technical field of digital circuit testing, and particularly relates to an embedded system and a testing method for realizing boundary scan testing.
Background
JTAG (Joint Test Action Group) is an international standard Test protocol (IEEE 1149.1) and is mainly used for chip testing. The working principle of JTAG can be summarized as follows: a TAP (Test Access Port) is defined in the device, and the internal nodes are tested and debugged through a special JTAG Test tool. The boundary scan test technology is a test structure and a test technology established on the IEEE1149.1 standard, has become a main means for testing and diagnosing complex digital circuits, and is widely used for offline testing of digital circuit boards. During testing, the digital circuit board is taken out from the radar system, and testing is completed by using the testing system integrating the boundary scanning testing function. Experts in 2016, boeing, usa, and a.t.e.solutions, inc. introduce a new embedded test technique based on boundary scan testing that can significantly increase the fault detection and isolation rates of digital circuits.
With the rapid development of digital radar technology, digital circuits are widely used in radar systems. In China, the boundary scan technology is also one of the main means for testing the radar digital circuit module, the boundary scan testing technology is only used for the offline test of the radar digital circuit module (the digital circuit module needs to be detached from a radar system) at present and is not used for the system level test, and the radar BIT data and health management subsystem does not contain any related content of the boundary scan test.
The chinese patent application with application number 200810207928.1 discloses an embedded module testing and maintaining bus system, which comprises a bus monitor and a plurality of embedded module testing and maintaining bus interface units connected through a TM bus, wherein the embedded module testing and maintaining bus interface units are connected with the bus monitor, and a master-slave communication protocol is adopted between the embedded module testing and maintaining bus interface units; the embedded module test and maintenance bus interface unit comprises a master module and a slave module, the logic processing parts of the master module and the slave module are positioned in the same chip, and the slave modules are distinguished through input module identifiers. However, the test method adopted by the system is actually a test method for the embedded module, and is not a method for embedded test; the main module and the subordinate module of the system are both required to be designed with a control interface circuit taking a processor as a core, control functions such as data receiving and transmitting, packaging and unpacking are realized, only testing can be performed, data receiving and transmitting are completed, diagnosis is completed by an upper computer, diagnosis cannot be realized by the embedded module testing and maintaining bus system, and therefore a test result conclusion is directly given, namely, an online fault diagnosis function cannot be realized, and the design cost of software and hardware is increased.
Disclosure of Invention
The invention aims to: aiming at the defects of the prior art, the embedded system and the test method for realizing the boundary scan test are provided, and the problems of online test and fault diagnosis of the digital circuit module can be solved.
Specifically, the invention is realized by adopting the following technical scheme.
In one aspect, the present invention provides an embedded system for implementing boundary scan test, comprising an embedded boundary scan test controller and a module under test for implementing boundary scan test according to claim 1, wherein the embedded boundary scan test controller and the module under test are interconnected via JTAG bus;
the embedded boundary scan test controller comprises an FPGA and a peripheral chip; the peripheral chip provides a CAN bus interface or an Ethernet interface; the FPGA comprises an ARM and a JTAG control logic module; the JTAG control logic module is used for realizing JTAG signal input and output control; ARM receives and analyzes the boundary scan test command from CAN bus interface or Ethernet interface, produce the test sequence of boundary scan, visit the module to be tested through JTAG bus, after the module to be tested carries out the boundary scan test, reclaim the test response data of boundary scan;
the module to be tested comprises a JTAG routing chip and a system functional circuit which needs to carry out boundary scan test, and the module to be tested receives a boundary scan test sequence through a JTAG bus and executes the boundary scan test of the system functional circuit; the main port of the JTAG routing chip is connected with a JTAG bus, the slave port is connected with a JTAG interface of a boundary scanning link of each component in the tested module, and the received boundary scanning test sequence is transmitted to each component in the tested module after level conversion.
Furthermore, the embedded system for realizing the boundary scan test also comprises a back plate, the back plate is provided with a JTAG bus, each tested module is accessed to the JTAG bus through the back plate, the JTAG bus communication is controlled by the embedded boundary scan test controller, and the signal interconnection of the embedded boundary scan test controller and the JTAG buses of all the tested modules is realized.
Furthermore, the ARM runs an embedded boundary scan test program, the program receives and analyzes a boundary scan test command from a CAN bus interface or an Ethernet interface to generate a boundary scan test sequence, accesses the tested module through a JTAG bus, and recovers boundary scan test response data after the tested module executes the boundary scan test.
Furthermore, the embedded boundary scan test controller is integrated in a digital circuit module of the module under test and is independent from a system function circuit of the module under test.
Further, the embedded boundary scan test controller starts a fault diagnosis program to complete fault diagnosis according to the recovered boundary scan test response data.
In another aspect, the present invention further provides an embedded method for implementing boundary scan test, which is implemented by the above embedded system for implementing boundary scan test, and includes the following steps:
the ARM receives a boundary scan test command from a CAN bus or an Ethernet and analyzes the boundary scan test command;
the ARM runs an embedded boundary scan test program according to the analyzed boundary scan test command, generates a boundary scan test sequence through a JTAG control logic module, addresses a JTAG route of the tested module through a JTAG bus, accesses the selected tested module through the JTAG bus after addressing is completed, and transmits the boundary scan test sequence to the tested module through the JTAG route of the selected tested module;
the selected tested module executes the boundary scanning test according to the boundary scanning test sequence;
and the selected tested module transmits the boundary scan test response data after the boundary scan test is executed back to the ARM of the embedded boundary scan test controller through the JTAG routing chip and the JTAG bus so as to complete the acquisition and storage of the boundary scan test data.
Furthermore, the peripheral chip comprises a FLASH chip, the embedded boundary scan test program is stored in the FLASH chip of the embedded boundary scan test controller, and the ARM loads the embedded boundary scan test program from the FLASH chip.
The embedded method for realizing the boundary scan test further comprises the following steps after the boundary scan test data acquisition and storage are finished: and the ARM starts a fault diagnosis program to diagnose faults, stores the diagnosis result into a memory and uploads the diagnosis result through a CAN bus or an upper computer network port to finish embedded boundary scanning on-line test and diagnosis. .
The embedded system and the test method for realizing the boundary scan test have the following beneficial effects:
by adopting a JTAG routing chip to design a boundary scanning test link in a module under test (UUT), the embedded boundary scanning test controller can access the UUT on line, and the UUT can receive a boundary scanning test access instruction of the embedded boundary scanning test controller and execute corresponding boundary scanning test through a JTAG routing. Compared with the prior art that the UUT is required to be detached from the work plug box and then is subjected to off-line testing, the method and the device can realize real system-level boundary scan testing, and the boundary scan testing efficiency is higher.
The embedded boundary scan test controller is integrated in the digital circuit module in an independent functional circuit mode, so that the variety and the number of the subsystem modules are reduced, and the cost and the space are saved for the highly integrated digital circuit module of the tested system. And the embedded boundary scan test controller can be used as a standardized circuit, can be designed in a digital circuit module with relatively low integration level according to the comprehensive requirement of the integration level of all digital circuit modules in a tested system, and has flexible functional design. The embedded boundary scan test controller is integrated in any digital circuit module of the subsystem, can realize the embedded boundary scan test function of all functional modules of the tested system, and is not restricted by position.
The embedded boundary scan test controller is integrated in a certain UUT. In the UUT, except the embedded boundary scan test controller circuit, the rest circuits (belonging to the digital circuit module of the tested system) realize the boundary scan link management based on the JTAG route, so that the boundary scan on-line test of the digital circuit modules of all the tested systems can be realized, and the problems of the boundary scan on-line test and the fault diagnosis of the digital circuit modules of the tested systems are solved.
Drawings
Fig. 1 is a block diagram of an embedded system implementing boundary scan testing according to the present embodiment.
FIG. 2 is a functional block diagram of a digital circuit module including an embedded boundary scan test controller according to the present embodiment.
FIG. 3 is a functional block diagram of the FPGA internal JTAG control logic of the embedded boundary scan test controller of the present embodiment.
Fig. 4 is a JTAG link connection diagram of the UUT based on JTAG routing according to the present embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following examples and the accompanying drawings.
Example 1:
an embodiment of the present invention provides an embedded system and a system-level boundary scan test method for implementing boundary scan test, which take the system-level boundary scan test on a digital circuit module (hereinafter referred to as a measured digital circuit module) of a radar signal processing subsystem as an example.
As shown in fig. 1, the embedded system for implementing boundary scan Test in this embodiment mainly includes an embedded boundary scan Test controller and a UUT (Unit Under Test) based on JTAG routing. The embedded system for realizing the boundary scan test of the embodiment adopts a working plug-in box structure actually used by a radar signal processing subsystem. The embedded system for implementing boundary scan testing of the embodiment performs boundary scan testing and fault diagnosis on the system functional circuit of each UUT. The digital circuit module of each UUT comprises a JTAG routing chip and a system function circuit which needs to carry out boundary scan test. The system function circuit of each UUT forms a digital circuit module (namely a tested digital circuit module) of the radar signal processing subsystem, and the system function of the radar signal processing subsystem is realized. The embedded boundary scan test controller is a core module of the embedded system for realizing the boundary scan test, and is used for realizing the control and management functions of the boundary scan test on each UUT, thereby realizing the system-level embedded boundary scan online test and fault diagnosis. The back board in the plug box is provided with JTAG buses, each plug board (namely UUT) is provided with a JTAG route, the JTAG buses are accessed through the back board, the JTAG bus communication is controlled by the embedded boundary scan test controller, and the JTAG bus signal interconnection of the embedded boundary scan test controller and all the system function circuits of the UUT is realized.
A plug board where the embedded boundary scan test controller is located adopts a double-FPGA + exchange chip architecture, wherein one FPGA is used for the embedded boundary scan test controller, and the other FPGA and the exchange chip are used for a system function circuit (namely a circuit for realizing corresponding functions of a radar signal processing subsystem) of the plug board (namely UUT).
The embedded boundary scan test controller is realized by an FPGA and a peripheral chip. The peripheral chip includes: FLASH, memory (e.g., DDR3), CAN transceivers, PHY chips, etc.
The FPGA is a core component of the embedded boundary scan controller, and completes operations such as boundary scan test selection (selecting JTAG route and test item of the tested UUT), boundary scan test sequence generation (the test sequence comprises information such as boundary scan test access instruction and test item), boundary scan test sequence sending and test response data acquisition, fault diagnosis and fault positioning, test result storage control and the like by operating the embedded boundary scan test program. FLASH is used for solidifying the storage of the embedded boundary scanning test program; the memory is used for the access of the test data and the temporary data; designing a CAN bus interface of the tested digital circuit module through a CAN transceiver; an ethernet interface for communicating with an upper computer is designed through a PHY chip, and is used for communicating with the upper computer by the embedded system for implementing the boundary scan test of the embodiment.
The circuit of the embedded boundary scan test controller is integrated in a digital circuit module of a UUT, and is independent from the system function circuit of the UUT, as shown in fig. 2. The digital circuit module of the UUT is designed based on JTAG route, and realizes the boundary scanning link management of the system function circuit (namely the circuit for realizing the corresponding function of the radar signal processing subsystem) in the UUT.
The FPGA adopts an ARM + JTAG control logic module architecture. ARM is used for embedded boundary scan test control and management central processing unit, adopts LINUX operating system, runs the program after loading the embedded boundary scan test program from FLASH, finishes the operations such as boundary scan test selection, boundary scan test sequence generation, fault diagnosis and fault location, test result storage control, etc.
And the ARM receives a boundary scanning test command from the CAN bus or the network port of the upper computer and completes analysis. The ARM completes generation and sending of related hardware initialization setting (including JTAG route initialization, selection of test speed and the like) data and a boundary scan test sequence in the embedded system for realizing the boundary scan test according to the analyzed boundary scan test command, controls the JTAG control logic module to complete recovery of test response data, stores the recovered boundary scan test response data, calls a fault diagnosis program to complete diagnosis, stores fault diagnosis result data, and selectively uploads the diagnosis result data or the test response data through a CAN bus or an upper computer network port.
The JTAG control logic block is used to implement five JTAG signal (TDI, TDO, TMS, TCK, TRST /) input-output control, as shown in FIG. 3. The JTAG control logic module is connected with a JTAG routing main port of a back plate JTAG bus and a UUT, and can provide a JTAG test interface for each UUT (including the UUT where the embedded boundary scan test controller is located) through the JTAG bus on the back plate so as to complete boundary scan test sequence sending and boundary scan test response data acquisition. The JTAG control logic module writes relevant data (internal address, data and control bus data from the ARM) of a boundary scan test sequence analyzed and generated in the internal ARM of the FPGA into the internal FIFO, sends test sequence data through TDI serial under the control of a test clock CLK _ O, sends test control data through TMS serial, sends test clock data through TCK serial, sends a reset control signal through TRST/signal, collects serially-input boundary scan test response data through TDO end, and sends the serially-input boundary scan test response data to the ARM through the internal FIFO for processing. The testing speed supported by the JTAG control logic module can be configured, and 0.25MHz, 0.5MHz, 1MHz, 2MHz, 5MHz, 10MHz, 20MHz and 25MHz can be selected to adapt to the testing speed requirements of different UUTs.
The embedded system for realizing the boundary scan test of the embodiment breaks away from the constraint of a computer, can automatically run a boundary scan test program and a fault diagnosis program in the embedded boundary scan test controller to complete the boundary scan test and the fault diagnosis function, takes the FPGA as a core, realizes the reasonable configuration and optimization of hardware resources, and occupies less software and hardware resources.
The UUT based on the JTAG route adopts a JTAG route chip to design a UUT inner boundary scanning test link, and the UUT can receive a boundary scanning test access instruction of an embedded boundary scanning test controller and execute a corresponding boundary scanning test. The JTAG link connection mode of the UUT based on JTAG routing is shown in FIG. 4. And a main port of a JTAG routing chip of the UUT is connected with a JTAG bus of the back plate, a secondary port is connected with a JTAG interface of each component boundary scanning link of the system function circuit in the UUT, and a test sequence is transmitted to each component in the UUT after level conversion so as to complete the boundary scanning link management of the UUT. The address bus of the JTAG routing chip in the UUT is connected with the corresponding slot address bus of the backboard, so that the JTAG routing address of each UUT is unique. JTAG bus interconnection of corresponding slots of all tested UUTs is realized on the backboard, JTAG bus signals comprise TDI, TDO, TMS, TCK and TRST/, and the JTAG bus signal speed supported by the system backboard is not lower than 50 MHz.
The digital circuit module of the socket (i.e. UUT) where the embedded boundary scan test controller is located includes a system function circuit. In the digital circuit module, an embedded boundary scan test controller is independent of a system function circuit; except for the embedded boundary scan test controller, other circuits realize boundary scan link management based on JTAG route, so that the system level embedded boundary scan online test of all UUTs in the embedded system for realizing boundary scan test of the embodiment can be realized.
The execution process of the embedded method for realizing boundary scan test of the embodiment is as follows:
(1) all the boundary scan test programs of the UUT of the embedded system for implementing the boundary scan test in this embodiment are stored in the FLASH chip of the embedded boundary scan test controller. After the embedded system for implementing boundary scan test in this embodiment is powered on and normally loaded, the ARM of the FPGA of the embedded boundary scan test controller loads the boundary scan test program of each UUT from the FLASH chip, receives a boundary scan test command from the CAN bus or the ethernet, and analyzes the boundary scan test command.
(2) The ARM of the embedded boundary scan test controller starts a boundary scan test program of a corresponding UUT according to an analyzed boundary scan test command, generates an actual boundary scan test sequence according to the IEEE1149.1 standard through a JTAG control logic module in the FPGA, addresses a JTAG route of the UUT through a JTAG bus of the backboard, accesses the selected UUT through the JTAG bus of the backboard through a boundary scan test access command after addressing is completed, and sends related data (hardware initialization setting data and the boundary scan test sequence) of the boundary scan test program to the UUT through the JTAG route of the selected UUT.
(3) The selected UUT performs boundary scan testing.
(4) The result data (namely boundary scan test response data) of the selected UUT executing the boundary scan test is transmitted back to the ARM of the embedded boundary scan test controller through the JTAG routing chip of the UUT and the JTAG bus of the back plate, and the boundary scan test data acquisition and storage are completed.
(5) And the ARM starts a fault diagnosis program to diagnose faults, stores the diagnosis result into a memory and uploads the diagnosis result through a CAN bus or an upper computer network port to finish embedded boundary scanning on-line test and diagnosis.
(6) And sequentially carrying out the same addressing access and boundary scanning test on other UUTs to finish the storage and uploading of the test result, wherein the data of the boundary scanning test result of different UUTs cannot be covered for subsequent maintenance and query. And after addressing access, executing boundary scan test by circuits except the embedded boundary scan test controller, transmitting the boundary scan test response data to the embedded boundary scan test controller through a JTAG route, and performing fault diagnosis. Therefore, boundary scan online test diagnosis of all UUTs is completed, and the problems of boundary scan online test and fault diagnosis of the digital circuit module to be tested are solved.
The embedded system and the test method for realizing the boundary scan test integrate the embedded boundary scan test controller into the digital circuit module of the UUT in an independent functional circuit mode, reduce the variety and the number of the digital circuit modules to be tested, and save the cost and the space for a highly integrated radar signal processing subsystem. The embedded boundary scan test controller can be used as a standardized circuit, can be designed in a digital circuit module with relatively low integration level according to the comprehensive requirement of the integration level of all digital circuit modules in a system needing boundary scan test, and is flexible in functional design. The embedded boundary scan test controller is integrated in any UUT of the digital circuit module to be tested, can realize the embedded boundary scan test function of all system functional circuits, and is not restricted by position. The whole boundary scanning test and diagnosis process is not restricted by an upper computer, all embedded boundary scanning test programs and fault diagnosis programs are realized in the embedded boundary scanning test controller, the defect of insufficient online diagnosis capability of a tested digital circuit module (namely a radar digital signal processing subsystem) is overcome, and effective data support is provided for the radar health management subsystem.
The embedded system and the test method for realizing the boundary scan test provide a system-level boundary scan test method for a radar signal processing subsystem digital circuit module, provide a design method for the embedded boundary scan test, and provide a test means and a test platform for the online test and the fault diagnosis of the radar digital circuit module. The BIT and health management subsystems of the radar system lack on-line testing means and fault diagnosis capability, and by the embedded boundary scanning testing method, the boundary scanning on-line testing and fault diagnosis of the radar digital correlation subsystem are realized, effective data support is provided for the radar health management subsystem, and the BIT level and comprehensive guarantee capability of a new-generation radar are improved.
In some embodiments, certain aspects of the techniques described above may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid state storage device such as flash memory, cache, Random Access Memory (RAM), etc., or other non-volatile memory device. Executable instructions stored on a non-transitory computer-readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executed by one or more processors.
A computer-readable storage medium may include any storage medium or combination of storage media that is accessible by a computer system during use to provide instructions and/or data to the computer system. Such storage media may include, but is not limited to, optical media (e.g., Compact Discs (CDs), Digital Versatile Discs (DVDs), blu-ray discs), magnetic media (e.g., floppy disks, tape, or magnetic hard drives), volatile memory (e.g., Random Access Memory (RAM) or cache), non-volatile memory (e.g., Read Only Memory (ROM) or flash memory), or micro-electromechanical systems (MEMS) -based storage media. The computer-readable storage medium can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., a magnetic hard drive), removably attached to a computing system (e.g., an optical disk or Universal Serial Bus (USB) based flash memory), or coupled to a computer system via a wired or wireless network (e.g., Network Accessible Storage (NAS)).
Note that not all of the activities or elements in the general description above are required, that a portion of a particular activity or device may not be required, and that one or more further activities or included elements may be performed in addition to those described. Still further, the order in which the activities are listed need not be the order in which they are performed. Moreover, these concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present disclosure.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims in any or all respects. Moreover, the particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.
Claims (6)
1. An embedded system for realizing boundary scan test is characterized by comprising an embedded boundary scan test controller, a tested module and a back plate, wherein the embedded boundary scan test controller is interconnected with a routing chip of the tested module through a JTAG bus;
the embedded boundary scan test controller is integrated in a digital circuit module of a tested module and is independent from a system function circuit of the tested module; the embedded boundary scan test controller comprises an FPGA and a peripheral chip; the peripheral chip provides a CAN bus interface or an Ethernet interface; the FPGA comprises an ARM and a JTAG control logic module; the JTAG control logic module is used for realizing JTAG signal input and output control; the ARM loads the boundary scan test programs of all tested modules, receives and analyzes a boundary scan test command from the CAN bus interface or the Ethernet interface, runs the boundary scan test program of the corresponding tested module, completes the boundary scan test selection, generates a boundary scan test sequence, accesses the tested module through the JTAG bus, and recovers the boundary scan test response data and carries out fault diagnosis after the tested module executes the boundary scan test;
the module to be tested comprises a JTAG routing chip and a system functional circuit which needs to carry out boundary scan test, and the module to be tested receives a boundary scan test sequence through a JTAG bus and executes the boundary scan test of the system functional circuit; the main port of the JTAG routing chip is connected with a JTAG bus, the slave port is connected with a JTAG interface of a boundary scanning link of each component in the tested module, and the received boundary scanning test sequence is transmitted to each component in the tested module after level conversion;
the back board is provided with JTAG buses, each tested module is accessed into the JTAG buses through the back board, and JTAG bus communication is controlled by the embedded boundary scan test controller, so that the signal interconnection of the embedded boundary scan test controller and the JTAG buses of all the tested modules is realized.
2. The embedded system for implementing boundary scan testing of claim 1, wherein the ARM runs an embedded boundary scan testing program, the program implements receiving and parsing boundary scan testing commands from the CAN bus interface or the Ethernet interface, generating boundary scan testing sequences, accessing the module under test through the JTAG bus, and recovering boundary scan testing response data after the module under test performs boundary scan testing.
3. The embedded system for implementing boundary scan testing of claim 1, wherein the embedded boundary scan test controller initiates a fault diagnosis procedure to complete fault diagnosis according to the recovered boundary scan test response data.
4. An embedded method for implementing boundary scan test, which is implemented by the embedded system for implementing boundary scan test according to any one of claims 1 to 3, comprising the following steps:
the ARM receives a boundary scan test command from a CAN bus or an Ethernet and analyzes the boundary scan test command;
the ARM runs an embedded boundary scan test program according to the analyzed boundary scan test command, generates a boundary scan test sequence through a JTAG control logic module, addresses a JTAG route of the tested module through a JTAG bus, accesses the selected tested module through the JTAG bus after addressing is completed, and transmits the boundary scan test sequence to the tested module through the JTAG route of the selected tested module;
the selected tested module executes the boundary scanning test according to the boundary scanning test sequence;
and the selected tested module transmits the boundary scan test response data after the boundary scan test is executed back to the ARM of the embedded boundary scan test controller through the JTAG routing chip and the JTAG bus so as to complete the acquisition and storage of the boundary scan test data.
5. The embedded method for implementing boundary scan test of claim 4, wherein the peripheral chip comprises a FLASH chip, the embedded boundary scan test program is stored in the FLASH chip of the embedded boundary scan test controller, and the ARM loads the embedded boundary scan test program from the FLASH chip.
6. The embedded method for implementing boundary scan test of claim 4, further comprising after completing the collection and storage of boundary scan test data: and the ARM starts a fault diagnosis program to diagnose faults, stores the diagnosis result into a memory and uploads the diagnosis result through a CAN bus or an upper computer network port to finish embedded boundary scanning on-line test and diagnosis.
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