CN104515951A - Board-level embedded test controller and board-level embedded test method - Google Patents
Board-level embedded test controller and board-level embedded test method Download PDFInfo
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- CN104515951A CN104515951A CN201410705687.9A CN201410705687A CN104515951A CN 104515951 A CN104515951 A CN 104515951A CN 201410705687 A CN201410705687 A CN 201410705687A CN 104515951 A CN104515951 A CN 104515951A
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Abstract
The invention discloses a board-level embedded test controller and a board-level embedded test method. The controller comprises a digit circuit test unit, an analog circuit test unit, a test process management unit and a test data generating, downloading and uploading unit. The method includes: firstly, using the data generation unit to create testable items of a circuit board under test, generating test data, downloading the test data to the embedded test controller, connecting the embedded test controller to the tested circuit board, enabling the controller to start embedded test after power-on, starting the corresponding digit circuit test unit and the analog circuit test unit to control the test process through the test process management unit according to test data, and storing corresponding test results. Test resources are reconfigurable, external test equipment is not required during testing, testing capability can be improved, and occupation of test resources is reduced.
Description
Technical field
The invention belongs to electronic system test and fault diagnosis field, particularly circuit board level embedded testing, does not adopt the technical field of external test facility.
Background technology
Along with the development of microelectric technique, the densification of electronic devices and components adds difficulty to the acquisition of test signal, brings challenge to the maintenance diagnostics of circuit board.Board structure of circuit and function complicated and diversified, make to adopt simple external testing means cannot the 26S Proteasome Structure and Function of abundant testing circuit board, and the high density of circuit board makes limited spatially can not apply enough test points, also more and more higher to the requirement of the fixture required for testing apparatus and probe, cost intensive.And for small serial production object, dissimilar circuit board needs the testing apparatus adopted, and can increase much extra fund input.And generally cannot carry a large amount of testing apparatuss for field level detection, require to test fast, therefore, need to adopt the method for embedded testing to improve Test coverage ability, shorten the test duration.
Summary of the invention
In view of this, the present invention, on the basis of existing measuring technology, provides a kind of plate level embedded test controller and method of testing, cannot realize or realize the higher problem of cost to solve circuit board utilizing external test facility, the Test coverage ability of circuit board can be improved, accelerate test speed.
The present invention is achieved through the following technical solutions:
A kind of plate level embedded test controller, comprising: digital circuit test unit, analog circuit test unit, testing process administrative unit, Test data generation and download uploading unit;
Described digital circuit test unit, realizes digital circuits section test and diagnostic, comprises boundary scan testing, IO test, communication bus test;
Described analog circuit test unit, realizes simulation and Digital Analog Hybrid Circuits partial test and diagnosis, comprises voltage monitoring, waveform occurs, input;
Described testing process administrative unit, for controlling the flow process of the mode of operation of embedded test controller, test pattern and whole test, realizes resource management and the scheduling of whole embedded testing process;
Described Test data generation and download uploading unit, realize numeral, simulation test desired data generate, and be downloaded to embedded test controller, and upload test result.
Described digital circuit test unit, comprises 1149.1 jtag interfaces, I/O interface, UART interface, SCI interface, SPI interface, I2C interface.
Described mode of operation comprises:
Standby mode, controller is in low power consumpting state;
Downloading mode, controller is in the state downloading test data;
Test pattern, controller is in the state performing embedded testing.
Described test pattern comprises:
Power-on self-test pattern, after powering on, embedded test controller starts test automatically;
Manual intervention Auto-Sensing Mode, manually starts embedded test controller and tests.
The present invention also provides a kind of plate level embedded testing method, comprises the following steps:
Step 1: all of digital circuit test unit, analog circuit test cell formation circuit-under-test plate can test item;
Step 2: the test item of all structures is generated embedded testing data with download uploading unit by Test data generation, is downloaded to embedded test controller;
Step 3: embedded test controller is connected to circuit-under-test plate;
Step 4: start circuit-under-test plate, the testing process administrative unit of embedded test controller starts test process according to different test patterns;
Step 5: after having tested, stores all test results, and indicates circuit-under-test plate whether to there is fault.
Further, can test item, comprise boundary scan testing, IO test, communication bus test, voltage detecting, waveform occur, signal monitoring.
Further, described boundary scan testing, comprises device ID test, interconnecting test, memory test.
Further, described communication bus test, comprises UART test, SCI test, SPI test, I2C test.
Further, embedded testing data comprise testing sequence, test-types, test command, excited data, intended response data.
Can select to set up test item dissimilar separately and test data for different Board Under Tests, but still identical embedded test controller can be adopted, realize embedded testing.
In embedded testing process, controller starts corresponding testing process according to the test pattern arranged.
When adopting power-on self-test pattern, after Board Under Test powers on, embedded test controller starts the testing process set automatically, can all perform all downloads by test item, and the response data analyzing each test item, record the test result of each test item.When all test item test results are all correct, confirm that circuit board does not have fault.When having a test result mistake at least, confirm that circuit board exists fault, then externally indicating circuit plate breaks down.When adopting manual intervention Auto-Sensing Mode, trigger embedded testing by tester.
In whole embedded testing process, the transmission of test stimulus data and the acceptance of response data, and the analyzing and diagnosing of fault all performs in circuit board inside, does not comprise any external test facility in test process.
Beneficial effect of the present invention is as follows:
By designing a kind of plate level embedded test controller and method of testing, contain multiple test resource, by being embedded into circuit board inside, without the need to can test automatically in realizing circuit plate and fault detect by external test facility, and according to different circuit boards, when not changing embedded test controller, reshuffling of test resource can be realized, improve the coverage rate of test, reduce testing cost simultaneously.Adopt embedded testing method, without the need to external test facility and test cable, during test, depart from the restriction of host computer, test can be realized in any occasion, greatly improve the ease for use of test.
Accompanying drawing explanation
Fig. 1 is the composition schematic diagram of the embedded test controller of the embodiment of the present invention;
Fig. 2 is the illustrative view of functional configuration of the circuit-under-test plate of the embodiment of the present invention;
Fig. 3 is the illustrative view of functional configuration that the embodiment of the present invention adopts the circuit-under-test plate of embedded test controller;
Fig. 4 is the method flow diagram of embodiment of the present invention embedded testing.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined object and take and effect, below in conjunction with accompanying drawing and preferred embodiment, the present invention is described in detail as after.
In the present embodiment, circuit-under-test plate comprises boundary scanning device FPGA, DSP that two have jtag interface, and FPGA is connected with connector by impact damper, DSP by UART be connected be connected.Have interconnection between FPGA and DSP, FPGA is connected with a SRAM simultaneously.The measurand that this circuit structure is implemented as embedded test controller provided by the present invention and method of testing.
Enforcement concrete steps are as follows:
Step 1, setting up all of circuit-under-test plate can test item.
In the present embodiment, can comprise by test item on analysis circuit plate: the IO test of board power voltage monitoring, FPGA device ID test, DSP device ID test, the test of FPGA and DSP interconnecting test, SRAM memory, impact damper, the UART test of DSP.
Board power voltage tester, the effective range of setting voltage.In testing, if voltage monitoring exceedes above-mentioned scope, decision circuit plate breaks down.
FPGA device ID test, DSP device ID test, FPGA and DSP interconnecting test, SRAM memory test the jtag interface then utilizing embedded test controller, belong to boundary scan testing.Any one test crash, then same decision circuit plate breaks down.Boundary scan testing data are more, need carry out compressing and optimization process.
The IO test of impact damper utilizes the input and output of the IO of embedded test controller to impact damper to test, if input and output are inconsistent, then same decision circuit plate breaks down.
The UART test of DSP utilizes the UART of embedded test controller to carry out communication test to it, if cannot normal communication, then same decision circuit plate breaks down.
Step 2, above-mentioned test item is generated corresponding embedded testing data.The test data of each test item comprises testing sequence, test-types, test command, excited data, intended response data.
Step 3, by all embedded testing data, be downloaded to embedded test controller.During download, controller by the standby mode of low-power consumption, can enter downloading mode, and all test datas can be kept at controller inside.Only otherwise again download, these test datas can carry out embedded testing to this circuit board always.
Step 4, embedded test controller is connected to circuit-under-test plate.Connected mode according to demand in different ways, as direct welding, or can utilize connector grafting.
Step 5, all testing apparatuss of circuit-under-test plate and outside to be disconnected, start power supply.After powering on, embedded test controller takes power-on self-test pattern, without the need to manual intervention, enters test pattern.In test process, intervene without any external world, circuit board inside can realize whole test and failure diagnostic process.
Step 6, embedded test controller perform supply voltage monitoring.If supply voltage does not meet test request, then controller can point out fault, interrupts follow-up test.
Step 8, embedded test controller perform FPGA device ID test, DSP device ID test, the test of FPGA and DSP interconnecting test, SRAM memory, the IO test of impact damper, the UART test of DSP.Any one test crash, then controller can point out fault.
The result of step 9, all test items of embedded test controller record.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a plate level embedded test controller, is characterized in that, comprising: digital circuit test unit, analog circuit test unit, testing process administrative unit, Test data generation and download uploading unit;
Described digital circuit test unit, realizes digital circuits section test and diagnostic, comprises boundary scan testing, IO test, communication bus test;
Described analog circuit test unit, realizes simulation and Digital Analog Hybrid Circuits partial test and diagnosis, comprises voltage monitoring, waveform occurs, input;
Described testing process administrative unit, for controlling the flow process of the mode of operation of embedded test controller, test pattern and whole test, realizes resource management and the scheduling of whole embedded testing process;
Described Test data generation and download uploading unit, realize numeral, simulation test desired data generate, and be downloaded to embedded test controller, and upload test result.
2. a kind of plate level embedded test controller as claimed in claim 1, is characterized in that described digital circuit test unit comprises 1149.1JTAG interface, I/O interface, UART interface, SCI interface, SPI interface, I2C interface.
3. a kind of plate level embedded test controller as claimed in claim 1 or 2, it is characterized in that, described mode of operation comprises:
Standby mode, controller is in low power consumpting state;
Downloading mode, controller is in the state downloading test data;
Test pattern, controller is in the state performing embedded testing.
4. a kind of plate level embedded test controller as claimed in claim 3, it is characterized in that, described test pattern comprises:
Power-on self-test pattern, after powering on, embedded test controller starts test automatically;
Manual intervention Auto-Sensing Mode, manually starts embedded test controller and tests.
5. a plate level embedded testing method, is characterized in that, comprise the following steps:
Step 1: all of digital circuit test unit, analog circuit test cell formation circuit-under-test plate can test item;
Step 2: the test item of all structures is generated embedded testing data with download uploading unit by Test data generation, is downloaded to embedded test controller;
Step 3: embedded test controller is connected to circuit-under-test plate;
Step 4: start circuit-under-test plate, the testing process administrative unit of embedded test controller starts test process according to different test patterns;
Step 5: after having tested, stores all test results, and indicates circuit-under-test plate whether to there is fault.
6. a kind of plate level embedded testing method as claimed in claim 5, is characterized in that, further, described can test item, comprise boundary scan testing, IO test, communication bus test, voltage detecting, waveform occur, signal monitoring.
7. a kind of plate level embedded testing method as claimed in claim 6, is characterized in that, further, described boundary scan testing, comprises device ID test, interconnecting test, memory test.
8. a kind of plate level embedded testing method as claimed in claim 6, is characterized in that, further, described communication bus test, comprises UART test, SCI test, SPI test, I2C test.
9. a kind of plate level embedded testing method as described in claim 5 or 6 or 7 or 8, it is characterized in that, further, embedded testing data comprise testing sequence, test-types, test command, excited data, intended response data.
10. a kind of plate level embedded testing method as claimed in claim 5, it is characterized in that, when adopting power-on self-test pattern, after Board Under Test powers on, embedded test controller starts the testing process set automatically, can all perform all downloads by test item, and the response data analyzing each test item, record the test result of each test item.When all test item test results are all correct, confirm that circuit board does not have fault.When having a test result mistake at least, confirm that circuit board exists fault, then externally indicating circuit plate breaks down.
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Cited By (10)
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| CN106526462A (en) * | 2016-11-04 | 2017-03-22 | 上海航天测控通信研究所 | Digital circuit system test method |
| CN107918075A (en) * | 2017-11-20 | 2018-04-17 | 中国电子科技集团公司第四十研究所 | A kind of embedded testing cell arrangement and method suitable for electronic equipment |
| CN108241117A (en) * | 2016-12-23 | 2018-07-03 | 台湾福雷电子股份有限公司 | System and method for testing semiconductor devices |
| CN109557458A (en) * | 2018-12-26 | 2019-04-02 | 中国电子科技集团公司第四十研究所 | One kind being suitable for electronic equipment digital-to-analog circuit embedded test system |
| CN109976305A (en) * | 2018-12-28 | 2019-07-05 | 北京航天测控技术有限公司 | A kind of aircraft automatic control system real-time closed-loop test system |
| CN110568339A (en) * | 2019-08-09 | 2019-12-13 | 江苏斯菲尔电气股份有限公司 | Instrument automatic testing system and method based on Internet of things |
| CN111239593A (en) * | 2018-11-29 | 2020-06-05 | 恩智浦有限公司 | Test system with embedded tester |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN113325300A (en) * | 2020-02-28 | 2021-08-31 | 美光科技公司 | Test access port control piece capable of being accessed by controller |
| CN118376864A (en) * | 2024-06-21 | 2024-07-23 | 深圳市曜通科技有限公司 | System and method for diagnosing faults of tubing mechanism based on semiconductor punching equipment |
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| CN111239593A (en) * | 2018-11-29 | 2020-06-05 | 恩智浦有限公司 | Test system with embedded tester |
| CN109557458A (en) * | 2018-12-26 | 2019-04-02 | 中国电子科技集团公司第四十研究所 | One kind being suitable for electronic equipment digital-to-analog circuit embedded test system |
| CN109976305A (en) * | 2018-12-28 | 2019-07-05 | 北京航天测控技术有限公司 | A kind of aircraft automatic control system real-time closed-loop test system |
| CN110568339A (en) * | 2019-08-09 | 2019-12-13 | 江苏斯菲尔电气股份有限公司 | Instrument automatic testing system and method based on Internet of things |
| CN113325300A (en) * | 2020-02-28 | 2021-08-31 | 美光科技公司 | Test access port control piece capable of being accessed by controller |
| CN113325300B (en) * | 2020-02-28 | 2022-06-17 | 美光科技公司 | Test access port control piece capable of being accessed by controller |
| CN111579974A (en) * | 2020-06-09 | 2020-08-25 | 中国电子科技集团公司第十四研究所 | Tested module, embedded system and test method for realizing boundary scan test |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
| CN118376864A (en) * | 2024-06-21 | 2024-07-23 | 深圳市曜通科技有限公司 | System and method for diagnosing faults of tubing mechanism based on semiconductor punching equipment |
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