CN104484248A - Diagnosis method and device for electrifying fault of computer motherboard - Google Patents

Diagnosis method and device for electrifying fault of computer motherboard Download PDF

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Publication number
CN104484248A
CN104484248A CN201410709778.XA CN201410709778A CN104484248A CN 104484248 A CN104484248 A CN 104484248A CN 201410709778 A CN201410709778 A CN 201410709778A CN 104484248 A CN104484248 A CN 104484248A
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power conversion
programmable logic
chip
logic chip
response vector
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CN201410709778.XA
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穆常青
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Inventec Pudong Technology Corp
Inventec Corp
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Inventec Pudong Technology Corp
Inventec Corp
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Priority to CN201410709778.XA priority Critical patent/CN104484248A/en
Publication of CN104484248A publication Critical patent/CN104484248A/en
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Abstract

The invention provides diagnosis method and device for an electrifying fault of a computer motherboard. The method comprises the steps of supplying power to the motherboard and determining whether a programmable logic chip works; if so, outputting at least one enable signal which is sequenced according to a preset time sequence according to the connection condition of the programmable logic chip and a plurality of power conversion chips so as to enable the power conversion chips to work; detecting level switching signals output by the plurality of power conversion chips through the programmable logic chip; determining the work from a circuit which generate the at least one enable signal to circuits between the successful level conversion signals of the corresponding power conversion chips is normal if the level conversion signals are valid, and otherwise, determining that the fault occurs in the circuit section. With the adoption of the diagnosis method for the electrifying fault of the computer motherboard, the difficulty and workload at the repair of the motherboard can be greatly decreased; the diagnosis method is fast and convenient; the fault can be accurately located to the level of some circuit generating the level signal.

Description

The diagnostic method of electric fault and device on computer motherboard
Technical field
The present invention relates to field of computer technology, particularly relate to diagnostic method and the device of electric fault on a kind of computer motherboard.
Background technology
In computer motherboard maintenance field, usually for the mainboard sending into maintenance station, the most worried situation running into mainboard and cannot power on of maintenance personal, that is, after pressing power on button, whole mainboard, without any reaction, causes maintenance personal to have no way of doing it.It is software that such main board failure can be got rid of usually, comprise firmware, the fault caused, because before feeding maintenance station, the problem of technician in the face of starting shooting, first will attempt the firmware etc. of burning Basic Input or Output System (BIOS) again (being called for short BIOS), programmable logic chip, when still cannot deal with problems, just can send into maintenance station.For this mainboard that cannot power on, production line comes the position of quick diagnosis fault appearance in the urgent need to a kind of technological means, improve maintenance efficiency.
Current computer motherboard system electrification control circuit all adopts CPLD or field programmable gate array (CPLD/FPGA) chip usually, and it can control based on CPU, the logic that powers on that customization is complicated.CPLD/FPGA chip due to its pin many, components and parts volume is little, and logical block density is large, probe cannot be utilized to carry out circuit test, generally all carry out circuit test by embedded boundary scan (Boundary Scan) circuit.But CPLD/FPGA only utilizes boundary scan chain to test the linkage function of self usually before dispatching from the factory.In normal operating process, CPLD performs its normal function, just looks like that boundary scan chain does not exist.But under boundary scan test mode, sweep circuit logic is activated, and external data can be sent in CPLD, and uses serial line interface data to be read out from CPLD.Such data can be used for activating the function of device on mainboard, are sent to PCB by signal from device wire, read the input lead of PCB and readout equipment exports.But utilize boundary scan chain to diagnose the technology of electric fault on mainboard also not occur.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides the diagnostic method of electric fault on a kind of computer motherboard, the diagnostic method of electric fault on a kind of computer motherboard, described mainboard comprises programmable logic chip and multiple power conversion chip, and it is characterized in that, the method comprises the following steps:
To described main board power supply, and judge whether described programmable logic chip works;
If described programmable logic chip work, then:
A. export according to the connection of described programmable logic chip and described multiple power conversion chip at least one enable signal arranged with scheduled timing, the described power conversion chip work of the enable correspondence of at least one enable signal described;
B. described programmable logic chip detects the level conversion pass signal that described multiple power conversion chip exports;
If the described level conversion pass signal of the power conversion chip that C. at least one enable signal described is corresponding is effective, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal, otherwise determine that described computer motherboard exists fault in this section;
D. for power conversion chip described in all the other, repeated execution of steps A, B, C, until whole described multiple power conversion chip is enabled at least one times, determine whole abort situation that described computer motherboard powers on thus.
The present invention also provides a kind of diagnostic device of electric fault on computer motherboard, and described mainboard comprises programmable logic chip and multiple power conversion chip, it is characterized in that, comprising:
Power supply judgment means, for: to described main board power supply, and judge whether described programmable logic chip works;
Sequential output unit, if for described programmable logic chip work, then export according to the connection of described programmable logic chip and multiple power conversion chip at least one enable signal arranged with scheduled timing, the described power conversion chip work of the enable correspondence of at least one enable signal described;
Response detection device, detects the level conversion pass signal of described multiple power conversion chip output for described programmable logic chip;
Trouble-shooter, if effective for the described level conversion pass signal of power conversion chip corresponding at least one enable signal described, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal, otherwise determine that described computer motherboard exists fault in this section.
Adopt diagnostic method and the device of electric fault on computer motherboard of the present invention, greatly reduce difficulty and the workload of mainboard maintenance job, fast, conveniently, localization of fault can be as accurate as the rank that a certain level signal produces circuit to diagnostic method.And for the mainboard of same model, only need configure once just can Reusability, improves fault diagnosis efficiency.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the diagnostic method process flow diagram of electric fault on computer motherboard according to an embodiment of the invention;
Fig. 2 is the ultimate principle figure utilizing CPLD controlling calculation mainboard to power on according to an embodiment of the invention;
Fig. 3 is the diagnostic method process flow diagram of electric fault on the computer motherboard according to the preferred embodiment of the invention;
Fig. 4 is the diagnostic system structured flowchart of electric fault on computer motherboard according to an embodiment of the invention;
Fig. 5 is the schematic diagram of a part for the River City mainboard electrifying timing sequence of Romley-EP framework according to an embodiment of the invention;
Fig. 6 is the schematic diagram of the diagnostic device of electric fault on a kind of computer motherboard according to an embodiment of the invention;
Fig. 7 is the schematic diagram of the diagnostic device of electric fault on a kind of computer motherboard according to another embodiment of the invention.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with the element shown in one or more other accompanying drawing or embodiment and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Following " mainboard " has with " computer motherboard " implication be equal to, and " CPLD " and " CPLD chip " and " CPLD device " have equivalents.
Fig. 1 is the diagnostic method process flow diagram of electric fault on computer motherboard according to an embodiment of the invention.Technical scheme of the present invention is operating as core with the CPLD's on mainboard.When diagnosing electric fault on mainboard, first will judge, whether the CPLD on mainboard can work.Thus can be two stages by fault diagnosis workload partition:
Stage one: CPLD does not work
First, in step S101, to main board power supply S101, in step S102, detect CPLD and whether work.If after providing 12V to power to mainboard, the CPLD on mainboard does not work, illustrate that mainboard basis supply line breaks down.Such as, be generally used for the CPLD use 3.3V auxiliary power supply that computer motherboard power up controls, the P3V3_AUX pin namely on CPLD chip should provide the voltage of 3.3V.If the P3V3_AUX pin of CPLD cannot provide this voltage, then CPLD cisco unity malfunction, the diagnosis and repair instruments such as multimeter can only be used manually to investigate fault between the P3V3_AUX pin of motherboard power supply 12V to CPLD conversion line by maintenance personal.By fault diagnosis being divided into two stages, greatly reducing the difficulty of main board diagnostic, reducing fault coverage, accelerate diagnosis process.
Stage two: CPLD can work
After CPLD work on mainboard, the failure diagnostic process that powers on can be completed according to the following steps.Utilize ultimate principle that this CPLD controlling calculation mainboard powers on as shown in Figure 2.CPLD on mainboard and the CPU on mainboard, other component circuitry such as DDR connects, in step S103, CPLD detects other parts from mainboard one by one and is sent to the signal on its pin, as " there is (CPU present) in CPU ", the significant level state of " DDR exists (DDR present) " etc., in step S104, export to the power conversion chip of correspondence the enable signal of level conversion allowing to correspond to certain parts according to the specific electrifying timing sequence of the mainboard of the type, the work of multiple power conversion chip on enable mainboard, thus multiple power conversion chip generates each road level signal that on mainboard, each parts power on and normally work required, complete and power on.After each road level generates, power conversion chip on mainboard has the level conversion success of " level conversion success (Power Good) " signal (appearing on a pin of power conversion chip) instruction correspondence corresponding to each parts such as such as CPU, DDR etc., such as, the CPU_Power_Good pin of corresponding power conversion chip of powering to CPU occurs that effective high level signal shows that power conversion chip outputs to the level conversion success of CPU.In step S105, " level conversion success (Power the Good) " signal on the power conversion chip of corresponding all parts successfully can be read with CPLD, as judging the mark that these parts can correctly power on.If CPLD cannot obtain " level conversion success (Power the Good) " signal of the power conversion chip of certain parts corresponding or acquisition to should " level conversion success (Power Good) " non-effective level of signal of parts, then can judge that this component circuitry does not normally power on, upwards electric fault diagnostic device reports this abort situation.It should be noted that, above-mentioned detection other parts from mainboard are sent to the signal on CPLD pin, enable mainboard corresponds to the work of the power conversion chip of these parts, and read the process of " level conversion successfully " signal of the power conversion chip corresponding with these parts, can be complete for parts, perform for another parts again, until whole parts to be detected complete S106.Usually, this depends on the timing requirements that mainboard powers on.Also first can detect other parts from mainboard one by one and be sent to the signal on CPLD pin, get rid of the parts not existing or break down, the work of power conversion chip corresponding on enable mainboard one by one more also reads corresponding " level conversion success " signal according to sequential, thus diagnosis fault location.
Fig. 3 illustrates the diagnostic method process flow diagram of electric fault on computer motherboard according to the preferred embodiment of the invention.According to this embodiment, except performing the step identical with above embodiment, after judging that CPLD can work, also perform following steps S203: the circuit connection of other parts on the CPLD on mainboard to be measured, power conversion chip and mainboard is analyzed, obtain CPLD and output to the enable control pin list of mainboard power source conversion chip and CPLD to the detection pin list of " level conversion success (Power Good) " signal of all parts on the corresponding mainboard of power conversion chip.Such as, signal (pin) is connected with providing the power conversion chip of Front Side Bus terminal voltage to know that CPLD passes through " CPU_Vtt is enable " by above-mentioned analysis, the conversion of the bus termination voltage in enable power conversion chip, CPLD is connected with providing the power conversion chip of CPU processor core voltage by " CPU_Vccp is enable " signal (pin), the conversion of the CPU processor core voltage in enable power conversion chip; CPLD is connected with providing the power conversion chip of Front Side Bus terminal voltage by " CPU_Vtt_Power_Good " signal (pin), know the level conversion result (" success " or " unsuccessful ") that the power conversion chip of Front Side Bus terminal voltage is provided, CPLD is connected with providing the power conversion chip of CPU processor core voltage by " CPU_Vccp_Power_Good " signal (pin), knows the level conversion result (" success " or " unsuccessful ") providing the power conversion chip of CPU processor core voltage.
According to the sequential chart that mainboard powers on, the time program process that mainboard powers on is analyzed, know the electrifying timing sequence step that CPLD participates in controlling and sequential relationship.Such as, by above-mentioned analysis, know the sequential relationship between " CPU_Vtt the is enable " signal that CPLD sends and " CPU_Vccp is enable " signal that CPLD sends, and enable provide the power conversion chip of Front Side Bus terminal voltage and CPU processor core voltage is provided power conversion chip level conversion after, the sequential relationship of " CPU_Vtt_Power_Good " signal and " CPU_Vccp_Power_Good " signal.
According to the description of Boundary Sweep Description Language (BSDL) file of this CPLD device, know CPLD control command and the corresponding relation between external pin and boundary scan cell (Boundary Scan Cell).
According to the analysis result of above-mentioned steps, generate test vector and the corresponding Expected Response vector of the jtag interface of control CPLD, and after enable power conversion chip, collect the actual real response vector (step S206) generated.Test vector makes CPLD export with the input signal sequence of multiple enable signals of scheduled timing arrangement, Expected Response vector is computer motherboard when powering on successful, the output signal sequence of the level conversion pass signal that multiple power conversion chips that CPLD chip detects under boundary scan test mode export.Corresponding for real response vector sum Expected Response vector is compared (step S207), the power conversion chip of corresponding parts can be diagnosed rapidly whether to be successfully completed level conversion.By performing the test vector of its correspondence for all parts, and its Expected Response vector is contrasted with real response vector, also just can determine, which power conversion chip real response and Expected Response do not meet, thus the concrete parts of accurately locating on mainboard corresponding to electric fault or gauze position.Continue to perform said process (step S208), until determine whole abort situation that mainboard powers on to all the other power conversion chips.
Further, by above-mentioned test vector, test response vector and Expected Response vectorial be converted to have test vector available on the trouble-shooter that powers on of USB interface, real response vector and Expected Response vectorial, test vector can be sent via USB/JTAG interface convertor to mainboard by the USB interface of the trouble-shooter that powers on, collect response vector, by with Expected Response vector comparative diagnoses localizing faults reason.By this vector conversion, various multi-purpose computer and the special instruments such as trouble-shooter that power on conveniently is utilized to carry out fault diagnosis test.
The diagnostic system structured flowchart of electric fault on the computer motherboard that Fig. 4 provides for one embodiment of the invention.The trouble-shooter that powers on is connected with USB/JTAG interface convertor by USB (universal serial bus) (USB) interface, and USB/JTAG interface convertor is connected by the jtag interface of CPLD on it with tested mainboard.
Technique scheme, greatly reduces difficulty and the workload of mainboard maintenance job, and fast, conveniently, localization of fault can be as accurate as the rank that a certain level signal produces circuit to diagnostic method.And for the mainboard of same model, only need configure once just can Reusability, improves fault diagnosis efficiency.
Orientate example as further illustrate concrete grammar step with the River City mainboard of the Intel Company Romley-EP framework fault diagnosis that powers on below.Fig. 5 is a part for this mainboard electrifying timing sequence.
Step one, analysis motherboard circuit schematic diagram, list the enable control pin of CPLD and Power Good detects pin list.Such as, the P1V5_SSB level in Fig. 4, the FM_VCC_MAIN_EN signal exported by CPLD controls enable, and as FM_VCC_MAIN_EN=1, the work of enable power conversion chip, produces P1V5_SSB level.Produce PWRGD_P1V5_SSB signal, input CPLD simultaneously.
Step 2, analysis mainboard electrifying timing sequence process.Analyze known in conjunction with motherboard circuit schematic diagram, in River City mainboard electrifying timing sequence figure, the signal below P1V5_SSB signal is all subject to CPLD to control to produce, and above signal is introduced by outside, does not control by CPLD.The order that recording level signal produces, and maintain the time required for sequential.Such as, need after PWRGD_P1V5_SSB signal being detected to maintain the enable signal (being only citing) that 50ms just can provide next P1V1_SSB.
The BSDL file of step 3, analysis CPLD.Such as, by analyzing the BSDL file of CPLD, show that CPLD boundary scan chain output unit (Boundary Scan Output Cell) sequence number that the FM_VCC_MAIN_EN signal of CPLD on mainboard is corresponding be CPLD boundary scan chain input block (the Boundary Scan Input Cell) sequence number that 100, PWRGD_P1V5_SSB is corresponding is 150.Can determine that test signal occupies the 100th and 150 respectively in test vector like this.
Step 4, generation test vector table.Such as, whether normal for detecting the work of P1V5_SSB level shifting circuit, setting enable signal FM_VCC_MAIN_EN=1, in then corresponding test vector, unit number be 100 bit value be set as 1, and after this group test vector comes into force, expect in the response vector obtained, unit number be 150 bit value expectation value be 1.
Step 5, test execution.According to signal sequence and the time requirement of electrifying timing sequence definition, the trouble-shooter that powers on sends dependence test vector, collects response vector, and compares with Expected Response vector, if the two is consistent, illustrates that test is passed through; Inconsistent, explanation is broken down.Such as, if unit number 150 does not get the bit value " 1 " of expectation, and the bit value obtained is " 0 ", then illustrate that P1V5_SSB level shifting circuit breaks down, now maintenance personal just can go to have checked with the gauze of P1V5_SSB signal correction targetedly.
Fig. 6 illustrates the block diagram of the diagnostic device of electric fault on a kind of computer motherboard according to an embodiment of the invention.This device comprises: power supply judgment means, for main board power supply, and judges whether programmable logic chip works; Sequential output unit, if for programmable logic chip work, export with the connection of multiple power conversion chip at least one enable signal arranged with scheduled timing, the power conversion chip work of the enable correspondence of these enable signals then according to programmable logic chip; Response detection device, detects the level conversion pass signal of multiple power conversion chip output for programmable logic chip; Trouble-shooter, if effective for the level conversion pass signal of power conversion chip corresponding at least one enable signal above-mentioned, the circuit working that the circuit then determining to produce at least one enable signal from programmable logic chip produces level conversion pass signal to the power conversion chip of correspondence is normal, otherwise determines that computer motherboard exists fault in this section.
Fig. 7 illustrates the block diagram of the diagnostic device of electric fault on a kind of computer motherboard according to a preferred embodiment of the invention.Above-mentioned sequential output unit may further include Connecting quantity generating apparatus, electrifying timing sequence parameter generation device, map pins parameter generation device.Connecting quantity generating apparatus, for the annexation according to programmable logic chip and multiple power conversion chip on the mainboard reflected in the circuit theory diagrams of computer motherboard, generates the annexation of mainboard electrification circuit.Electrifying timing sequence parameter generation device, for according to motherboard circuit sequential chart, extracts time sequence information, generates the time sequence parameter of mainboard electrification circuit.Map pins parameter generation device, for according to the external pin of programmable logic chip on mainboard and the corresponding relation of inner scanning logic unit, exports the sequence number of inner scanning logical block corresponding to each external pin.
Above-mentioned response detection device, may further include test vector generation device, Expected Response vector generator and real response vector harvester.Test vector generation device is used for according to the input from above-mentioned Connecting quantity generating apparatus, electrifying timing sequence parameter generation device, map pins parameter generation device, generate test vector, test vector is the input signal sequence comprising the enable signal of at least one power conversion chip of the predetermined electrifying timing sequence arrangement according to mainboard.Expected Response vector generator, for supposing that the multiple power conversion chips on mainboard are all changed successfully, is created on the level conversion consequential signal on the output pin of power conversion chip.Expected Response vector is that supposition performs described test vector, when computer motherboard powers on successful, and the output signal sequence of the level conversion pass signal that multiple power conversion chips that programmable logic chip detects under boundary scan test mode export.Real response vector harvester, for making measurement vector perform on mainboard, thus the programmable logic chip of mainboard generates real response vector, and this device collects real response vector from the programmable logic chip of mainboard.
According to one embodiment of the invention, above-mentioned trouble-shooter also comprises fault diagnosis locating device, this fault diagnosis locating device is used for comparing real response vector sum Expected Response vector, if Expected Response vector sum real response vector is identical, then the circuit working that the circuit determining to produce at least one enable signal from programmable logic chip produces level conversion pass signal to the power conversion chip of correspondence is normal; If Expected Response vector sum real response vector is different, then based on the component of the real response vector different from the respective components of Expected Response vector, determine the job failure position in this section of circuit.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or equivalent replacement is carried out to wherein portion of techniques feature, such as CPLD is replaced to realize each technical scheme above-mentioned with FPGA, above-mentioned diagnostic method is applied to the maintenance etc. of industrial computer mainboard, and these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (9)

1. the diagnostic method of electric fault on computer motherboard, described mainboard comprises programmable logic chip and multiple power conversion chip, and it is characterized in that, the method comprises the following steps:
To described main board power supply, and judge whether described programmable logic chip works;
If described programmable logic chip work, then:
A. export according to the connection of described programmable logic chip and described multiple power conversion chip at least one enable signal arranged with scheduled timing, the described power conversion chip work of the enable correspondence of at least one enable signal described;
B. described programmable logic chip detects the level conversion pass signal that described multiple power conversion chip exports;
If the described level conversion pass signal of the power conversion chip that C. at least one enable signal described is corresponding is effective, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal, otherwise determine that described computer motherboard exists fault in this section;
D. for power conversion chip described in all the other, repeated execution of steps A, B, C, until whole described multiple power conversion chip is enabled at least one times, determine whole abort situation that described computer motherboard powers on thus.
2. the diagnostic method of electric fault on computer motherboard according to claim 1, it is characterized in that, described method comprises further:
Generate the test vector of described programmable logic chip under boundary scan test mode and Expected Response vector, wherein, described test vector is make described programmable logic chip export the input signal sequence comprising the enable signal of at least one power conversion chip arranged with described scheduled timing, described Expected Response vector is for performing described test vector, when described computer motherboard powers on successful, the output signal sequence of the level conversion pass signal that described multiple power conversion chips that described programmable logic chip detects under boundary scan test mode export.
3. the diagnostic method of electric fault on computer motherboard according to claim 2, is characterized in that, described " described programmable logic chip detects the level conversion pass signal that described multiple power conversion chip exports " specifically comprises:
Perform described test vector, the real response vector exported in response to described test vector when obtaining described power conversion chip real work.
4. the diagnostic method of electric fault on computer motherboard according to claim 3, it is characterized in that, described " if the described level conversion pass signal of power conversion chip corresponding at least one enable signal described is effective; the circuit working that the circuit then determining to produce at least one enable signal described from described programmable logic chip produces described level conversion pass signal to the power conversion chip of described correspondence is normal, otherwise determines this section of circuit working fault " specifically comprises:
Real response vector described in more described Expected Response vector sum;
If real response vector is identical described in described Expected Response vector sum, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal;
If real response vector is different described in described Expected Response vector sum, then based on the component of the described real response vector different from the respective components of described Expected Response vector, determine the job failure position in this section of circuit.
5. the diagnostic method of electric fault on computer motherboard according to claim 1, is characterized in that, also comprise:
To described main board power supply, if described programmable logic chip does not work, then determine mainboard basis supply line fault.
6. the diagnostic device of electric fault on computer motherboard, described mainboard comprises programmable logic chip and multiple power conversion chip, it is characterized in that, comprising:
Power supply judgment means, for: to described main board power supply, and judge whether described programmable logic chip works;
Sequential output unit, if for described programmable logic chip work, then export according to the connection of described programmable logic chip and multiple power conversion chip at least one enable signal arranged with scheduled timing, the described power conversion chip work of the enable correspondence of at least one enable signal described;
Response detection device, detects the level conversion pass signal of described multiple power conversion chip output for described programmable logic chip;
Trouble-shooter, if effective for the described level conversion pass signal of power conversion chip corresponding at least one enable signal described, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal, otherwise determine that described computer motherboard exists fault in this section.
7. device according to claim 6, it is characterized in that, described sequential output unit comprises further: Connecting quantity generating apparatus, electrifying timing sequence parameter generation device, map pins parameter generation device, described Connecting quantity generating apparatus, for the annexation according to programmable logic chip and described multiple power conversion chip on the described mainboard reflected in the circuit theory diagrams of described computer motherboard, generates the annexation of mainboard electrification circuit; Described electrifying timing sequence parameter generation device, for the circuit timing diagram according to described mainboard, extracts time sequence information, generates the time sequence parameter of mainboard electrification circuit; Described map pins parameter generation device, for according to the external pin of programmable logic chip on described mainboard and the corresponding relation of inner scanning logic unit, exports the sequence number of inner scanning logical block corresponding to each external pin.
8. device according to claim 7, is characterized in that, described response detection device comprises further: test vector generation device, Expected Response vector generator and real response vector harvester; Described test vector generation device, makes described programmable logic chip export the input signal sequence comprising the enable signal of at least one power conversion chip arranged with described scheduled timing for generating; Described Expected Response vector generator, performs described test vector for supposing, when described computer motherboard powers on successful, is created on the level conversion consequential signal on the output pin of described multiple power conversion chip; Described real response vector harvester, for making described measurement vector perform on described mainboard, thus the programmable logic chip of described mainboard generates real response vector, and this harvester collects real response vector from the programmable logic chip of described mainboard.
9. device according to claim 8, it is characterized in that, described trouble-shooter also comprises fault diagnosis locating device, described fault diagnosis locating device is used for Expected Response vector described in more described real response vector sum, if real response vector is identical described in described Expected Response vector sum, then determine that the circuit working that the power conversion chip from the circuit of described programmable logic chip generation at least one enable signal described to described correspondence produces described level conversion pass signal is normal; If real response vector is different described in described Expected Response vector sum, then based on the component of the described real response vector different from the respective components of described Expected Response vector, determine the job failure position in this section of circuit.
CN201410709778.XA 2014-11-28 2014-11-28 Diagnosis method and device for electrifying fault of computer motherboard Pending CN104484248A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106597062A (en) * 2016-12-30 2017-04-26 上海华岭集成电路技术股份有限公司 Current testing system and method of integrated circuit device in power supply power-on process
CN106774631A (en) * 2016-12-06 2017-05-31 郑州云海信息技术有限公司 A kind of mainboard and a kind of sequential control method of mainboard
CN107395180A (en) * 2017-08-14 2017-11-24 河北新华北集成电路有限公司 The enabled circuit of power down delay
CN107797050A (en) * 2017-10-20 2018-03-13 郑州云海信息技术有限公司 A kind of method of location-server mainboard electrifying timing sequence abnormal state
CN110045268A (en) * 2019-05-07 2019-07-23 广东工业大学 A kind of chip detecting system
CN111308934A (en) * 2020-02-27 2020-06-19 浪潮商用机器有限公司 Power supply time sequence power-on monitoring circuit
CN113204508A (en) * 2021-04-25 2021-08-03 山东英信计算机技术有限公司 Complex programmable logic device scanning method and device
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222255A (en) * 1997-02-10 1998-08-21 Nec Eng Ltd Power supply system for electronic device
CN101526581A (en) * 2008-03-07 2009-09-09 佛山市顺德区顺达电脑厂有限公司 Boundary scanning chip failure detection device and method
CN102419723A (en) * 2011-12-31 2012-04-18 曙光信息产业股份有限公司 Device and method for monitoring mainboard booting
CN102621483A (en) * 2012-03-27 2012-08-01 中国人民解放军国防科学技术大学 Multi-link parallel boundary scanning testing device and method
CN103376340A (en) * 2013-07-04 2013-10-30 曙光信息产业(北京)有限公司 Adapter plate, a multi-platform serial test system and method
CN103838344A (en) * 2012-11-27 2014-06-04 英业达科技有限公司 System and method for mainboard power supply control by boundary scanning
CN103970635A (en) * 2014-04-28 2014-08-06 浪潮电子信息产业股份有限公司 Server hardware fault self-diagnosis method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10222255A (en) * 1997-02-10 1998-08-21 Nec Eng Ltd Power supply system for electronic device
CN101526581A (en) * 2008-03-07 2009-09-09 佛山市顺德区顺达电脑厂有限公司 Boundary scanning chip failure detection device and method
CN102419723A (en) * 2011-12-31 2012-04-18 曙光信息产业股份有限公司 Device and method for monitoring mainboard booting
CN102621483A (en) * 2012-03-27 2012-08-01 中国人民解放军国防科学技术大学 Multi-link parallel boundary scanning testing device and method
CN103838344A (en) * 2012-11-27 2014-06-04 英业达科技有限公司 System and method for mainboard power supply control by boundary scanning
CN103376340A (en) * 2013-07-04 2013-10-30 曙光信息产业(北京)有限公司 Adapter plate, a multi-platform serial test system and method
CN103970635A (en) * 2014-04-28 2014-08-06 浪潮电子信息产业股份有限公司 Server hardware fault self-diagnosis method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106774631A (en) * 2016-12-06 2017-05-31 郑州云海信息技术有限公司 A kind of mainboard and a kind of sequential control method of mainboard
CN106597062A (en) * 2016-12-30 2017-04-26 上海华岭集成电路技术股份有限公司 Current testing system and method of integrated circuit device in power supply power-on process
CN107395180A (en) * 2017-08-14 2017-11-24 河北新华北集成电路有限公司 The enabled circuit of power down delay
CN107395180B (en) * 2017-08-14 2020-07-28 河北新华北集成电路有限公司 Power-down delay enable circuit
CN107797050A (en) * 2017-10-20 2018-03-13 郑州云海信息技术有限公司 A kind of method of location-server mainboard electrifying timing sequence abnormal state
CN107797050B (en) * 2017-10-20 2021-07-02 郑州云海信息技术有限公司 Method for positioning abnormal power-on time sequence state of server mainboard
CN110045268A (en) * 2019-05-07 2019-07-23 广东工业大学 A kind of chip detecting system
CN111308934A (en) * 2020-02-27 2020-06-19 浪潮商用机器有限公司 Power supply time sequence power-on monitoring circuit
CN113204508A (en) * 2021-04-25 2021-08-03 山东英信计算机技术有限公司 Complex programmable logic device scanning method and device
CN113364910A (en) * 2021-06-08 2021-09-07 Tcl通讯(宁波)有限公司 Signal processing method, device, equipment and storage medium

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