CN108241117B - System and method for testing semiconductor devices - Google Patents
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
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Abstract
The present disclosure provides a system for testing a semiconductor device, which includes a data generating apparatus, a data testing apparatus, and a data processing apparatus. The data processing device is configured to transmit a first command to the data testing device and transmit a first response to the data generating device after transmitting the first command. After receiving the first response, the data generating device transmits a first data to the data processing device.
Description
Technical Field
The present disclosure relates to a system for testing semiconductor devices and a method for testing semiconductor devices.
Background
Generally, after a chip (e.g., an integrated circuit chip) is manufactured, an electrical test is performed to determine whether the chip is a good product with normal electrical properties, so as to ensure the quality of the chip during shipment. In the field of semiconductor testing, test time is an important and critical factor affecting yield in automatic testing. In general, productivity is measured as the number of units per hour that can be completed (unit per hour). The test time is affected by three factors: the design of the test method, the optimization degree of the test program and the efficiency of the test system. The performance of the test system is mainly determined by: the execution speed of hardware, the execution efficiency of software, and the communication time between the hardware and the software.
In the conventional chip testing process, after the hardware testing end performs a test, it is necessary to wait for an Application Programming Interface (API) in the computer of the testing machine to generate a next test command, and write the test command into the memory of the machine control unit, so that the hardware testing end can obtain the next test command through the machine control unit. Therefore, when a large number of tests are performed, the time for the hardware testing end to wait for the next test command will result in a decrease in testing efficiency.
In order to reduce the consumption of the communication time between the software and the hardware, an embedded system testing method is developed in the prior art, and in the testing process of the embedded system, all testing program codes are burnt into a hard disk of a hardware testing end in advance, so that after the hardware testing end executes a testing command, the next testing command can be immediately picked up from a memory of the hardware testing end.
However, embedded systems can reduce instruction transmission time, but also have other problems. As more and more functions are embedded in hardware for execution, the modification of the test flow becomes less flexible. Because all program codes are pre-burned into the hard disk of the hardware testing end, when the program codes are abnormal or the testing result is abnormal, the test cannot be directly interrupted and the testing program codes cannot be debugged, which causes inconvenience for research personnel to correct and adjust the testing program codes, and thus, the testing mode of the embedded system is not widely applied. Therefore, a semiconductor test system and method are needed to improve the efficiency of the conventional chip test process and to effectively eliminate the abnormality of the test procedure.
Disclosure of Invention
An embodiment of the present disclosure provides a system for testing a semiconductor device, which includes a data generating apparatus, a data testing apparatus, and a data processing apparatus. The data processing device is configured to transmit a first command to the data testing device and transmit a first response to the data generating device after transmitting the first command. After receiving the first response, the data generating device transmits a first data to the data processing device.
Another embodiment of the present disclosure provides a method for testing a semiconductor device, which includes providing a data generating apparatus, providing a data processing apparatus, and providing a data testing apparatus. The method further comprises: transmitting a first command to the data testing device at a first time by the data processing device, so that the data testing device performs testing according to the first command; and after the first command is transmitted to the data testing device, the data processing device transmits a first response to the data generating device. Wherein the data generating device transmits a first data to the data processing device according to the received first response.
The semiconductor test system and the semiconductor test method described in the present disclosure can improve the efficiency of semiconductor test, reduce the memory usage in the semiconductor test system, and increase the efficiency of eliminating the test procedure abnormality.
Drawings
FIG. 1 is a schematic diagram of a semiconductor test system.
FIG. 2 is a schematic diagram of a semiconductor test system according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention.
FIG. 4 is a schematic diagram of a semiconductor test system according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention.
FIG. 6 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention.
FIG. 7 is a schematic diagram of a semiconductor test system according to an embodiment of the invention.
FIG. 8 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention.
FIG. 9 is a schematic diagram of a semiconductor test system according to an embodiment of the invention.
FIG. 10 is a schematic diagram illustrating a semiconductor testing method according to an embodiment of the invention.
Detailed Description
The present disclosure provides many different embodiments, or examples, for implementing different features of the invention. For simplicity of illustration, examples of specific components and arrangements are also described in the present disclosure. It should be noted that these specific examples are provided for illustrative purposes only and are not intended to be limiting in any way.
As used herein, the terms "first," "second," "third," and "fourth" are used to describe various elements, components, steps, signals or commands, and these elements, components, steps, signals or commands should not be limited by these terms. These terms are only used to distinguish one element, component, step, signal, or command from another element, component, step, signal, or command. Unless the context clearly dictates otherwise, when words such as "first", "second", "third", and "fourth" are used herein, no sequence or order is intended.
FIG. 1 is a schematic diagram of a semiconductor test system. As shown in fig. 1, the semiconductor test system includes a test computer 100, a machine control unit 120, a hardware tester 140, and a load board 180. The test computer 100, the machine control unit 120, the hardware tester 140, and the load board 180 are electrically connected to each other for transmitting signals and commands, and the device under test 160 is mounted on the load board 180. Generally, the dut may be an integrated circuit chip.
The test computer 100 includes a processor 102 and a memory 104. The test computer 100 generates test data by the API installed thereon and stores the test data in the memory 104. The machine control unit 120 includes a processor 122, a memory 124, and an input/output port 126. The machine control unit 120 receives the test data from the test computer 100 and processes the test data to generate the test command. The test commands may be stored in memory 124 and sent to hardware tester 140 via I/O ports 126.
Hardware tester 140 may include a plurality of modules for testing semiconductor devices. For example, hardware tester 140 may include a dc module 142, a Precision Measurement Unit (PMU) 144, a digital module 146, and a relay board 148. Based on the content of the generated test command, the machine control unit 120 transmits the test command to the corresponding modules of the hardware tester 140 via the input/output port 126.
The dc module 142 provides a measurement of the dc parameter of the semiconductor device. For example, the dc module 142 may provide a test current to the semiconductor device to be tested and measure a corresponding voltage of the semiconductor device. Alternatively, the dc module 142 may provide a test voltage to the semiconductor device to be tested and measure the corresponding current of the semiconductor device.
The precision measurement unit 144 also provides for measurement of the dc parameter of the semiconductor device. However, the precision measurement unit 144 may provide a higher precision (accuracy) measurement than the dc module 142. Generally, the precision measurement unit 144 is designed for testing with small currents and small voltages. Because the voltage and current provided by the device are small, it is necessary to have better precision.
In the testing of the integrated circuit chip, in addition to the electrical measurement for the direct current, the testing needs to be performed for different functions of the integrated circuit chip. The digital module 146 can perform a signal transceiving test for a plurality of digital functions of the integrated circuit. For example, the digital module 146 may perform transceiving tests for the I2C Bus (Inter-Integrated Circuit Bus), TTL (Transistor-Transistor logic), SPI (serial Peripheral interface) and Tx/Rx at baseband frequency of the Integrated Circuit. In order to perform the above test, the digital module 146 can set the voltage level and the current value, and also can set the signal switching frequency, the voltage rising/falling edge, the synchronization of the receiving/transmitting time, and the like. Generally, the digital module 146 may provide a voltage range that is small, approximately close to the precision measurement unit 144. In one embodiment, the digital module 146 may also provide all the functions of the precision metrology unit 144.
Relay board 148 may provide a path switching function for hardware tester 140. In semiconductor device testing, the number of available test channels of hardware tester 140 is often insufficient due to cost constraints or excessive pin count of the device under test (dut). In this case, pins must share the same test channel, and the switching can be controlled through the relay board 148.
FIG. 2 is a schematic diagram of a semiconductor test system 200 according to an embodiment of the invention. As shown in FIG. 2, the semiconductor test system 200 includes a data generating device 220, a data processing device 240 and a data testing device 260. The data generating device 220, the data processing device 240 and the data testing device 260 are electrically connected to each other for transmitting signals and commands. The device under test 280 is mounted on the data testing device 260. The data processing device 240 includes a processor 242 and a memory 244.
The data generating device 220 may generate a test data, and the data processing device 240 receives the test data from the data generating device 220, processes the test data and generates a test command. The processing of test data and the generation of test commands are performed by processor 242. The data testing device 260 can test the device under test 280 according to the test command from the data processing device 240. In an embodiment of the present invention, after the data processing apparatus 240 transmits the test command to the data testing apparatus 260, the data processing apparatus 240 generates a response to the data generating apparatus 220. After receiving the response, the data generating device 220 generates the next test data and transmits the next test data to the data processing device 240.
The data processing device 240 processes the next test data and generates the next test command. When the data testing device 260 completes the test according to the current test command, a response is generated to the data processing device 240, and the data processing device 240 can send the next test command to the data testing device 260.
It should be noted that in this embodiment, the data generating device 220 does not need to wait for the data testing device 260 to complete the current test command to generate the test data for the next test. The data processing device 240 completes the processing of the next test data and generates the next test command before the data testing device 260 completes the current test command. In this manner, multiple tests performed by the data testing apparatus 260 can be continuously performed without interruption, thereby greatly reducing the latency time consumed by the communication between the software and the hardware in the semiconductor test system.
In addition, the data processing device 240 can determine whether the test command is executed correctly according to the response returned by the data testing device 260. If the data processing device 240 determines that the response returned by the data testing device 260 is abnormal, a corresponding warning message can be generated, so that the research and development personnel can correct and adjust the testing program code in real time, thereby increasing the efficiency of exception elimination.
FIG. 3 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention. As shown in fig. 3, the semiconductor testing method of the present embodiment includes the following steps:
step 302: the data processing device 240 processes the first data from the data generating device 220, generates a first command and transmits the first command to the data testing device 260;
step 304: the data testing device 260 tests the device under test 280 according to the first command;
step 306: the data processing means 240 transmits the first response to the data generating means 220;
step 308: after receiving the first response from the data processing device 240, the data generating device 220 generates second data for the next test and transmits the second data to the data processing device 240;
step 310: the data processing device 240 processes the second data and generates a second command for the next test;
step 312: when the data testing device 260 completes the testing of the first command, the data processing device 240 transmits a second command to the data testing device 260; and
step 314: the data testing device 260 tests the device under test 280 according to the second command.
It should be noted that step 304 and step 306 are not necessarily distinguished from each other in time, that is, step 304 and step 306 may be started simultaneously.
FIG. 4 is a schematic diagram of a semiconductor test system 400 according to an embodiment of the invention. As shown in FIG. 4, the semiconductor test system 400 includes a data generating device 420, a data processing device 440, and a data testing device 460. The data generating device 420, the data processing device 440 and the data testing device 460 are electrically connected to each other for transmitting signals and commands. The device under test 480 is mounted on the data testing device 460. The data generating device 420 includes a memory 422. The data processing device 440 includes a processor 442 and a memory 444.
In this embodiment, the data generating device 420 generates a piece of test data according to the first response transmitted by the data processing device 440. Each time the data generating device 420 generates a piece of test data, the test data is not directly transmitted to the data processing device 440, but the test data is first stored in the memory 422. The data generating device 420 transmits the test data to the data processing device 440 after receiving a second response transmitted by the data processing device 440.
After the data processing device 440 transmits a test command to the data testing device 460, a first response is sent to the data generating device. And the data processing device 440 may transmit a second response according to different circumstances. Generally, when the data processing device 440 completes processing the current test data and can process the next test data, a second response is sent to the data generating device 420.
In this embodiment, the data generating device 420 generates the test data according to the first response transmitted by the data processing device 440, which can prevent the data generating device 420 from continuously generating the test data and thus reduce the memory usage of the data generating device 420. In addition, the data processing device 440 can determine whether the test command is executed correctly according to the response returned by the data testing device 460. The transmission of the first response and the second response and the determination of the exception are performed by processor 442. If the data processing device 440 determines that the response returned by the data testing device 460 is abnormal, a corresponding warning message can be generated, so that the research and development personnel can modify and adjust the testing program code in real time, thereby increasing the efficiency of exception elimination.
FIG. 5 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention. The semiconductor test method illustrated in fig. 5 corresponds to a portion of the operational steps of the semiconductor test system 400 illustrated in fig. 4. As shown in fig. 5, the semiconductor testing method of the present embodiment includes the following steps:
step 502: the data processing means 440 transmits the first response to the data generating means 420;
step 504: in response to the first response, the data generating device 420 generates first data and stores the first data in the memory 422;
step 506: the data processing means 440 transmits a second response to the data generating means 420; and
step 508: in response to the second response, the data generating device 420 transmits the first data stored in the memory 422 to the data processing device 440.
Step 510: the data processing device 440 stores the first data in the memory 444.
FIG. 6 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention. The semiconductor test method shown in fig. 6 may correspond to a portion of the operational steps of the semiconductor test system shown in fig. 2, 4, 7 and 9. For convenience of explanation, the semiconductor test system 200 shown in FIG. 2 will be described as an example.
As shown in fig. 6, the semiconductor test method of the present embodiment includes the following steps:
step 602: the data processing means 240 processes the second data from the data generating means 220 and generates a second command;
step 604: the data testing device 260 completes the test according to the first command;
step 606: the data testing device 260 transmits a third response to the data processing device 240;
step 608: the data processing device 240 transmits a second command to the data testing device 260; and
step 610: the data testing device 260 performs a test according to the second command.
It should be noted that in this embodiment, the step 602 is necessarily earlier in time than the step 606, so that the data processing apparatus 240 has completed processing the second data and generated the second command before the data testing apparatus 260 completes the test according to the first command. In this manner, multiple tests performed by the data testing apparatus 260 can be continuously performed without interruption, thereby greatly reducing the latency time consumed by the communication between the software and the hardware in the semiconductor test system.
FIG. 7 is a schematic diagram of a semiconductor test system 700 according to an embodiment of the invention. As shown in FIG. 7, the semiconductor test system 700 includes a data generating apparatus 720, a data processing apparatus 740, and a data testing apparatus 760. The data generating device 720, the data processing device 740, and the data testing device 760 are electrically connected to each other for transmitting signals and commands. Device under test 780 is mounted on data testing apparatus 760. The data processing device 740 includes a processor 742, a first memory 744, and a second memory 746.
In this embodiment, the data generating device 720 transmits the encoded test data to the data processing device 740. The encoded test data is received by the data processing apparatus 740 and stored in the first memory 744. After the encoded test data is stored in the first memory 744, the data processing apparatus 740 returns a response to the data generating apparatus 720, so that the data generating apparatus 720 generates the next test data. The processor 742 of the data processing apparatus 740 decodes the test data stored in the first memory 744 and processes the decoded test data to generate the test command. The generated test command is stored in the second memory 746. At this time, the data processing apparatus 740 transmits a response to the data generating apparatus 720, so that the data generating apparatus 720 transmits the next encoded test data to the data processing apparatus 740 and stores the next encoded test data in the first memory 744.
Each time a test is completed, the data testing apparatus 760 sends a response to the data processing apparatus 740, and then the data processing apparatus 740 sends the test command stored in the second memory 746 to the data testing apparatus 760. After the test command in the second memory 746 is transmitted to the data testing apparatus 760, the data processing apparatus 740 decodes the test data stored in the first memory 744 and processes the test command to generate a next test command. The next test command is generated and stored in the second memory 746.
FIG. 8 is a schematic diagram of a semiconductor testing method according to an embodiment of the invention. The semiconductor test method shown in fig. 8 corresponds to a portion of the operational steps of the semiconductor test system 700 shown in fig. 7. As shown in fig. 8, the semiconductor test method of the present embodiment includes the following steps:
step 802: the data generating device 720 transmits the encoded first data to the data processing device 740, and the data processing device 740 stores the encoded first data in the first memory 744;
step 804: the data processing device 740 transmits the first response to the data generating device 720, so that the data generating device 720 generates the encoded second data;
step 806: the data processing device 740 decodes the encoded first data, processes to generate a first command and stores the first command in the second memory 746;
step 808: the data processing apparatus 740 transmits a second response to the data generating apparatus 720, so that the data generating apparatus 720 transmits the encoded second data to the data processing apparatus 740 and stores the encoded second data in the first memory 744; and
step 810: the data testing apparatus 760 transmits a third response to the data processing apparatus 740, causing the data processing apparatus 740 to transmit the first command to the data testing apparatus 760.
It should be noted that, in this embodiment, the data generating apparatus 720 transmits the data of the next test to the data processing apparatus 740 and stores the data in the first memory before the data testing apparatus 760 completes the current test command. And the data processing apparatus 740 decodes and generates the command for the next test and stores the command in the second memory before the data testing apparatus 760 completes the current test command. In this manner, each time data testing apparatus 760 completes a test, a response is returned to data processing apparatus 740 to obtain a command for the next test. Therefore, a plurality of tests can be continuously performed without interruption, and the waiting time for communication between software and hardware in the semiconductor test system is greatly reduced.
FIG. 9 is a schematic diagram of a semiconductor test system according to an embodiment of the invention. As shown in fig. 9, the semiconductor test system 900 includes a data generating device 920, a data processing device 940 and a data testing device 960. The data generating device 920, the data processing device 940 and the data testing device 960 are electrically connected to each other for transmitting signals and commands. Device under test 980 is mounted on data test device 960. Data processing device 940 includes a processor 942, memory 944, and registers 946.
In this embodiment, the data generation device 920 transmits the encoded test data to the data processing device 940. The encoded test data is received by the data processing device 940 and stored in the memory 944. When data processing apparatus 940 receives a response from data test apparatus 960, informing that the current test is completed, processor 942 of data processing apparatus 940 decodes the test data stored in memory 944, and synchronously transmits the decoded test data to data test apparatus 960 via register 946. That is, the data processing apparatus 940 does not need to store the next test command generated in the memory. The memory usage of the data processing apparatus 940 can be saved.
FIG. 10 is a schematic diagram illustrating a semiconductor testing method according to an embodiment of the invention. The semiconductor test method shown in fig. 10 corresponds to a portion of the operational steps of the semiconductor test system 900 shown in fig. 9. As shown in fig. 10, the semiconductor test method of the present embodiment includes the following steps:
step 1002: the data generating device 920 transmits the encoded test data to the data processing device 940;
step 1004: data processing device 940 stores the encoded test data in memory 944;
step 1006: the data testing device 960 sends a response to the data processing device 940;
step 1008: the data processing device 940 decodes the encoded test data in the memory 944 to generate a test command, and synchronously transmits the test command to the data testing device 960 via the register 946.
While the invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not intended to limit the invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, method, or component to the objective, spirit and scope of the present invention. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that such operations may be combined, sub-divided, or re-sequenced to form equivalent methods without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present invention.
Claims (17)
1. A system for testing semiconductor components, comprising:
a data generating device;
a data testing device; and
a data processing device having a processor and a first memory, the data processing device configured to transmit a first command to the data testing device and to transmit a first response to the data generating device after transmitting the first command,
wherein after receiving the first response, the data generation device transmits first data to the data processing device, and
the processor of the data processing apparatus is configured to process the first data and complete processing of the first data and generate a second command before the data testing apparatus completes the first command.
2. The system of claim 1, wherein the processor is configured to process the first data and generate a second command, and store the second command in the first memory.
3. The system of claim 2, wherein the data generating means is responsive to the first response to generate the first data.
4. The system of claim 2, wherein the data generating means transmits the first data to the data processing means in response to a second response from the data processing means.
5. The system of claim 4, wherein the data processing device is configured to respond to a third response to transfer the second command stored in the first memory to the data testing device.
6. The system of claim 5, wherein the transmission of the first data is completed before the data processing device receives the third response.
7. The system of claim 2, wherein
The data processing apparatus further comprises a buffer; and is
The data processing device is configured to synchronously transmit the second command to the data testing device via the buffer while processing the first data in response to a third response.
8. The system of claim 2, wherein the data processing device further comprises:
a second memory therein
The data processing device is configured to dump the second command from the first memory into the second memory prior to transmitting the first response to the data generating device.
9. The system of claim 8, wherein the data processing device is configured to transmit the second command stored in the second memory to the data testing device in response to a third response.
10. The system of claim 2, wherein the first data is encoded and the processor is configured to code the first data and generate the second command.
11. A method for testing a semiconductor component, comprising:
providing a data generating device;
providing a data processing device having a processor and a first memory; and
providing a data testing device;
transmitting a first command to the data testing device by the data processing device at a first time, so that the data testing device performs testing according to the first command;
after the first command is transmitted to the data testing device, the data processing device transmits a first response to the data generating device;
the data generating device transmits first data to the data processing device according to the received first response;
the processor of the data processing apparatus is configured to process the first data and complete processing of the first data and generate a second command before the data testing apparatus completes the first command.
12. The method of claim 11, further comprising processing, by the processor of the data processing device, the first data and generating a second command, and storing the second command in the first memory.
13. The method of claim 11, wherein
The data generating means generates the first data in response to the first response and transmits the first data to the data processing means in response to a second response from the data processing means.
14. The method of claim 12, wherein the data processing device responds to a third response by synchronously transmitting the second command to the data testing device while processing the first data.
15. The method of claim 14, wherein the transmitting of the first data is completed before the data processing device receives the third response.
16. The method of claim 12, wherein the data processing device further comprises a second memory, and the method further comprises:
unloading, by the data processing apparatus, the second command from the first memory into the second memory before transmitting the first response to the data generating apparatus.
17. The method of claim 12, further comprising coding, by the processor, the first data and generating the second command.
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| TW105143111A TWI637177B (en) | 2016-12-23 | 2016-12-23 | System and method for testing semiconductor elements |
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| CN108241117A (en) | 2018-07-03 |
| TWI637177B (en) | 2018-10-01 |
| TW201823743A (en) | 2018-07-01 |
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