CN111856246A - High-speed synchronous trigger bus circuit and synchronous trigger method - Google Patents
High-speed synchronous trigger bus circuit and synchronous trigger method Download PDFInfo
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- CN111856246A CN111856246A CN202010668804.4A CN202010668804A CN111856246A CN 111856246 A CN111856246 A CN 111856246A CN 202010668804 A CN202010668804 A CN 202010668804A CN 111856246 A CN111856246 A CN 111856246A
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000012360 testing method Methods 0.000 claims abstract description 46
- 238000004891 communication Methods 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000001960 triggered effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- Tests Of Electronic Circuits (AREA)
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Abstract
The invention relates to a high-speed synchronous trigger bus circuit, and belongs to the technical field of chip testing devices. The method is characterized in that: the device is divided into a central control board part and a test board part, wherein each part comprises an FPGA chip, a circuit interface and a high-speed communication interface; the FPGA chip is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip of the central control board part is connected with a communication bus of an upper computer through a circuit interface, and the FPGA chip of the test board part is connected with a functional unit of a chip test device through the circuit interface; the synchronous signal output end of the central control board part and the synchronous signal receiving end of the test board card part, the synchronous signal output end of the test board card part and the synchronous signal receiving end of the central control board part are connected with each other through a high-speed communication cable. The invention provides high-speed synchronous trigger signal input and output by utilizing the LVDS port signal characteristic of the FPGA chip and avoids interference.
Description
Technical Field
The invention relates to a high-speed synchronous trigger bus circuit and a synchronous trigger method, and belongs to the technical field of chip testing devices.
Background
Automatic Test Equipment (ATE) is commonly used in the field of chip manufacturing to test logic on manufactured chips to ensure that the performance of the chips meets design requirements. Different test items are usually designed in the automatic test machine, different test board cards are designed, and the central control board and each test board card are synchronously triggered through a bus. The synchronous trigger communication internal communication is divided into parallel communication and serial communication, wherein the parallel communication generally transmits each bit of a data byte by using a plurality of data lines at the same time, but needs a plurality of data lines and control lines, occupies more resources for the whole system, and has limited operation speed due to the difficulty of data bit alignment; the serial communication is usually a mode of splitting data into one bit and one bit, and the data is transmitted on a single data line, so that the advantages of saving system resources and extremely high single-line transmission speed (which can reach 5 Gbps). However, because the boards share the ground, the low-frequency disturbance between the boards at two ends of communication affects each other, and the requirement of high-speed synchronous triggering in chip testing is not met.
Disclosure of Invention
The invention provides a high-speed synchronous trigger bus circuit, which solves the problem of safe and high-speed communication between a central control board and each test board card.
The technical scheme is as follows:
a high speed synchronous trigger bus circuit, comprising: the device is divided into a central control board part and a test board part, wherein each part comprises an FPGA chip, a circuit interface and a high-speed communication interface; the FPGA chip is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip of the central control board part is connected with a communication bus of an upper computer through a circuit interface, and the FPGA chip of the test board part is connected with a functional unit of a chip test device through the circuit interface; the synchronous signal output end of the central control board part and the synchronous signal receiving end of the test board card part, the synchronous signal output end of the test board card part and the synchronous signal receiving end of the central control board part are connected with each other through a high-speed communication cable.
Furthermore, the central control board part and the test board card part are not grounded in common, and low-frequency disturbance among the board cards is effectively isolated.
Furthermore, the synchronous signal output end and the synchronous signal receiving end of the FPGA chip are LVDS signal ports
Further, the high-speed communication cable is a differential coaxial cable.
Furthermore, a capacitor is respectively connected in front of the two-port synchronous signal receiving end of the FPGA chip for direct current isolation.
Further, the capacitance of the capacitor is 10 nF.
A synchronous trigger method for transmission by using the circuit is characterized in that an FPGA chip at a sending end decomposes a synchronous trigger signal into first-class data and second-class data, encodes the first-class data into third-class data, encodes the second-class data into fourth-class data and then sends the fourth-class data, and an FPGA chip at a receiving end decodes the received third-class data and fourth-class data into the first-class data and the second-class data and synthesizes the first-class data and the second-class data into the synchronous trigger signal.
The first type data and the second type data are opposite to each other, the third type data and the fourth type data are formed by alternately combining the first type data and the second type data, and the first type data and the second type data are opposite to each other, if the first type data is 0, the second type data is 1, the third type data is 01, the fourth type data is 10, or the first type data is 0, the second type data is 1, the third type data is 010, and the fourth type data is 101; the difference between the synchronous trigger signals of the sending end and the receiving end is a fixed clock period, the difference between the clock period and the synchronous trigger signals is equal to the length difference between the third type of data and the first type of data or between the fourth type of data and the second type of data, the difference between 01 and 0 or 10 and 1 is a period, and the difference between 010 and 0 or 101 and 1 is two periods.
Has the advantages that:
1) the invention provides high-speed synchronous trigger signal input and output by utilizing the LVDS (low voltage differential signal) signal characteristic of a high-speed port of an FPGA (field programmable gate array) chip, does not need an additional driving circuit and reduces the cost.
2) The common high-speed differential coaxial cable is matched with the capacitance detection blocking of the receiving end to realize uploading and distribution of internal synchronous trigger signals, direct current isolation is carried out among the board cards, the board cards with different voltages are supported to be connected with each other, and common ground interference is avoided.
3) The system is triggered in extremely low delay (fixed delay with one clock) by matching with a special synchronous triggering method, so that the testing efficiency of the whole ATE testing system is improved. Meanwhile, when a plurality of instrument board cards work cooperatively, the instrument board cards all work under the same delay condition, so that strict synchronous triggering of a large system can be ensured, and the problem that the traditional triggering bus can cause asynchronous triggering among the board cards is avoided.
Drawings
FIG. 1 is a schematic diagram of a high-speed synchronous trigger bus circuit according to the present invention;
FIG. 2 is a schematic view of an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an encoding method of the synchronization triggering method;
FIG. 4 is a schematic diagram illustrating another encoding method of the synchronization triggering method;
Wherein: the test board is characterized in that 1 is a central control board part, 2 is a test board part, 3 is an FPGA chip, 4 is a high-speed communication cable, 5 is a capacitor, 6 is an upper computer, and 7 is a functional unit.
Detailed Description
The invention is described in detail below with reference to the following figures and specific examples:
as shown in fig. 1, a high-speed synchronous trigger bus circuit is divided into a central control board part 1 and a test board card part 2, each of which comprises an FPGA chip 3, a circuit interface and a high-speed communication interface; the FPGA chip 3 is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip 3 of the central control board part 1 is connected with a communication bus of an upper computer 6 through a circuit interface, and the FPGA chip 3 of the test board card part 2 is connected with a functional unit 7 of a chip test device through a circuit interface; the synchronizing signal output terminal of the central control board part 1 and the synchronizing signal receiving terminal of the test board part 2, the synchronizing signal output terminal of the test board part 2 and the synchronizing signal receiving terminal of the central control board part 1 are connected to each other through a high-speed communication cable 4.
The central control board part 1 and the test board card part 2 are not grounded in common, and low-frequency disturbance among the board cards is effectively isolated.
The synchronous signal output end and the synchronous signal receiving end of the FPGA chip 3 are LVDS signal ports.
The high-speed communication cable 4 is a differential coaxial cable.
And a capacitor 5 is respectively connected in front of the two-port synchronous signal receiving end of the FPGA chip 3 for direct current isolation.
The capacitance 5 has a capacity of 10 nF.
A synchronous trigger method for transmission by using the circuit is characterized in that an FPGA chip at a sending end decomposes a synchronous trigger signal into first-class data and second-class data, encodes the first-class data into third-class data, encodes the second-class data into fourth-class data and then sends the fourth-class data, and an FPGA chip at a receiving end decodes the received third-class data and fourth-class data into the first-class data and the second-class data and synthesizes the first-class data and the second-class data into the synchronous trigger signal.
The first kind of data and the second kind of data are mutually reverse, the third kind of data and the fourth kind of data are formed by combining the first kind of data and the second kind of data at intervals, the first kind of data and the second kind of data are mutually reverse, the synchronous trigger signals of the sending end and the receiving end have a fixed clock period difference, and the clock period difference is equal to the length difference value of the third kind of data and the first kind of data or the fourth kind of data and the second kind of data.
Example 1 as shown in fig. 3: the FPGA chip of the circuit of the central control board part connected with the PC upper computer decomposes an internal synchronous trigger signal transmitted by an ATE testing device through a bus into a first type data 0 and a second type data 1, encodes the data 0 into the data 01, encodes the data 1 into the data 10, transmits the data to the test board part through a high-speed communication cable, correspondingly decodes the signal by the FPGA chip of the test board part, restores the data 01 into the data 0, restores the data 10 into the data 1, simultaneously transmits the signal fed back by the test board part to the central control board through the high-speed communication cable after the signal is encoded by the FPGA chip, correspondingly decodes the signal after the FPGA chip of the central control board part receives the signal, and the signal of a transmitting end and the signal of a receiving end have a clock interval. And the FPGA chip carries out direct current isolation on the received signals through a capacitor of 10nF at a synchronous signal receiving end, so that voltage floating between the central control board and the test board card is ensured, and transmitted signal data are not interfered.
Example 2 as shown in fig. 4: the FPGA chip of the central control board part circuit connected with the PC upper computer decomposes an internal synchronous trigger signal transmitted by an ATE testing device through a bus into a first type data 0 and a second type data 1, encodes the data 0 into a data 10, encodes the data 1 into a data 01, transmits the data to the test board part through a high-speed communication cable, correspondingly decodes the signal by the FPGA chip of the test board part, reduces the data 10 into the data 0, reduces the data 01 into the data 1, simultaneously transmits the signal fed back by the test board part to the central control board through the high-speed communication cable after the signal is encoded by the FPGA chip, correspondingly decodes the signal after the FPGA chip of the central control board part receives the signal, the signals of a transmitting end and a receiving end have the same difference of one clock interval, and the rest parts are the same as the embodiment 1.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and scope of the present invention are intended to be covered thereby.
Claims (8)
1. A high speed synchronous trigger bus circuit, comprising: the device is divided into a central control board part (1) and a test board card part (2), wherein each part comprises an FPGA chip (3), a circuit interface and a high-speed communication interface; the FPGA chip (3) is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip (3) of the central control board part (1) is connected with a communication bus of an upper computer (6) through a circuit interface, and the FPGA chip (3) of the test board part (2) is connected with a functional unit (7) of a chip test device through a circuit interface; the synchronous signal output end of the central control board part (1) and the synchronous signal receiving end of the test board card part (2), the synchronous signal output end of the test board card part (2) and the synchronous signal receiving end of the central control board part (1) are connected with each other through a high-speed communication cable (4).
2. A high speed synchronous trigger bus circuit as in claim 1 wherein: the central control board part (1) and the test board card part (2) are not grounded in common, and low-frequency disturbance among the board cards is effectively isolated.
3. A high speed synchronous trigger bus circuit as in claim 1 wherein: and the synchronous signal output end and the synchronous signal receiving end of the FPGA chip (3) are LVDS signal ports.
4. A high speed synchronous trigger bus circuit as in claim 1 wherein: the high-speed communication cable (4) is a differential coaxial cable.
5. A high speed synchronous trigger bus circuit as in claim 1 wherein: and a capacitor (5) is respectively connected in front of the two port synchronous signal receiving ends of the FPGA chip (3) for direct current isolation.
6. The high speed synchronous trigger bus circuit of claim 5 wherein: the capacitance of the capacitor (5) is 10 nF.
7. A synchronization triggering method, characterized by: the high-speed synchronous trigger bus circuit according to any one of claims 1 to 6 is used for transmission, the FPGA chip at the transmitting end decomposes the synchronous trigger signal into first data and second data, encodes the first data into third data, encodes the second data into fourth data, and transmits the encoded data, and the FPGA chip at the receiving end decodes the received third data and fourth data into the first data and second data and synthesizes the decoded data into the synchronous trigger signal.
8. The synchronous triggering method as recited in claim 7, wherein: the first type data and the second type data are mutually reverse, the third type data and the fourth type data are formed by combining the first type data and the second type data at intervals, the first type data and the second type data are mutually reverse, the synchronous trigger signals of the sending end and the receiving end have a fixed clock period difference, and the clock period difference is equal to the length difference value of the third type data and the first type data or the fourth type data and the second type data.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010668804.4A CN111856246B (en) | 2020-07-13 | High-speed synchronous trigger bus circuit and synchronous trigger method | |
| TW110117199A TWI777557B (en) | 2020-07-13 | 2021-05-13 | Synchronous triggering method based on high speed synchronous triggering bus circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010668804.4A CN111856246B (en) | 2020-07-13 | High-speed synchronous trigger bus circuit and synchronous trigger method |
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| Publication Number | Publication Date |
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| CN111856246A true CN111856246A (en) | 2020-10-30 |
| CN111856246B CN111856246B (en) | 2024-07-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115941398A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH10336042A (en) * | 1996-09-06 | 1998-12-18 | Toshiba Corp | Variable length encoding and decoding device and recording medium recording data or program used by this device |
| KR20000040531A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | High-speed physical chip system for ieee 1394 serial bus interface and method transmitting and receiving data of the same |
| CN107480390A (en) * | 2017-08-23 | 2017-12-15 | 京东方科技集团股份有限公司 | Compensation method, device and the computer equipment of signal delay |
| CN212379519U (en) * | 2020-07-13 | 2021-01-19 | 胜达克半导体科技(上海)有限公司 | High-speed synchronous trigger bus circuit |
| US20220124655A1 (en) * | 2018-12-28 | 2022-04-21 | Zte Corporation | Time synchronization method and electronic device |
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10336042A (en) * | 1996-09-06 | 1998-12-18 | Toshiba Corp | Variable length encoding and decoding device and recording medium recording data or program used by this device |
| KR20000040531A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | High-speed physical chip system for ieee 1394 serial bus interface and method transmitting and receiving data of the same |
| CN107480390A (en) * | 2017-08-23 | 2017-12-15 | 京东方科技集团股份有限公司 | Compensation method, device and the computer equipment of signal delay |
| US20220124655A1 (en) * | 2018-12-28 | 2022-04-21 | Zte Corporation | Time synchronization method and electronic device |
| CN212379519U (en) * | 2020-07-13 | 2021-01-19 | 胜达克半导体科技(上海)有限公司 | High-speed synchronous trigger bus circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115941398A (en) * | 2022-12-01 | 2023-04-07 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
| CN115941398B (en) * | 2022-12-01 | 2024-03-05 | 电子科技大学 | Cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
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| Publication number | Publication date |
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| TW202203024A (en) | 2022-01-16 |
| TWI777557B (en) | 2022-09-11 |
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Address after: 201799 1st floor, building 1, 1130 qinghewan Road, Qingpu District, Shanghai Applicant after: Sundak Semiconductor Technology (Shanghai) Co.,Ltd. Address before: 201799 1st floor, building 1, 1130 qinghewan Road, Qingpu District, Shanghai Applicant before: Sundec semiconductor technology (Shanghai) Co.,Ltd. |
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