CN201689889U

CN201689889U - Cascade circuit for physical layer of Ethernet

Info

Publication number: CN201689889U
Application number: CN 201020138857
Authority: CN
Inventors: 刘德银; 江惠秋; 黄洪波; 郑宏涛
Original assignee: Shenzhen Gongjin Electronics Co Ltd
Priority date: 2010-03-22
Filing date: 2010-03-22
Publication date: 2010-12-29
Anticipated expiration: 2020-03-22

Abstract

A cascade circuit for physical layer of Ethernet settles the technical problems of complicate structure, high cost and large design space in the cascade circuit of physical layer. The adopted technical solution is characterized in that: the cascade circuit structure comprises two or more than two physical layer chips and a signal conversion unit provided between the two physical layer chips; the signal conversion unit is composed of a group of capacitors connected between the transmission-end pins and receiving-end pins of two physical layer chips; and the physical layer chips crossly transmit and receive the differential pair signal by means of the capacitors. The cascade circuit for physical layer of Ethernet is advantageous in that: through redesigning the signal conversion unit in the cascade circuit, the design space and the production cost are reduced while a purpose of signal conversion is obtained.

Description

A kind of ethernet physical layer cascade circuit

Technical field

The utility model relates in the Fast Ethernet physical layer to the docking technique field of physical layer, refer in particular to a kind of simple for structure,, the shared PCB of design is little, cost is very low, meet the ethernet physical layer cascade circuit of industry standard standard.

Background technology

PHY refers to physical layer, and physical layer is the ground floor of OSI, though it is in the bottom, is the basis of whole open system.Physical layer provides transmission medium and interconnect equipment for the data communication between the equipment, for transfer of data provides reliable environment.Medium and interconnect equipment: the medium of physical layer comprise aerial line, balanced cable, optical fiber, wireless channel etc.The interconnect equipment of communication usefulness refers to the interconnect equipment between DTE and DCE.DTE is data terminal equipment both, claims again all to be included physical equipment as computer, terminal etc.DCE then is data communications equipment or circuit connection device, as modulator-demodulator etc.Transfer of data is normally passed through DTE-DCE, passes through the path of DCE-DTE again.Interconnect equipment refers to device that DTE, DCE are coupled together, as various plugs, socket.Various thick, thin coaxial cable, T type among the LAN connects, plug, and receiver, transmitter, repeater etc. all belong to the medium and the connector of physical layer.The major function of physical layer: 1) for data terminal equipment provides the path that transmits data, data path can be a physical medium, also can be that a plurality of physical mediums are formed by connecting.Once complete transfer of data comprises the activation physical connection, transmits data, stops physical connection.The so-called activation exactly no matter there are how many physical mediums to participate in, all will couple together, forms a path between two data terminal equipments of communication.2) transmission data, physical layer will form the entity that is fit to the transfer of data needs, is data delivery service.The one, guarantee that data can correctly pass through thereon, the 2nd, provide enough bandwidth (bandwidth is meant bit (BIT) number that can pass through in each second), to reduce congested on the channel.The mode of transmission data can satisfy point-to-point, a bit to multiple spot, serial or parallel, half-or full-duplex, synchronously or the needs of asynchronous transmission.

At present, generally be divided into two kinds in the cascade system of 100M Switch chip or physical chip: the one, standard MII interface mode, the wiring of this kind connected mode is cumbersome, and two sides all have 18 lines to dock by the standard connected mode; Another kind directly couples together the physical layer architecture of two chips with digital signal transformer and relevant configuration device by the standard connection.The preceding relatively a kind of method of second method more still needs extra magnetic device to build, and cost and space are relatively large.In current competition excited electrons communication products, miniaturization day by day has higher requirement to design space and cost.Physical layer is often to use to the Cascading Methods of physical layer in the design of communication products, but these present two kinds of modes all are difficult to reach the requirement that cascade system is simple and reliable, cost is little, the design space is little, has brought inconvenience for the work of this area.

Summary of the invention

The utility model is for solving the technical problem that physical layer cascade circuit structure is numerous and diverse, cost is high, the design space is big, designed a kind of ethernet physical layer cascade circuit, by the signal conversion unit in the cascade circuit is redesigned, when reaching the conversion of signals purpose, also reduce the design space, saved production cost.

The utility model for realizing the technical scheme that goal of the invention adopts is, a kind of ethernet physical layer cascade circuit, comprise two or more physical chips in the cascade circuit structure and be arranged on two signal conversion units between the physical chip, above-mentioned signal conversion unit is made up of one group of electric capacity that is connected between two physical chips transmissions and the receiving terminal pin, and physical chip sends and receive differential pair signal by capacitive cross.

The beneficial effects of the utility model are: by to the redesign of the signal conversion unit in the cascade circuit, when reaching the conversion of signals purpose, also reduced the design space, saved production cost.

Description of drawings

Fig. 1 is a physical layer cascade circuit diagram in the prior art.

Fig. 2 is a circuit structure diagram of the present utility model.

In the accompanying drawing, U1, U2 represents physical layer chip, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10 represent electric capacity, and R1, R2, R3, R4, R5, R6, R7, R8 represent resistance, T1 representation signal transformer.

Embodiment

Referring to accompanying drawing, a kind of ethernet physical layer cascade circuit, comprise two or more physical chips in the cascade circuit structure and be arranged on two signal conversion units between the physical chip, above-mentioned signal conversion unit is made up of one group of capacitor C 5, C6, C7, C8 that is connected between two physical chip U1, U2 transmissions and the receiving terminal pin, and physical chip U1, U2 send and receive differential pair signal by capacitor C 5, C6, C7, C8 intersection.

Also comprise in the above-mentioned cascade circuit structure and each input/output port of physical chip U1, U2 impedance matching circuit supporting, that form by resistance R 1, R2, R3, R4, R5, R6, R7, R8 and capacitor C 1, C2, C3, C4.

Also be reserved with the reference bias voltage port supporting in the structure of above-mentioned impedance matching circuit with physical chip U1, U2.

Above-mentioned capacitor C 5, C6, C7, C8 are ceramic condensers.

The utility model in the specific implementation, only need by some simple resistances, hold combination, be connected to form the capacitance-resistance direct-coupled circuit,, just can realize directly that physical layer is to the simple and reliable cascade of physical layer by connecting correct physical chip U1, the reference bias voltage of U2.

The utility model circuit structure is divided into three fractions: the impedance matching circuit of physical chip U1 input/output port; Capacitor C 5, C6, C7, C8 are every straight coupling circuit; The impedance matching circuit of physical chip U2 input/output port.

Referring to Fig. 2, the transmission differential pair U1-TX+/U1-TX-of physical chip U1 and reception differential pair U1-RX+/U1-RX-are cross connected to the reception differential pair U2-RX+/U2-RX-of physical chip U2 by capacitor C 5, C6, C7, C8 and send on the differential pair U2-TX+/U2-TX-; 100ohm impedance on the PHY of U1, U2 end coupling respectively then, at the resistance that on every differential signal line, draws 49.9ohm respectively, on draw electric capacity to connect the reference bias voltage value of own PHY respectively; Connect a 0.1uH ceramic condenser on the reference bias voltage value last drawing then.

A specific embodiment of the present utility model, it is the exchange chip of 88E6060 that physical chip U1 adopts model, the reference bias voltage port of physical chip U1 inserts the reference voltage of 2.5V; It is the exchange chip of RTL8306 that physical chip U2 adopts model, the reference bias voltage port of physical chip U2 inserts the reference voltage of 1.8V, the resistance of resistance R 1, R2, R3, R4, R5, R6, R7, R8 is 49.9ohm, encapsulate 0402 of optional standard, the capacitance of capacitor C 5, C6, C7, C8 is 0.1uF, and withstand voltage is 25V, the type selecting ceramic condenser, encapsulate 0402 of optional standard, it is the ceramic condenser of 0.01～1uF that capacitor C 1, C2, C3, C4 can select capacitance.

Referring to Fig. 1 and Fig. 2, with respect to prior art, capacitor C 5 in the utility model, C6, C7, C8 have substituted original signal transformer T1 and supporting peripheral circuit thereof, effectively reduced the PCB space, saved production cost, and the utility model is easy to realize the 100M cascade of two physical chip U1, U2, and is simple for structure.

Claims

1. ethernet physical layer cascade circuit, comprise two or more physical chips in the cascade circuit structure and be arranged on two signal conversion units between the physical chip, it is characterized in that: described signal conversion unit is made up of one group of electric capacity (C5, C6, C7, C8) that is connected between two physical chips (U1, U2) transmission and the receiving terminal pin, and physical chip (U1, U2) sends and receive differential pair signal by electric capacity (C5, C6, C7, C8) intersection.

2. a kind of ethernet physical layer cascade circuit according to claim 1 is characterized in that: also comprise in the described cascade circuit structure and each input/output port of physical chip (U1, U2) impedance matching circuit supporting, that be made up of resistance (R1, R2, R3, R4, R5, R6, R7, R8) and electric capacity (C1, C2, C3, C4).

3. a kind of ethernet physical layer cascade circuit according to claim 1 is characterized in that: the also default and supporting reference bias voltage port of physical chip (U1, U2) in the structure of described impedance matching circuit.