本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。 在本文中所使用的“第一”、“第二”、“第三”以及“第四”語詞係描述各種元件、組件、步驟、信號或命令，這些元件、組件、步驟、信號以或命令應不受限於這些語詞。這些語詞僅用於分別一元件、組件、步驟、信號或命令與另一元件、組件、步驟、信號或命令。除非內文中清楚指明，否則當於本文中使用例如“第一”、“第二”、“第三”以及“第四”語詞時，並非意指序列或順序。 圖1繪示一半導體測試系統之示意圖。如圖1所示，半導體測試系統包含測試電腦100、機台控制單元120、硬體測試機140及負載板180。測試電腦100、機台控制單元120、硬體測試機140及負載板180彼此間具有可以傳輸信號及指令的電連接，待測裝置160則安裝於負載板180上。一般言之，待測裝置可為一積體電路晶片。 測試電腦100包含處理器102及記憶體104。測試電腦100藉由安裝於其上的API產生測試資料並儲存於記憶體104中。機台控制單元120包含處理器122、記憶體124以及輸入/輸出埠126。機台控制單元120可接收來自測試電腦100之測試資料，並將測試資料處理後產生測試命令。測試命令可儲存於記憶體124中，並經由輸入/輸出埠126送至硬體測試機140。 硬體測試機140可包含多個用於測試半導體元件之模組。舉例言之，硬體測試機140可包含直流電模組142、精確量測單元（Precision Measurement Unit，PMU）144、數位模組146以及中繼板148。根據所產生測試命令的內容，機台控制單元120經由輸入/輸出埠126將測試命令分別傳送至硬體測試機140相應之模組。 直流電模組142提供半導體元件直流參數的量測。舉例言之，直流電模組142可以提供測試電流至待測試之半導體元件，並量測半導體元件之相應電壓。或者，直流電模組142可以提供測試電壓至待測試之半導體元件並量測半導體元件之相應電流。 精確量測單元144亦提供半導體元件直流參數的量測。然而，相較於直流電模組142，精確量測單元144可以提供更高精準度（accuracy）的量測。一般而言，精確量測單元144係針對小電流及小電壓的測試。因為其所提供之電壓及電流較小，故必須具有更佳的精準度。 在積體電路晶片的測試中，除了上述針對直流電的電性量測外，亦需針對積體電路晶片的不同功能進行測試。數位模組146可針對積體電路之多種數位功能進行信號的收發測試。舉例言之，數位模組146可針對積體電路之數位控制I2C匯流排（Inter-Integrated Circuit Bus）、TTL（Transistor-transistor logic）、SPI（Serial Peripheral Interface）以及基頻的Tx/Rx進行信號收發測試。為了能進行上述測試，數位模組146除了能設定電壓準位及電流值以外，還能設定信號切換頻率、電壓上升/下降邊緣、接收/發送時間之同步等。一般而言，數位模組146可以提供之電壓範圍較小，大約與精確量測單元144接近。在一實施例中，數位模組146亦可提供精確量測單元144之所有功能。 中繼版148可提供硬體測試機140路徑切換功能。在半導體元件測試中，常因成本限制或者待測裝置的針腳（pin）數過多，使得硬體測試機140可用的測試頻道數目不足。在此情況下必須有針腳共用相同的測試頻道，便可透過中繼板148進行控制切換。 圖2繪示本發明一實施例之半導體測試系統200的示意圖。如圖2所示，半導體測試系統200包含資料產生裝置220、資料處理裝置240及資料測試裝置260。資料產生裝置220、資料處理裝置240及資料測試裝置260彼此間具有可以傳輸信號及指令的電連接。待測裝置280安裝於資料測試裝置260上。資料處理裝置240包含處理器242及記憶體244。 資料產生裝置220可產生一測試資料，資料處理裝置240從資料產生裝置220接收了測試資料後，會將測試資料處理並產生一測試命令。測試資料的處理以及測試命令的產生由處理器242執行。資料測試裝置260可根據來自資料處理裝置240之測試命令對待測裝置280進行測試。在本發明之一實施例中，在資料處理裝置240將測試命令傳送至資料測試裝置260後，資料處理裝置240隨即產生一回應至資料產生裝置220。資料產生裝置220在收到回應後便產生下一筆測試資料並傳送至資料處理裝置240。 資料處理裝置240將接收之下一筆測試資料進行處理並產生下一筆測試命令。當資料測試裝置260根據當前的測試命令完成測試後，會產生一回應給資料處理裝置240，此時資料處理裝置240便可將下一筆測試命令發送給資料測試裝置260。 需注意的是，在此實施例中，資料產生裝置220並不需要等待資料測試裝置260完成當前的測試命令，便可產生用於下一筆測試之測試資料。資料處理裝置240在資料測試裝置260完成當前的測試命令之前，便已完成下一測試資料之處理並已產生下一筆測試命令。依此方式，在資料測試裝置260進行的多個測試便可不中斷地持續進行，大幅減少半導體測試系統中軟硬體之間溝通所耗費的等待時間。 此外，資料處理裝置240可根據資料測試裝置260所回傳之回應來判斷測試命令是否正確地執行。若資料處理裝置240判斷資料測試裝置260所回傳之回應產生異常，可產生相應警告訊息，使研發人員能即時修正及調整測試程式碼，如此可增加異常排除的效率。 圖3繪示本發明一實施例之半導體測試方法的示意圖。如圖3所示，本實施例之半導體測試方法包括下列步驟： 步驟302：資料處理裝置240處理來自資料產生裝置220之第一資料，產生第一命令並將第一命令傳送至資料測試裝置260； 步驟304：資料測試裝置260根據第一命令對待測裝置280進行測試； 步驟306：資料處理裝置240傳送第一回應至資料產生裝置220； 步驟308：在接收了來自資料處理裝置240之第一回應後，資料產生裝置220產生用於下一筆測試之第二資料，並將第二資料傳送至資料處理裝置240； 步驟310：資料處理裝置240處理第二資料並產生用於下一筆測試之第二命令； 步驟312：當資料測試裝置260完成了第一命令的測試後，資料處理裝置240將第二命令傳送至資料測試裝置260；以及 步驟314：資料測試裝置260根據第二命令對待測裝置280進行測試。 需注意的是，步驟304與步驟306並不必然存在時間上先後的區別，也就是說，步驟304與步驟306可以同時開始進行。 圖4繪示本發明一實施例之半導體測試系統400的示意圖。如圖4所示，半導體測試系統400包含資料產生裝置420、資料處理裝置440及資料測試裝置460。資料產生裝置420、資料處理裝置440及資料測試裝置460彼此間具有可以傳輸信號及指令的電連接。待測裝置480安裝於資料測試裝置460上。資料產生裝置420包含記憶體422。資料處理裝置440包含處理器442及記憶體444。 在此實施例中，資料產生裝置420根據資料處理裝置440傳送之第一回應而產生一筆測試資料。每當資料產生裝置420產生一筆測試資料後，並不直接將測試資料傳送至資料處理裝置440，而是先將測試資料存入記憶體422中。在收到資料處理裝置440傳送之一第二回應後，資料產生裝置420才將測試資料傳送至資料處理裝置440。 當資料處理裝置440將一筆測試命令傳送至資料測試裝置460後，便發送第一回應至資料產生裝置。而資料處理裝置440可根據不同情況傳送第二回應。一般言之，當資料處理裝置440完成了當前測試資料的處理，而可以處理下一筆測試資料時，將傳送第二回應至資料產生裝置420。 在此實施例中，資料產生裝置420根據資料處理裝置440傳送之第一回應而產生測試資料，可避免資料產生裝置420持續不斷產生測試資料，並因此降低了資料產生裝置420之記憶體使用量。此外，資料處理裝置440可根據資料測試裝置460所回傳之回應來判斷測試命令是否正確地執行。第一回應及第二回應的傳送以及異常的判斷由處理器442執行。若資料處理裝置440判斷資料測試裝置460所回傳之回應產生異常，可產生相應警告訊息，使研發人員能即時修正及調整測試程式碼，如此可增加異常排除的效率。 圖5繪示本發明一實施例之半導體測試方法的示意圖。圖5中所示之半導體測試方法對應於圖4中所示之半導體測試系統400之一部分操作步驟。如圖5所示，本實施例之半導體測試方法包括下列步驟： 步驟502：資料處理裝置440傳送第一回應至資料產生裝置420； 步驟504：回應於第一回應，資料產生裝置420產生第一資料並將第一資料儲存於記憶體422中； 步驟506：資料處理裝置440傳送第二回應至資料產生裝置420；以及 步驟508：回應於第二回應，資料產生裝置420將儲存於記憶體422中的第一資料傳送至資料處理裝置440。 步驟510：資料處理裝置440將第一資料儲存於記憶體444中。 圖6繪示本發明一實施例之半導體測試方法的示意圖。圖6中所示之半導體測試方法可對應於圖2、圖4、圖7及圖9中所示之半導體測試系統之一部分操作步驟。為了說明的方便，現以圖2中所示之半導體測試系統200為例進行說明。 如圖6所示，本實施例之半導體測試方法包括下列步驟： 步驟602：資料處理裝置240處理來自資料產生裝置220的第二資料並產生第二命令； 步驟604：資料測試裝置260完成根據第一命令之測試； 步驟606：資料測試裝置260傳送第三回應至資料處理裝置 240； 步驟608：資料處理裝置240傳送第二命令至資料測試裝置260；以及 步驟610：資料測試裝置260進行根據第二命令之測試。 需注意的是，在此實施例中，步驟602於時間上必定早於步驟606，如此一來，在資料測試裝置260完成根據第一命令的測試之前，資料處理裝置240便已完成第二資料之處理並已產生第二命令。依此方式，在資料測試裝置260進行的多個測試便可不中斷地持續進行，大幅減少半導體測試系統中軟硬體之間溝通所耗費的等待時間。 圖7繪示本發明一實施例之半導體測試系統700的示意圖。如圖7所示，半導體測試系統700包含資料產生裝置720、資料處理裝置740及資料測試裝置760。資料產生裝置720、資料處理裝置740及資料測試裝置760彼此間具有可以傳輸信號及指令的電連接。待測裝置780安裝於資料測試裝置760上。資料處理裝置740包含處理器742、第一記憶體744以及第二記憶體746。 在此實施例中，資料產生裝置720將經過編碼之測試資料傳送至資料處理裝置740。資料處理裝置740接收了經編碼之測試資料後，先將其儲存於第一記憶體744中。在經編碼之測試資料儲存至第一記憶體744之後，資料處理裝置740會回傳一回應至資料產生裝置720，使資料產生裝置720產生下一筆測試資料。資料處理裝置740之處理器742會將儲存於第一記憶體744中的測試資料進行解碼，並處理產生測試命令。產生之測試命令會儲存至第二記憶體746中。此時資料處理裝置740會傳送一回應至資料產生裝置720，使資料產生裝置720將下一筆經編碼之測試資料傳送到資料處理裝置740並儲存於第一記憶體744中。 每當完成一筆測試，資料測試裝置760會傳送一回應至資料處理裝置740，隨後資料處理裝置740便將儲存在第二記憶體746中的測試命令傳送至資料測試裝置760。在第二記憶體746中的測試命令傳送至資料測試裝置760之後，資料處理裝置740將儲存於第一記憶體744中的測試資料進行解碼，並處理產生下一筆測試命令。產生之下一筆測試命令會儲存至第二記憶體746中。 圖8繪示本發明一實施例之半導體測試方法的示意圖。圖8中所示之半導體測試方法對應於圖7中所示之半導體測試系統700之一部分操作步驟。如圖8所示，本實施例之半導體測試方法包括下列步驟： 步驟802：資料產生裝置720將經過編碼之第一資料傳送至資料處理裝置740，資料處理裝置740將經編碼之第一資料儲存於第一記憶體744； 步驟804：資料處理裝置740傳送第一回應至資料產生裝置720，使資料產生裝置720產生經編碼之第二資料； 步驟806：資料處理裝置740解碼經編碼之第一資料，處理產生第一命令並將第一命令儲存於第二記憶體746； 步驟808：資料處理裝置740傳送第二回應至資料產生裝置720，使資料產生裝置720將經編碼之第二資料傳送到資料處理裝置740並儲存於第一記憶體744中；以及 步驟810：資料測試裝置760傳送第三回應至資料處理裝置740，使資料處理裝置740將第一命令傳送至資料測試裝置760。 需注意的是，在此實施例中，資料產生裝置720在資料測試裝置760完成當前的測試命令之前，便已將下一筆測試之資料傳送至資料處理裝置740並儲存於第一記憶體中。且資料處理裝置740在資料測試裝置760完成當前的測試命令之前，便已解碼並產生下一筆測試之命令且儲存於第二記憶體中。依此方式，每當資料測試裝置760完成一筆測試，回傳一回應至資料處理裝置740後便可立即獲得下一筆測試的命令。因此，進行的多個測試便可不中斷地持續進行，大幅減少半導體測試系統中軟硬體之間溝通所耗費的等待時間。 圖9繪示本發明一實施例之半導體測試系統的示意圖。如圖9所示，半導體測試系統900包含資料產生裝置920、資料處理裝置940及資料測試裝置960。資料產生裝置920、資料處理裝置940及資料測試裝置960彼此間具有可以傳輸信號及指令的電連接。待測裝置980安裝於資料測試裝置960上。資料處理裝置940包含處理器942、記憶體944以及暫存器946。 在此實施例中，資料產生裝置920將經過編碼之測試資料傳送至資料處理裝置940。資料處理裝置940接收了經編碼之測試資料後，先將其儲存於記憶體944中。當資料處理裝置940接收到資料測試裝置960之一回應，告知已完成當前測試後，資料處理裝置940之處理器942將儲存於記憶體944中的測試資料進行解碼，並同時經由暫存器946同步傳送至資料測試裝置960。亦即，資料處理裝置940不需將產生之下一筆測試命令儲存於記憶體中。可以節省資料處理裝置940的記憶體使用量。 圖10繪示本發明一實施例之半導體測試方法的示意圖。圖10中所示之半導體測試方法對應於圖9中所示之半導體測試系統900之一部分操作步驟。如圖10所示，本實施例之半導體測試方法包括下列步驟： 步驟1002：資料產生裝置920將經過編碼之測試資料傳送至資料處理裝置940； 步驟1004：資料處理裝置940將經編碼之測試資料儲存於記憶體944； 步驟1006：資料測試裝置960傳送一回應至資料處理裝置940 ； 步驟1008：資料處理裝置940將記憶體944中經編碼之測試資料解碼產生測試命令，並經由暫存器946同步傳送至資料測試裝置 960。 儘管已參考本發明之特定實施例描述並說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者應理解，在不脫離如由所附申請專利範圍界定的本發明之真實精神及範疇的情況下，可作出各種改變且可用等效物取代。應將本說明書及圖式視為說明性而非限制性的。可作出修改，以使特定情形、方法或元件適應於本發明之目標、精神及範疇。所有該等修改均意欲處於此處隨附之申請專利範圍之範疇內。儘管已參看按特定次序執行之特定操作描述本文中所揭示之方法，但應理解，在不脫離本發明之教示的情況下，可組合、再分或重新定序此等操作以形成等效方法。因此，除非本文中具體指示，否則操作之次序及分組並非對本發明之限制。This disclosure provides several different implementation methods or embodiments that can be used to implement different features of the present invention. To simplify the description, this disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for demonstration purposes only and not for any limitation. The terms "first", "second", "third", and "fourth" as used herein describe various elements, components, steps, signals, or commands, and these elements, components, steps, signals, or commands Should not be limited to these words. These terms are only used to distinguish one element, component, step, signal or command from another element, component, step, signal or command. Unless the context clearly indicates otherwise, the terms "first," "second," "third," and "fourth" when used herein do not imply a sequence or order. FIG. 1 is a schematic diagram of a semiconductor test system. As shown in FIG. 1, the semiconductor test system includes a test computer 100, a machine control unit 120, a hardware test machine 140, and a load board 180. The test computer 100, the machine control unit 120, the hardware test machine 140, and the load board 180 have electrical connections that can transmit signals and instructions to each other. The device under test 160 is mounted on the load board 180. Generally speaking, the device under test can be an integrated circuit chip. The test computer 100 includes a processor 102 and a memory 104. The test computer 100 generates test data by using an API installed on the test computer 100 and stores the test data in the memory 104. The machine control unit 120 includes a processor 122, a memory 124 and an input / output port 126. The machine control unit 120 can receive the test data from the test computer 100 and process the test data to generate a test command. The test command can be stored in the memory 124 and sent to the hardware testing machine 140 through the input / output port 126. The hardware testing machine 140 may include a plurality of modules for testing semiconductor components. For example, the hardware testing machine 140 may include a DC power module 142, a Precision Measurement Unit (PMU) 144, a digital module 146, and a relay board 148. According to the content of the generated test command, the machine control unit 120 transmits the test command to the corresponding module of the hardware test machine 140 through the input / output port 126 respectively. The DC power module 142 provides a measurement of a DC parameter of a semiconductor element. For example, the DC power module 142 can provide a test current to the semiconductor device to be tested, and measure the corresponding voltage of the semiconductor device. Alternatively, the DC power module 142 may provide a test voltage to the semiconductor device to be tested and measure a corresponding current of the semiconductor device. The precise measurement unit 144 also provides measurement of DC parameters of semiconductor components. However, compared to the DC power module 142, the accurate measurement unit 144 can provide a higher accuracy measurement. Generally speaking, the accurate measurement unit 144 is a test for small current and small voltage. Because it provides less voltage and current, it must have better accuracy. In the test of integrated circuit chips, in addition to the above-mentioned electrical measurement for direct current, different functions of the integrated circuit chip need to be tested. The digital module 146 can perform signal transmission and reception tests for various digital functions of the integrated circuit. For example, the digital module 146 can signal the digital control I2C bus (Inter-Integrated Circuit Bus), TTL (Transistor-transistor logic), SPI (Serial Peripheral Interface), and Tx / Rx of the fundamental frequency for the integrated circuit. Send and receive tests. In order to perform the above tests, in addition to being able to set the voltage level and current value, the digital module 146 can also set the signal switching frequency, voltage rising / falling edges, and synchronization of receiving / transmitting time. Generally speaking, the voltage range that the digital module 146 can provide is relatively small, which is approximately close to the accurate measurement unit 144. In one embodiment, the digital module 146 can also provide all the functions of the accurate measurement unit 144. The relay version 148 can provide the path switching function of the hardware testing machine 140. In semiconductor device testing, the number of test channels available to the hardware tester 140 is often insufficient due to cost constraints or too many pins of the device under test. In this case, the pins must share the same test channel, and control switching can be performed through the relay board 148. FIG. 2 is a schematic diagram of a semiconductor test system 200 according to an embodiment of the present invention. As shown in FIG. 2, the semiconductor test system 200 includes a data generating device 220, a data processing device 240, and a data testing device 260. The data generating device 220, the data processing device 240, and the data testing device 260 have electrical connections with each other that can transmit signals and instructions. The device under test 280 is mounted on the data testing device 260. The data processing device 240 includes a processor 242 and a memory 244. The data generating device 220 can generate a test data. After receiving the test data from the data generating device 220, the data processing device 240 processes the test data and generates a test command. Processing of test data and generation of test commands are performed by the processor 242. The data testing device 260 may test the device under test 280 according to a test command from the data processing device 240. In one embodiment of the present invention, after the data processing device 240 transmits the test command to the data testing device 260, the data processing device 240 then generates a response to the data generating device 220. After receiving the response, the data generating device 220 generates the next test data and sends it to the data processing device 240. The data processing device 240 will receive the next test data for processing and generate the next test command. After the data testing device 260 completes the test according to the current test command, a response is generated to the data processing device 240. At this time, the data processing device 240 can send the next test command to the data testing device 260. It should be noted that, in this embodiment, the data generating device 220 does not need to wait for the data testing device 260 to complete the current test command, and can generate test data for the next test. The data processing device 240 has completed the processing of the next test data and generated the next test command before the data test device 260 completes the current test command. In this way, multiple tests performed in the data testing device 260 can be continuously performed without interruption, which greatly reduces the waiting time required for communication between software and hardware in the semiconductor test system. In addition, the data processing device 240 can determine whether the test command is executed correctly according to the response returned by the data testing device 260. If the data processing device 240 judges that the response returned by the data testing device 260 is abnormal, a corresponding warning message can be generated, so that the R & D personnel can correct and adjust the test code in real time, which can increase the efficiency of exception elimination. FIG. 3 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. As shown in FIG. 3, the semiconductor testing method of this embodiment includes the following steps: Step 302: The data processing device 240 processes the first data from the data generating device 220, generates a first command, and transmits the first command to the data testing device 260. Step 304: the data testing device 260 tests the device under test 280 according to the first command; step 306: the data processing device 240 sends a first response to the data generating device 220; step 308: upon receiving the first from the data processing device 240 After the response, the data generating device 220 generates second data for the next test, and transmits the second data to the data processing device 240; Step 310: The data processing device 240 processes the second data and generates the first data for the next test. Two commands; step 312: after the data test device 260 completes the test of the first command, the data processing device 240 transmits the second command to the data test device 260; and step 314: the data test device 260 performs the test on the device under test according to the second command 280 for testing. It should be noted that step 304 and step 306 are not necessarily different in time sequence, that is, step 304 and step 306 can be started at the same time. FIG. 4 is a schematic diagram of a semiconductor test system 400 according to an embodiment of the present invention. As shown in FIG. 4, the semiconductor test system 400 includes a data generating device 420, a data processing device 440, and a data testing device 460. The data generating device 420, the data processing device 440, and the data testing device 460 have electrical connections with each other that can transmit signals and instructions. The device under test 480 is mounted on the data testing device 460. The data generating device 420 includes a memory 422. The data processing device 440 includes a processor 442 and a memory 444. In this embodiment, the data generating device 420 generates a piece of test data according to the first response sent by the data processing device 440. Whenever the data generating device 420 generates a piece of test data, the test data is not directly transmitted to the data processing device 440, but the test data is first stored in the memory 422. After receiving a second response transmitted by the data processing device 440, the data generating device 420 transmits the test data to the data processing device 440. After the data processing device 440 sends a test command to the data testing device 460, it sends a first response to the data generating device. The data processing device 440 may transmit a second response according to different situations. Generally speaking, when the data processing device 440 finishes processing the current test data and can process the next test data, it will send a second response to the data generating device 420. In this embodiment, the data generating device 420 generates test data according to the first response sent by the data processing device 440, which can prevent the data generating device 420 from continuously generating test data, and therefore reduces the memory usage of the data generating device 420. . In addition, the data processing device 440 may determine whether the test command is executed correctly according to the response returned by the data testing device 460. The transmission of the first response and the second response and the determination of the abnormality are executed by the processor 442. If the data processing device 440 determines that the response returned by the data testing device 460 is abnormal, a corresponding warning message can be generated, so that the R & D personnel can correct and adjust the test code in real time, which can increase the efficiency of exception removal. FIG. 5 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor test method shown in FIG. 5 corresponds to a part of the operation steps of the semiconductor test system 400 shown in FIG. 4. As shown in FIG. 5, the semiconductor test method of this embodiment includes the following steps: Step 502: The data processing device 440 sends a first response to the data generating device 420; Step 504: In response to the first response, the data generating device 420 generates a first response The data and stores the first data in the memory 422; step 506: the data processing device 440 sends a second response to the data generating device 420; and step 508: in response to the second response, the data generating device 420 will be stored in the memory 422 The first data in is transmitted to the data processing device 440. Step 510: The data processing device 440 stores the first data in the memory 444. FIG. 6 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor test method shown in FIG. 6 may correspond to a part of the operation steps of the semiconductor test system shown in FIGS. 2, 4, 7, and 9. For convenience of description, the semiconductor test system 200 shown in FIG. 2 is taken as an example for description. As shown in FIG. 6, the semiconductor testing method of this embodiment includes the following steps: Step 602: The data processing device 240 processes the second data from the data generating device 220 and generates a second command; Step 604: The data testing device 260 finishes A command test; step 606: the data testing device 260 sends a third response to the data processing device 240; step 608: the data processing device 240 sends a second command to the data testing device 260; and step 610: the data testing device 260 performs Test of Second Order. It should be noted that, in this embodiment, step 602 must be earlier than step 606 in time. In this way, the data processing device 240 has completed the second data before the data testing device 260 completes the test according to the first command. Processing and has generated a second command. In this way, multiple tests performed in the data testing device 260 can be continuously performed without interruption, which greatly reduces the waiting time required for communication between software and hardware in the semiconductor test system. FIG. 7 is a schematic diagram of a semiconductor test system 700 according to an embodiment of the present invention. As shown in FIG. 7, the semiconductor test system 700 includes a data generating device 720, a data processing device 740, and a data testing device 760. The data generating device 720, the data processing device 740, and the data testing device 760 have electrical connections with each other that can transmit signals and instructions. The device under test 780 is mounted on the data testing device 760. The data processing device 740 includes a processor 742, a first memory 744 and a second memory 746. In this embodiment, the data generating device 720 transmits the encoded test data to the data processing device 740. After receiving the encoded test data, the data processing device 740 stores it in the first memory 744. After the encoded test data is stored in the first memory 744, the data processing device 740 returns a response to the data generating device 720, so that the data generating device 720 generates the next test data. The processor 742 of the data processing device 740 decodes the test data stored in the first memory 744 and processes to generate a test command. The generated test command is stored in the second memory 746. At this time, the data processing device 740 sends a response to the data generating device 720, so that the data generating device 720 sends the next encoded test data to the data processing device 740 and stores it in the first memory 744. Each time a test is completed, the data testing device 760 sends a response to the data processing device 740, and then the data processing device 740 sends a test command stored in the second memory 746 to the data testing device 760. After the test command in the second memory 746 is transmitted to the data testing device 760, the data processing device 740 decodes the test data stored in the first memory 744 and processes it to generate a next test command. The next test command generated is stored in the second memory 746. FIG. 8 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor test method shown in FIG. 8 corresponds to a part of the operation steps of the semiconductor test system 700 shown in FIG. 7. As shown in FIG. 8, the semiconductor testing method of this embodiment includes the following steps: Step 802: The data generating device 720 transmits the encoded first data to the data processing device 740, and the data processing device 740 stores the encoded first data In the first memory 744; step 804: the data processing device 740 sends a first response to the data generating device 720, so that the data generating device 720 generates the encoded second data; step 806: the data processing device 740 decodes the encoded first Data, processing generates a first command and stores the first command in the second memory 746; step 808: the data processing device 740 sends a second response to the data generating device 720, so that the data generating device 720 transmits the encoded second data Go to the data processing device 740 and store it in the first memory 744; and step 810: the data testing device 760 sends a third response to the data processing device 740, so that the data processing device 740 sends the first command to the data testing device 760. It should be noted that, in this embodiment, before the data testing device 760 completes the current test command, the data generating device 720 has transmitted the data of the next test to the data processing device 740 and stored in the first memory. And before the data testing device 760 completes the current test command, the data processing device 740 decodes and generates the next test command and stores it in the second memory. In this way, whenever the data testing device 760 completes a test, a response is returned to the data processing device 740 to obtain the command for the next test immediately. Therefore, multiple tests can be performed continuously without interruption, which greatly reduces the waiting time for communication between software and hardware in a semiconductor test system. FIG. 9 is a schematic diagram of a semiconductor test system according to an embodiment of the present invention. As shown in FIG. 9, the semiconductor test system 900 includes a data generating device 920, a data processing device 940, and a data testing device 960. The data generating device 920, the data processing device 940, and the data testing device 960 have electrical connections with each other that can transmit signals and instructions. The device under test 980 is mounted on the data testing device 960. The data processing device 940 includes a processor 942, a memory 944, and a register 946. In this embodiment, the data generating device 920 transmits the encoded test data to the data processing device 940. After the data processing device 940 receives the encoded test data, it stores it in the memory 944 first. When the data processing device 940 receives a response from one of the data testing devices 960 informing that the current test has been completed, the processor 942 of the data processing device 940 decodes the test data stored in the memory 944 and simultaneously passes the temporary register 946 Synchronized to the data testing device 960. That is, the data processing device 940 does not need to store the next test command generated in the memory. The memory usage of the data processing device 940 can be saved. FIG. 10 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor test method shown in FIG. 10 corresponds to a part of the operation steps of the semiconductor test system 900 shown in FIG. 9. As shown in FIG. 10, the semiconductor test method of this embodiment includes the following steps: Step 1002: The data generating device 920 transmits the encoded test data to the data processing device 940; Step 1004: The data processing device 940 transmits the encoded test data Stored in the memory 944; step 1006: the data testing device 960 sends a response to the data processing device 940; step 1008: the data processing device 940 decodes the encoded test data in the memory 944 to generate a test command, and passes the register 946 Synchronized to the data testing device 960. Although the invention has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations do not limit the invention. Those skilled in the art should understand that various changes can be made and replaced with equivalents without departing from the true spirit and scope of the invention as defined by the scope of the appended patent applications. This specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, method, or element to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the patentable applications attached hereto. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the present invention. . Therefore, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present invention.