CN105004984A - Automatic chip testing method - Google Patents
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Abstract
The invention discloses a automatic chip testing method, which is characterized by comprising the steps that: the system is powered on, and initialization is completed; the configuration is carried out, a test thread needs to be started is determined according to chip types, and an instrument transceiving end is configured; a test command is generated, test items and test parameter setting in a chip integrated test case configuration file are read and analyzed, and a command frame is generated and transmitted to a single-board system through a communication interface; and the command is analyzed, and setting and testing steps are carried out. The automatic chip testing method can achieve the automatical test and data storage of chips, can be used for testing the chips quickly, is high in test efficiency, saves test time to a certain extent, can achieve the purposes of automatic configuration of a tested DUT chip, automatic configuration of instruments, automatic recovery of test results and automatic generation of test reports, automatic generation of test case reports and automatic switching of test cases through the development of an automatic chip testing platform.
Description
Technical field
The invention belongs to the technical field of chip, particularly utilize the FPGA of linux operating system, embedded arm processor stone to develop and cooperatively interact and realize chip automatic test approach.
Background technology
All that the bare machine mode of operating system that do not have of low speed microcomputer development realizes substantially in current chip testing apparatus, versatility is poor, high-speed communication needs external special chip and communication stability is poor, there is the bottlenecks such as traffic rate is low, hardware cost is high, development mode is single between apparatus for testing chip and computing machine, and PC software development is limited to the api function that manufacturer provides, operability and transplantability poor; Chip testing efficiency is very low, and for the long-time test that high/low temperature etc. needs some hours, the proving installation based on low speed single-chip microcomputer bare machine framework can only test one single chip at every turn, is difficult to carry out concurrent testing, and needs hand-kept data; There is the duplication of labour in chip testing phase research staff, automaticity is low, research staff's time is taken in a large number, face the requirement of a large amount of project processes, be forced to step into the duplication of labour, this vicious cycle gone round and begun again, cannot improve the software of research staff, hardware R & D Level, becomes the bottleneck of whole chip research and development gradually; Test cannot accomplish traversal, tests incomplete, may there are potential risks, directly can affect the quality of chip; Apparatus for testing chip based on veneer does not enrich due to its storage space and Peripheral Interface, cause Hierarchical Design comparatively simple, modularization and reusability design and incomplete, coupling between module is too strong, cannot develop new proving installation fast, each exploitation can cause the serious waste of manpower and materials and time resource.Proving installation exploitation rests on traditional pattern, and hardware system safeguards that complexity is high, is unfavorable for upgrading and the development of proving installation.
Patented claim 201010622301.X discloses a kind of test macro based on test vector, realize the functional test to digital integrated circuit, the logic function of the main test chip of functional test under certain sequential, its ultimate principle is by means of test vector, excitation is applied to chip, observes consistent whether with imagination of its response.Functional test can cover the failure model of very high percentage logical circuit.This debugging technique supports that single stepping test system comprises two large divisions: the test vector file switching software and the digital integrated circuit chip test machine composition that run on PC.Digital integrated circuit chip test machine is made up of the framework of CPU+FPGA, and CPU is responsible for that pattern file stores, conversion, test process controls, with the function such as main-machine communication.The logical circuit that pattern controls is realized by one piece of FPGA, and FPGA completes waveform generation, the control of Pattern RAM and controlling of sampling, and control and drive system and comparer are with the testing and control of realization to measurand simultaneously.But this patent is by means of test vector, excitation is applied to chip, observe consistent whether with imagination of its response, can not can only test one single chip at every turn, be difficult to carry out concurrent testing, solve the problem that chip testing efficiency is low, and test cannot accomplish traversal, tests incomplete.
Summary of the invention
For solving the problem, the object of the present invention is to provide a kind of robotization chip detecting method, the method aims to provide the 7 Series FPGA exploitations that the Xilinx of an embedded Cortex A9 double-core arm processor can be utilized up-to-date, adopt the development mode of software-hardware synergism, maximum saving hardware cost and Software for Design cycle, abandon the concept of upper and lower computer, PC runs Windows operating system, and test platform runs the method for (SuSE) Linux OS.
Another object of the present invention is to provide a kind of robotization chip detecting method, and the method can be tested chip rapidly, and testing efficiency is high, solves personnel's duplication of labour and inefficiency problem; And add reliability, the stability of system and save hardware cost.
For achieving the above object, technical scheme of the present invention is as follows.
A kind of robotization chip detecting method, is characterized in that the method comprising the steps of:
101, system electrification, completes initialization;
BootLoader according to cutting loads linux kernel, after kernel loads completes by kernel calls firmware program to each hardware module self-inspection, port driver loads, comprise USB driving, a series of kernel starting operation such as network port driving, GPIO are arranged, according to the communication interface foundation of setting and linking of PC, after successful connection, whole system waits for that PC sends order and deals with the work, and completes instruction to PC transmission initialization.
102, be configured;
After the initialization of whole single board system modules completes, PC reads chip id, the kind of test chip is selected according to ID, the test thread needing to start is determined according to chip kind, corresponding thread reads and namely the testing apparatus configuration file of resolving this chip configures temperature control device, instrumentation etc., then generate different command frames according to configuration file, instrument sending and receiving end is configured.
103, test command is generated
Read and analysis chip integration testing use-case configuration file in test item and test parameter arrange, corresponding test case is called according to different test items and test parameter, each test item and test parameter are arranged different test commands according to different type chip, and test command composition command frame also sends single board system to by communication interface.
104, resolve command and arranging
Host computer PC control software design arranges different temperature spots according to configuration file and utilizes timer timing, the time PC control software design reaching setting sends test command according to configuration file to single board system, be responsible for receiving the test data passed back from single board system simultaneously, single board system receives the command frame of PC transmission, message call out process carries out command analysis, decomposite test item and test parameter and preserve, instrumentation is set according to test item and test parameter, closes the information reporting such as chip testing alarm and interruption;
105, test
The test case of decomposing out and test parameter are successively configured to chip under test and test by test case configuration task process, test case configuration task process obtains test parameter configuration return data, each test parameter configuration return data data are reported PC, report test alarming information simultaneously, empty test alarming information, after completing configuration, Message Processing process returns to PC configuration successful message frame.
In described method, include 106 steps further, described 106 steps comprise: in described 103 steps, after PC receives command frame, remove the historical information on last instrument and equipment, start bootrom test assignment, PC controls to issue test sign on, after single board system message sink process receives message, carry out command analysis and process, carry out one by one testing and configuring according to test item and test parameter, the test data of each test item is uploaded to PC and processes by veneer control system.
In described method, include 107 steps further, described 107 steps comprise: PC receives test item and the test data of the transmission of veneer TT&C system, generate test report, PC reads each test item design parameter of chip and test parameter compares, according to design code error range determination repetition measurement item, and generate the test indexs such as the test item of repetition measurement item, test command and test parameter, generate repetition measurement allocation list.
Described method, can repeat above 103,104,105,106,107 steps according to the repetition measurement allocation list generated, testing of equipment all can carry out above steps operation.
In described method, include 109 steps further, described 109 steps comprise: after carrying out a repetition measurement to the test data of off-design target, test data to be appended in 107 test report and to mark, generate final test report, there is at PC data display equipment mark the test item that design load and test value do not conform to, thus save designer and tester's time, help designer and tester to carry out trouble-shoots.
In described 103-105 step, test item described in timing acquiring and test parameter.
Described chip detecting method, in order to improve its communication efficiency further, described in the command frame format that issues be: frame head+test command item+test parameter+School Affairs+postamble; The described command messages form reported is: frame head+reporting message type+alarm information character string+School Affairs+postamble.
Described test parameter, can comprise a plurality of test parameter, these test parameter order arrangements.
The present invention can realize automatic test and the data preservation of chip, can test chip rapidly, testing efficiency is high, save the test duration to a certain extent, by the exploitation of this automatic test platform, the automatic configuration of tested DUT chip, the automatic configuration of instrument, the automatic recovery of test result, the automatic generation of test report can be reached, the energy report of generating test use case automatically, the object of test case automatic switchover.
The method can reduce personnel's participation, improves personnel's utilization factor, solves personnel's duplication of labour and inefficiency problem; And add reliability, the stability of system and save hardware cost.
Accompanying drawing explanation
Fig. 1 is the hardware system structure figure that the present invention implements.
Fig. 2 is the structural drawing of the PC that the present invention implements.
Fig. 3 implements by the present invention the processing flow chart of single board system.
The software control flow chart that Fig. 4 implements for the present invention.
The command messages frame format issued that Fig. 5 implements for the present invention.
The command messages frame format reported that Fig. 6 implements for the present invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The present invention realize robotization chip detecting method hardware system form and be divided into that instrument and device drives part, PC, command analysis control to perform information reporting and test item functional configuration part, single board system forms, wherein hardware is all utilize existing hardware facility to complete, and makes brief of the introduction below as follows:
One, instrument and device drives part, as shown in Figure 1, mainly completes:
(1) communication interface communication module utilizes windows api to realize the opening of communication interface data, closes, sends data, receives data, be packaged into a communication interface class, provide communication interface to open, communication interface closedown, communication interface read data, communication interface write data four interface functions.
(2) instrument arrangement modular meter configuration module is by sending order to high-low temperature chamber, and high-low temperature chamber can be resolved these and ordered and do corresponding operating, and related command form can by obtaining in device data handbook.
(3) equipment state read module equipment state read module is by sending order to equipment, equipment can be resolved these orders and end value is returned, equipment state read module comprise fetch equipment various status datas (alarm, state of temperature, test duration), interface function is carried in the driving of equipment, and user can call arbitrarily the status information of an interface function fetch equipment.
(4) test environment of the layering of VMM hierarchy, there is good extendability and reusability, at all levelsly complete oneself specific function, different people pays close attention to different levels, after veneer control system receives the instruction of PC control software design transmission, for the specifications abstraction function point of chip, then test point is decomposed according to function point, for each test point, form different test item, the test case of different test item produces different test commands and forms layer order, the power function of call instruction layer test forms functional layer, for dissimilar chip, the different test case that is combined to form of different test function is called different test process, and then DUT is tested, the talent only building environment needs understanding at all levels, and the stratification of test structure can reduce complexity and the environment maintenance cost of test environment, new test platform adopts modular design, is divided into a lot of assembly, process, and module that can be general all made by some assemblies, can provide reusability like this, reduces cost of development.
Two, PC, as shown in Figure 2, be responsible for test case and perform control, major function is described as:
(1) the issuing of test configurations order: test case item and configuration parameter composition message frame are handed down to bottom board software by communication interface communication.
(2) control of instrument and equipment: when test case performs, by calling the interface function that instrument drive part provides, the instrument that configuration testing use-case is corresponding or equipment setting option, and obtain test result.
(3) collection of chip testing information: receive the chip testing status message frame that bottom board software reports, and resolve the test mode information obtaining chip and produce, comprise test item and formally start, be completed, test process interrupts etc.; (4) generation of test result report: the test report item generated is comprised the chip testing object information collected in test case parameter, test duration, test process and is filled into side in pre-designed test excel form, directly generate resolution chart and test curve.
Three, command analysis controls to perform information reporting and test item functional configuration part, comprise the module such as the transmission of DUT data message, test item configuration that communication protocol commands is resolved, the control of test pattern performs, collection obtains, the configuration of test function item and alarm-monitor module, mainly carry out:
(1) reception of command messages frame and parsing, receives the command messages frame that Collaborative Control software section issues, and resolves, know to perform which test function according to analysis result, and the parameter of this test function item.
(2) test item functional configuration, according to the function items that will test and the parameter issued, is configured the register of relevant FPGA, chip under test.
(3) chip testing information, alarm, interrupt processing: DUT chip is in test run process, if there is interruption alarm inside, can be reported by the form of interrupt tree, until most top layer interrupt pin, arm processor is after receiving external terminal look-at-me, search downwards step by step according to interrupt tree in interrupt processing function, until find final alarm source, comprise the up-set condition such as temperature, voltage.
(4) the reporting of warning information: after chip warning processing module finds final alarm source, warning information is formed message frame and report Collaborative Control software by communication interface.
Four, single board system, needs establishment three tasks, two message queues, two interrupt processings.Receive Command Task: be responsible for the test command message frame that reception upper strata Collaborative Control software issues.Communication interface reporting message task: be responsible for reporting test platform internal alarm status message.Test case configuration task: the configuration being responsible for test function item register.Chip alarm interrupt processing: receive during test platform is sent here and have no progeny, search final alarm source according to interrupt tree, and this alarm information is sent in alarm information queue.Test command message queue: be responsible for receiving the communication between Command Task and test case configuration task.Communication interface reception task receives orders after message frame, this message is sent in message queue.Test result message queue: the communication between primary responsibility interrupt processing and reporting message task, after interrupt processing finds final alarm source, composition message is sent in alarm information queue.
Its treatment scheme as shown in Figure 3, after starting, first creates serial ports and receive Command Task, serial ports report and alarm task, test case configuration task, then create the message queue of communication between each task, and configuring external pin is interrupted, disconnecting process function; Carry out ADC test, temperature sensor test, fixed data configuration more successively, write the step of register, read register, until shut-down operation.
Wherein, ADC test, temperature sensor are tested, fixed data configures, write register, these steps of read register can carry out cycle control.
Implementation method as shown in Figure 4, comprises the steps:
101, single board system powers on, BootLoader according to cutting loads linux kernel, after kernel loads completes by kernel calls firmware program to each hardware module self-inspection, port driver loads, comprise USB driving, a series of kernel starting operation such as network port driving, GPIO are arranged, according to the communication interface foundation of setting and linking of PC, after successful connection, whole system waits for that PC sends order and deals with the work, and completes instruction to PC transmission initialization.
102, after the initialization of whole single board system modules completes, PC reads chip id, the kind of test chip is selected according to ID, the test thread needing to start is determined according to chip kind, corresponding thread reads and namely the testing apparatus configuration file of resolving this chip configures temperature control device, instrumentation etc., then generate different command frames according to configuration file, instrument sending and receiving end is configured.
103, read and analysis chip integration testing use-case configuration file in test item and test parameter arrange, corresponding test case is called according to different test items and test parameter, each test item and test parameter are arranged different orders according to different type chip, and composition command frame also sends single board system to by communication interface.
104, host computer PC control software design arranges different temperature spots according to configuration file and utilizes timer timing, the time PC control software design reaching setting sends test command according to configuration file to single board system, be responsible for receiving the test data passed back from single board system simultaneously, single board system receives the command frame of PC transmission, message call out process carries out command analysis, decomposite test item and test parameter and preserve, instrumentation is set according to test item and test parameter, closes the information reporting such as chip testing alarm and interruption;
105, test case configuration task process is successively configured to chip under test tests decomposing test case out and test parameter, test case configuration task process obtains test parameter configuration return data, each test parameter configuration return data data are reported PC, report test alarming information simultaneously, empty test alarming information, after completing configuration, Message Processing process returns to PC configuration successful message frame.
106, the step PC wait-receiving mode chip success configuration messages frames such as above 203, after receiving configuration successful frame, remove the historical information on last instrument and equipment, start bootrom test assignment, PC controls to issue test sign on, after single board system message sink process receives message, carries out command analysis and process, carry out one by one testing and configuring according to test item and test parameter, the test data of each test item is uploaded to PC and processes by veneer control system.
107, PC receives test item and the test data of single board system transmission, generate test report, PC reads each test item design parameter of chip and test parameter compares, according to design code error range determination repetition measurement item, and generate the test indexs such as the test item of repetition measurement item, test command and test parameter, generate repetition measurement allocation list.
108, repeat the steps such as above 203,204,205,206,207 according to the repetition measurement allocation list generated, testing of equipment all can carry out above steps operation.
109, after a repetition measurement being carried out to the test data of off-design target, test data to be appended in 207 test report and to mark, generate final test report, the test item that design load and test value do not conform to is there is at PC data display equipment mark, thus save designer and tester's time, help designer and tester to carry out trouble-shoots.
In order to improve its communication efficiency further, the method is defined instruction and frame format, and as shown in Figure 5, the command messages frame format that veneer bottom software reports is as shown in Figure 6 to the command messages frame format that upper strata Collaborative Control software issues.Upper strata Collaborative Control software and veneer bottom software adopt the communication modes of similar UDP.Veneer bottom software end does service end, and upper strata Collaborative Control software end does client.Test command item: 0x01:MCU functional test, 0x02: performance test, 0x03 high/low temperature is tested ... test parameter: different test items has different test parameters.For test command item for high/low temperature test, test parameter 1 is the test duration, test parameter 2 is probe temperature.School Affairs: the parity check sum of test command item and all test parameters.Reporting message type: 0x01: chip test platform alarm; 0x02: the effect and the mistake that receive transmitting order to lower levels; 0x03: test function configuration successful alarm information character string: the alarm source information that DUT or FPGA is detailed.
The present invention can realize automatic test and the data preservation of chip, personnel's participation can be reduced, raising personnel utilization factor, save the test duration to a certain extent, by the exploitation of this automatic test platform, the automatic configuration of tested DUT chip, the automatic configuration of instrument, the automatic recovery of test result, the automatic generation of test report can be reached, the energy report of generating test use case automatically, the object of test case automatic switchover.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. a robotization chip detecting method, is characterized in that the method comprising the steps of:
101, system electrification, completes initialization;
102, be configured;
After the initialization of whole single board system modules completes, PC reads chip id, selects the kind of test chip according to ID, determines the test thread needing to start according to chip kind, and corresponding thread reads and resolves the testing apparatus configuration file of this chip;
103, test command is generated
Read and analysis chip integration testing use-case configuration file in test item and test parameter arrange, corresponding test case is called according to different test items and test parameter, each test item and test parameter are arranged different test commands according to different type chip, and test command composition command frame also sends single board system to by communication interface;
104, resolve command and arranging
Host computer PC control software design arranges different temperature spots according to configuration file and utilizes timer timing, the time PC control software design reaching setting sends test command according to configuration file to single board system, be responsible for receiving the test data passed back from single board system simultaneously, single board system receives the command frame of PC transmission, message call out process carries out command analysis, decomposite test item and test parameter and preserve, instrumentation is set according to test item and test parameter, closes the information reporting such as chip testing alarm and interruption;
105, test
The test case of decomposing out and test parameter are successively configured to chip under test and test by test case configuration task process, test case configuration task process obtains test parameter configuration return data, each test parameter configuration return data data are reported PC, report test alarming information simultaneously, empty test alarming information, after completing configuration, Message Processing process returns to PC configuration successful message frame.
2. robotization chip detecting method as claimed in claim 1, it is characterized in that in described method, include 106 steps further, described 106 steps comprise: in described 103 steps, after PC receives command frame, remove the historical information on last instrument and equipment, start bootrom test assignment, PC controls to issue test sign on, after single board system message sink process receives message, carry out command analysis and process, carry out one by one testing and configuring according to test item and test parameter, the test data of each test item is uploaded to PC and processes by veneer control system.
3. robotization chip detecting method as claimed in claim 1, it is characterized in that in described method, include 107 steps further, described 107 steps comprise: PC receives test item and the test data of the transmission of veneer TT&C system, generate test report, PC reads each test item design parameter of chip and test parameter compares, according to design code error range determination repetition measurement item, and generate the test indexs such as the test item of repetition measurement item, test command and test parameter, generate repetition measurement allocation list.
4. robotization chip detecting method as claimed in claim 1, is characterized in that described method, can repeat above 103,104,105,106,107 steps according to the repetition measurement allocation list generated.
5. robotization chip detecting method as claimed in claim 4, it is characterized in that in described method, include 109 steps further, described 109 steps comprise: after carrying out a repetition measurement to the test data of off-design target, test data to be appended in 107 test report and to mark, generating final test report.
6. robotization chip detecting method as claimed in claim 4, is characterized in that in described 103-105 step, test item described in timing acquiring and test parameter.
7. robotization chip detecting method as claimed in claim 1, the command frame format issued described in it is characterized in that is: frame head+test command item+test parameter+School Affairs+postamble; The described command messages form reported is: frame head+reporting message type+alarm information character string+School Affairs+postamble.
8. robotization chip detecting method as claimed in claim 7, is characterized in that described test parameter, can comprise a plurality of test parameter, these test parameter order arrangements.
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