CN102183726A - Field programmable gate array (FPGA)-based integrated circuit chip testing system and method - Google Patents

Field programmable gate array (FPGA)-based integrated circuit chip testing system and method Download PDF

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Publication number
CN102183726A
CN102183726A CN201110063373XA CN201110063373A CN102183726A CN 102183726 A CN102183726 A CN 102183726A CN 201110063373X A CN201110063373X A CN 201110063373XA CN 201110063373 A CN201110063373 A CN 201110063373A CN 102183726 A CN102183726 A CN 102183726A
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China
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chip
test
fpga
measured
test vector
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CN201110063373XA
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Chinese (zh)
Inventor
杨林
郑灼荣
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建荣集成电路科技(珠海)有限公司
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Priority to CN201110063373XA priority Critical patent/CN102183726A/en
Publication of CN102183726A publication Critical patent/CN102183726A/en

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Abstract

The invention discloses a field programmable gate array (FPGA)-based integrated circuit testing system, and a method for testing a digital-analog hybrid integrated circuit chip provided with a digital module or using a digital module as a main module and provided with a few analog modules by using the testing system. The system mainly comprises a personal computer (PC) machine, a main control chip, a FPGA chip, configuration information storage equipment and testing vector storage equipment. The testing method is implemented by the following steps that: the main control chip configures the FPGA chip, the main control chip sends a testing command to the FPGA chip, the FPGA chip sends an excitation signal to a chip to be tested and acquires the output response of the chip to be tested, or the analog parameter module acquires analog output response, the FPGA chip compares the output response or the analog output response of the chip to be tested with the testing information and judges the consistency of the output response and the testing information, and the chip to be tested is an accepted product or a defective product is judged. The system and the method can be widely applied in the field of integrated circuit chip test.

Description

A kind of IC chip test System and method for based on FPGA
Technical field
The present invention relates to a kind of IC chip test system based on FPGA, and utilize this test macro to the integrated circuit (IC) chip of band digital module or based on digital module, have the method that the hybrid digital-analog integrated circuit chip of a small amount of analog module is tested.
Background technology
Development along with IC industry, the testing cost proportion of integrated circuit (IC) chip is constantly soaring, integrated circuit (IC) design company often needs to seek professional chip testing machine chip is tested in chip design with after producing, to discern and to pick out bad sheet, have only by the qualified chip of test and just can sell use.At present domestic IC chip test is mainly bought the board test voluntarily or is entrusted professional testing agency to test by integrated circuit (IC) design company.But because the professional test machine costs an arm and a leg, domestic design corporation generally is unwilling substantial contribution is put on the equipment of buying costliness, and simultaneously domestic professional testing agency is few, causes the measurement examination of chip to become the big bottleneck that product can not put goods on the market fast.In the market based on digital module, in addition the integrated circuit of a small amount of analog module is very many, the design cycle is short, with low cost, shipment amount is big, and is therefore also relatively tight to the testing cost control of this type of chip.
Summary of the invention
Technical matters to be solved by this invention is to overcome the deficiencies in the prior art, provide a kind of simple in structure, be easy to carry, cost is lower, the IC chip test system based on FPGA of stable performance.
The present invention also provides a kind of said integrated circuit chip test system that utilizes to come to the integrated circuit (IC) chip of band digital module or based on digital module, have the method that the hybrid digital-analog integrated circuit chip of a small amount of analog module is tested; by this method, can reach test period short, testing cost is low, test effect fast.
A kind of technical scheme that is adopted based on the IC chip test system of FPGA of the present invention is: this system comprises PC, main control chip, fpga chip, configuration information memory device, test vector memory device,
Described configuration information memory device is used to store the configuration information that described fpga chip is configured;
Described test vector memory device is used to store the test vector that compares with chip to be measured;
Described main control chip is used to dispose described fpga chip, controls described fpga chip chip to be measured is tested, and the test result that described fpga chip feeds back is sent to described PC;
Described PC is used to the test result that shows that described main control chip sends;
Described fpga chip is used to receive the test command that described main control chip sends, and read test vector from described test vector memory device is tested chip to be measured, judges whether chip to be measured is non-defective unit, and test result is fed back to described main control chip.
Described IC chip test system based on FPGA also comprises the analog parameter module, and described analog parameter module is used to test the analog parameter value of chip to be measured, and test value is sent to described fpga chip.
Described IC chip test system based on FPGA also comprises the mechanical arm interface, and described mechanical arm interface is used for being connected with peripheral mechanical arm and controlling the classification that described mechanical arm carries out chip under test.
Described PC also can be used for revising the configuration information in the described configuration information memory device, perhaps is used for upgrading the test vector of described test vector memory device, to adapt to the test request of different chips to be measured.
Described fpga chip comprises CPU, clock generator, test vector storer, timer, mobile storage interface, serial data interface.
Described test vector memory device is USB flash disk or SD card or MS card.
A kind of technical scheme that is adopted based on the IC chip test method of FPGA of the present invention may further comprise the steps:
(1) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(2) described main control chip sends test command to described fpga chip;
(3) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal
(4) described fpga chip is gathered the output response after chip to be measured is encouraged;
(5) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(6) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
Perhaps, adopt described IC chip test system to come the method that integrated circuit (IC) chip is tested be may further comprise the steps based on FPGA:
(a) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(b) described main control chip sends test command to described fpga chip;
(c) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal;
If include digital module in the chip to be measured, then turn to following steps:
(d) described fpga chip is gathered the output response after chip to be measured is encouraged;
(e) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(f) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products;
If include analog module in the chip to be measured, then turn to following steps:
(g) described analog parameter module is gathered the simulation output response after chip to be measured is encouraged and response is exported in the simulation that collects and sends to described fpga chip;
(h) described fpga chip compares the detecting information in the simulation of the chip to be measured that receives output response and the described test vector, judges the consistance of comparative result;
(i) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
The invention has the beneficial effects as follows: mainly comprise PC, main control chip, fpga chip and some peripheral memory devices owing to the present invention is based on the IC chip test system of FPGA, both can test the digital module of chip to be measured, can test the analog module of chip to be measured again, and whole test system is as a test macro and need not to cooperate with other test machines and just can finish chip testing independently, so test macro of the present invention structurally is comparatively simple, this is easy to carry; Because the whole cost of test macro of the present invention mainly is to concentrate on the described fpga chip, other all are the components and parts of using always as components and parts such as main control chips, and described fpga chip all is cheaply, so cost of testing system of the present invention is cheap; Because test macro of the present invention as long as described fpga chip is provided with, just can be tested chip to be measured, and other components and parts can not change, so test macro performance of the present invention is stable.
Because the present invention is based on the IC chip test method of FPGA is to utilize described main control chip to dispose described fpga chip, and then utilize described fpga chip to come chip to be measured is detected, its test speed is fast, so method of testing test period weak point of the present invention has reduced testing cost simultaneously indirectly.
Because system of the present invention is connected with the PC of periphery, can show test results by described PC, perhaps revise the described configuration information and the test vector that upgrades in the described test vector memory device that is stored in the described configuration information memory device, to tackle the test request of different money chips, so the present invention disposes conveniently, perfect in shape and function.
Because test frequency, the detecting information in the described test vector among the present invention, communication port is all adjustable, so the present invention can solve the excitation when chip to be measured is tested and the sequence problem of sampling.
Because the described main control chip in the system of the present invention also is connected with mechanical arm by described mechanical arm interface, the instruction that described mechanical arm can send according to main control chip, chip → test chip → robotization sorting chips is got in the realization robotization, so the present invention both can be manually to sorting chips, also can realize that test is full-automatic, greatly improve testing efficiency by described mechanical arm.
Total system volume of the present invention and quality are all smaller, easy to carry, are easy to safeguard and debugging.
Description of drawings
Fig. 1 is a theory diagram of the present invention;
Fig. 2 is the process flow diagram of the embodiment of the invention one;
Fig. 3 is the process flow diagram of the embodiment of the invention two;
Fig. 4 is described fpga chip structural drawing.
Embodiment
Embodiment one:
As shown in Figure 1 and Figure 2, the present invention relates to be a kind of based on FPGA the IC chip test system and utilize this test macro to come the method that the integrated circuit (IC) chip that has digital module is tested.In the present embodiment, described test macro comprises PC, main control chip, fpga chip, configuration information memory device, test vector memory device and mechanical arm interface.Described test vector memory device can be USB flash disk or SD card or MS card.As shown in Figure 4, described fpga chip comprises CPU, clock generator, test vector storer, timer, mobile storage interface, serial data interface.Between described PC and the described main control chip, between described main control chip and the described fpga chip, between described main control chip and the described configuration information memory device, between described PFGA chip and the described test vector memory device, all realize being connected between described fpga chip and the chip to be measured.Described mechanical arm interface is used for being connected with peripheral mechanical arm and controlling described mechanical arm and carry out sorting chips, the instruction that described mechanical arm can send according to described main control chip, chip under test on production line realization robotization is got chip → test chip → robotization to sorting chips, separately, greatly improved testing efficiency through test and the chip that is defined as non-defective unit and defective products.
Described configuration information memory device is used to store the configuration information that described fpga chip is configured; Described test vector memory device is used to store the test vector that compares with chip to be measured; Described main control chip is used to dispose described fpga chip, controls described fpga chip chip to be measured is tested, and the test result that described fpga chip feeds back is sent to described PC; Described PC is used to the test result that shows that described main control chip sends, perhaps be used for revising the configuration information of described configuration information memory device, perhaps be used for upgrading the test vector of described test vector memory device, to adapt to the test request of different chips to be measured; Described fpga chip is used to receive the test command that described main control chip sends, and read test vector from described test vector memory device is tested chip to be measured, judges whether chip to be measured is non-defective unit, and test result is fed back to described main control chip.
In the present embodiment, only have digital module in the chip to be measured, a kind of technical scheme that is adopted based on the IC chip test method of FPGA of the present invention may further comprise the steps:
(1) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(2) described main control chip sends test command to described fpga chip;
(3) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal
(4) described fpga chip is gathered the output response after chip to be measured is encouraged;
(5) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(6) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
When judging that chip under test is a defective products, described fpga chip will be at the relevant position of described test vector mark failpoint, and failure conditions is noted, and searches by failure analysis and problem, find out failure cause, so that chip under test is repaired or directly re-designed.
Described fpga chip can adopt the low-cost fpga chip of ALTERA cyclone III EP3C25, EP3C40 series.
Embodiment two:
The difference of present embodiment and embodiment one is: in the described chip to be measured except including digital module, also include analog module, correspondingly, in IC chip test system, also include the analog parameter module based on FPGA, described analog parameter module is used to test the analog parameter value of chip to be measured, and test value is sent to described fpga chip.Testing procedure when in the present embodiment, adopting described IC chip test system based on FPGA to come chip to be measured tested is as follows:
(a) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(b) described main control chip sends test command to described fpga chip;
(c) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal;
Below be the step that the digital module that comprises in the chip to be measured is tested:
(d) described fpga chip is gathered the output response after chip to be measured is encouraged;
(e) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(f) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
Below be the step that the analog module that includes in the chip to be measured is tested:
(g) described analog parameter module is gathered the simulation output response after chip to be measured is encouraged and response is exported in the simulation that collects and sends to described fpga chip;
(h) described fpga chip compares the detecting information in the simulation of the chip to be measured that receives output response and the described test vector, judges the consistance of comparative result;
(i) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
The analog parameter module that uses in above-mentioned steps can be set to ADC chip comparatively accurately.
The present invention can be widely used in the IC chip test field.

Claims (8)

1. IC chip test system based on FPGA, it is characterized in that: described system comprises PC, main control chip, fpga chip, configuration information memory device, test vector memory device,
Described configuration information memory device is used to store the configuration information that described fpga chip is configured;
Described test vector memory device is used to store the test vector that compares with chip to be measured;
Described main control chip is used to dispose described fpga chip, controls described fpga chip chip to be measured is tested, and the test result that described fpga chip feeds back is sent to described PC;
Described PC is used to the test result that shows that described main control chip sends;
Described fpga chip is used to receive the test command that described main control chip sends, and read test vector from described test vector memory device is tested chip to be measured, judges whether chip to be measured is non-defective unit, and test result is fed back to described main control chip.
2. the IC chip test system based on FPGA according to claim 1, it is characterized in that: described IC chip test system based on FPGA also comprises the analog parameter module, described analog parameter module is used to test the analog parameter value of chip to be measured, and test value is sent to described fpga chip.
3. the IC chip test system based on FPGA according to claim 1, it is characterized in that: described IC chip test system based on FPGA also comprises the mechanical arm interface, and described mechanical arm interface is used for being connected with peripheral mechanical arm and controlling described mechanical arm and carry out sorting chips.
4. the IC chip test system based on FPGA according to claim 1, it is characterized in that: described PC also can be used for revising the configuration information in the described configuration information memory device, perhaps be used for upgrading the test vector of described test vector memory device, to adapt to the test request of different chips to be measured.
5. the IC chip test system based on FPGA according to claim 1 is characterized in that: described fpga chip comprises CPU, clock generator, test vector storer, timer, mobile storage interface, serial data interface.
6. the IC chip test system based on FPGA according to claim 1 is characterized in that: described test vector memory device is USB flash disk or SD card or MS card.
7. one kind is adopted the described IC chip test system based on FPGA of claim 1 to come the method that integrated circuit (IC) chip is tested, and it is characterized in that this method may further comprise the steps:
(1) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(2) described main control chip sends test command to described fpga chip;
(3) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal;
(4) described fpga chip is gathered the output response after chip to be measured is encouraged;
(5) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(6) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
8. one kind is adopted the described IC chip test system based on FPGA of claim 2 to come the method that integrated circuit (IC) chip is tested, and it is characterized in that this method may further comprise the steps:
(a) described main control chip comes the configuration information that is stored in the described configuration information memory device described fpga chip is configured, and it is configured to and corresponding control of chip to be measured and FPDP processor;
(b) described main control chip sends test command to described fpga chip;
(c) after described fpga chip receives test command, read test vector from described test vector memory device, and the test vector that reads carried out information analysis, the sequential of the detecting information in the described test vector by test request is transferred to chip to be measured with pumping signal;
If include digital module in the chip to be measured, then turn to following steps:
(d) described fpga chip is gathered the output response after chip to be measured is encouraged;
(e) described fpga chip compares the detecting information in the output of the chip to be measured that collects response and the described test vector, judges the consistance of comparative result;
(f) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products;
If include analog module in the chip to be measured, then turn to following steps:
(g) described analog parameter module is gathered the simulation output response after chip to be measured is encouraged and response is exported in the simulation that collects and sends to described fpga chip;
(h) described fpga chip compares the detecting information in the simulation of the chip to be measured that receives output response and the described test vector, judges the consistance of comparative result;
(i) comparative result is judged as unanimity, judges that then chip to be measured is a non-defective unit, and comparative result is judged as inconsistent, judges that then chip to be measured is a defective products.
CN201110063373XA 2011-03-16 2011-03-16 Field programmable gate array (FPGA)-based integrated circuit chip testing system and method CN102183726A (en)

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Application publication date: 20110914