CN108241117A - System and method for testing semiconductor devices - Google Patents
System and method for testing semiconductor devices Download PDFInfo
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- CN108241117A CN108241117A CN201710062839.1A CN201710062839A CN108241117A CN 108241117 A CN108241117 A CN 108241117A CN 201710062839 A CN201710062839 A CN 201710062839A CN 108241117 A CN108241117 A CN 108241117A
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- 238000012360 testing method Methods 0.000 title claims abstract description 244
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims description 22
- 238000012545 processing Methods 0.000 claims abstract description 116
- 230000004044 response Effects 0.000 claims abstract description 44
- 230000015654 memory Effects 0.000 claims description 43
- 230000005540 biological transmission Effects 0.000 claims description 24
- 238000010586 diagram Methods 0.000 description 20
- 238000010998 test method Methods 0.000 description 15
- 238000005259 measurement Methods 0.000 description 12
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
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- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 238000011160 research Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
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Abstract
The present disclosure provides a system for testing a semiconductor device, which includes a data generating apparatus, a data testing apparatus, and a data processing apparatus. The data processing device is configured to transmit a first command to the data testing device and transmit a first response to the data generating device after transmitting the first command. After receiving the first response, the data generating device transmits a first data to the data processing device.
Description
Technical field
This exposure system is used to test the side of semiconductor subassembly about a kind of for testing the system of semiconductor subassembly and one kind
Method.
Background technology
In general, chip (such as IC chip) can carry out electrical testing after completing, judgement chip is
No is electrical normal non-defective unit, to ensure quality of the chip in shipment.In semiconductor test field, the testing time is automatic
Key factor that is important and influencing production capacity in test.In general, Board Lot (unit of the production capacity can be done per hour
Per hour) as measurement standard.Testing time is influenced by three kinds of factors：The design of test method, the optimization of test program
Degree and the efficiency for testing system.And the efficiency for testing system depends primarily on：The execution of the execution speed, software of hardware
The length of time for communication between efficiency and software and hardware.
In traditional chip testing flow, after having performed a test whenever hardware testing end, it is necessary to wait for test machine
Application programming interface (Application Programming Interface, API) in computer generates next record and surveys
Examination order, and by after the memory of test command write-in board control unit, hardware testing end could be obtained via board control unit
Obtain next record test command.Therefore, when largely being tested, hardware testing end waits for the time of next record test command will
Testing efficiency is caused to reduce.
In order to reduce the consuming of time for communication between software and hardware, existing a kind of embedded system test mode of exploitation, embedding
In embedded system testing process, in all advance burned hard disk to hardware testing end of all test program codes, therefore whenever hardware
After test lead has performed a test command, next record test command can be captured from the memory at hardware testing end immediately.
However, though embedded system can reduce instruction transmission time, but also the problem of bring other.With more and more work(
It can be embedded in hardware and perform, the modification elasticity of testing process is caused to become smaller.Because all program codes are all burned to hard in advance
It, can not directly interrupt test and right when program code, which has abnormal or test result, generates abnormal in the hard disk of part test lead
Test program code carries out except mistake, causing the inconvenience that research staff corrects and adjusts test program code, therefore embedded system
System test mode is not used largely.Therefore there is an urgent need for a kind of semiconductor test system and methods, can improve traditional die test stream
It is abnormal also efficiently to exclude test program for the efficiency of journey.
Invention content
One of this exposure embodiment provides a kind of system for testing semiconductor subassembly, and it includes a data to generate dress
It puts, a data test device and a data processing equipment.Data processing equipment is configured to one first order of transmission to data and surveys
Trial assembly is put and transmission one first is responded to data generating apparatus after the first order of transmission.After the first response is received, data
Generation device transmits one first data to the data processing equipment.
Another embodiment of this exposure provides a kind of method for testing semiconductor subassembly, and it includes provide data production
Generating apparatus provides a data processing equipment and provides a data test device.This method further includes：By the data processing
Device transmits one first order to the data test device at the first time one, makes the data test device according to first order
It is tested；And after first order is sent to the data test device, by one first response of data processing equipment transmission
To the data generating apparatus.Wherein the data generating apparatus is according to the first response one first data of transmission received to the number
According to processing unit.
The described semiconductor test system of this exposure and semiconductor test method can promote the efficiency of semiconductor test,
The usage amount of memory in semiconductor test system is reduced, and increases the exclusion efficiency of test program exception.
Description of the drawings
Fig. 1 is painted the schematic diagram of semiconductor test system.
Fig. 2 is painted the schematic diagram of the semiconductor test system of one embodiment of the invention.
Fig. 3 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.
Fig. 4 is painted the schematic diagram of the semiconductor test system of one embodiment of the invention.
Fig. 5 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.
Fig. 6 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.
Fig. 7 is painted the schematic diagram of the semiconductor test system of one embodiment of the invention.
Fig. 8 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.
Fig. 9 is painted the schematic diagram of the semiconductor test system of one embodiment of the invention.
Figure 10 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.
Specific embodiment
This exposure provides several different implementations or embodiment, available for realizing the different characteristic of the present invention.For
For the sake of simplifying explanation, this exposure also describes specific spare part and the example of arrangement simultaneously.It please notes that and these particular examples is provided
Purpose be only that demonstration rather than give any restrictions.
" first ", " second ", " third " and " the 4th " words and phrases system used in herein describes various assemblies, group
Part, step, signal or order, these components, component, step, signal with or order should be not only restricted to these words and phrases.These words and phrases
It is only used for a component, component, step, signal or order and another component, component, step, signal or order respectively.Unless interior text
In clearly indicate, otherwise when in this article use such as " first ", " second ", " third " and " the 4th " words and phrases when, not anticipate
Refer to sequence or sequence.
Fig. 1 is painted the schematic diagram of semiconductor test system.As shown in Figure 1, semiconductor test system includes measuring and calculation
Machine 100, board control unit 120, hardware testing machine 140 and load board 180.Test computer 100, board control unit 120,
Hardware testing machine 140 and load board 180 have the electrical connection that can transmit signal and instruction to each other, and test system 160 is then pacified
Loaded in load board 180.Generally say it, test system can be an IC chip.
Test computer 100 includes processor 102 and memory 104.Test computer 100 is by the API being mounted thereon
It generates test data and is stored in memory 104.Board control unit 120 include processor 122, memory 124 and input/it is defeated
Go out of the port 126.Board control unit 120 can receive the test data from test computer 100, and be produced after test data is handled
Raw test command.Test command can be stored in memory 124, and is sent via input/output end port 126 to hardware testing machine 140.
Hardware testing machine 140 may include multiple modules for being used to test semiconductor subassembly.For example, hardware testing machine
140 may include DC power module 142, accurate measurement unit (Precision Measurement Unit, PMU) 144, digital mould
Block 146 and relay plate 148.According to the content of produced test command, board control unit 120 is via input/output port 126
Test command is respectively sent to the corresponding module of hardware testing machine 140.
DC power module 142 provides the measurement of semiconductor subassembly DC parameter.For example, DC power module 142 can be with
Test electric current is provided to semiconductor subassembly to be tested, and measures the relevant voltage of semiconductor subassembly.Alternatively, DC power module
142 can provide test voltage to semiconductor subassembly to be tested and measure the phase induced current of semiconductor subassembly.
Accurate measurement unit 144 also provides the measurement of semiconductor subassembly DC parameter.However, compared to DC power module
142, accurate measurement unit 144 can provide the measurement of more high accurancy and precision (accuracy).In general, accurate measurement unit
144 systems are for the test of low current and small voltage.Because its voltage and current provided is smaller, therefore must have more preferably smart
Accuracy.
In the test of IC chip, other than the above-mentioned electrical measurement for direct current, also need for integrated electricity
The different function of road chip is tested.Digital module 146 can be directed to the receipts of a variety of digital functions progress signal of integrated circuit
Hair test.For example, digital module 146 can be directed to the digital control I2C buses (Inter-Integrated of integrated circuit
Circuit Bus)、TTL(Transistor-transistor logic)、SPI(Serial Peripheral
Interface) and the Tx/Rx of fundamental frequency sends and receives signals test.In order to carry out above-mentioned test, digital module 146 in addition to
It can set other than voltage quasi position and current value, moreover it is possible to when setting signal switching frequency, voltage rise/fall edge, reception/transmission
Between synchronization etc..In general, the voltage range that digital module 146 can provide is smaller, about connect with accurate measurement unit 144
Closely.In one embodiment, digital module 146 can also provide accurate measurement unit 144 institute it is functional.
Relaying version 148 can provide hardware testing machine 140 path handoff functionality.In semiconductor component test, often because of cost
The stitch (pin) of limitation or test system number is excessive so that 140 available testing channel number deficiency of hardware testing machine.
There must be stitch to share identical testing channel in the case of this, control switching can be carried out through relay plate 148.
Fig. 2 is painted the schematic diagram of the semiconductor test system 200 of one embodiment of the invention.As shown in Fig. 2, semiconductor test
System 200 includes data generating apparatus 220, data processing equipment 240 and data test device 260.Data generating apparatus 220,
Data processing equipment 240 and data test device 260 have the electrical connection that can transmit signal and instruction to each other.Test system
280 are installed on data test device 260.Data processing equipment 240 includes processor 242 and memory 244.
Data generating apparatus 220 can generate a test data, and data processing equipment 240 is received from data generating apparatus 220
After test data, test data can be handled and generate a test command.The processing of test data and the production of test command
Life is performed by processor 242.Data test device 260 can be according to the test command from data processing equipment 240 to dress to be measured
280 are put to be tested.In one of present invention embodiment, test command is sent to data test in data processing equipment 240
After device 260, data processing equipment 240 generates a response to data generating apparatus 220 immediately.Data generating apparatus 220 is being received
Just next record test data is generated after to response and is sent to data processing equipment 240.
The next record test data of reception is handled and generates next record test command by data processing equipment 240.When
After data test device 260 completes test according to current test command, one can be generated and respond to data processing equipment 240, this
When data processing equipment 240 next record test command can be sent to data test device 260.
It is noted that in this embodiment, data generating apparatus 220 does not need to wait for data test device 260 complete
Into current test command, the test data for next record test can be generated.Data processing equipment 240 is filled in data test
Before putting the current test command of 260 completions, the processing of next test data is just completed and has generated next record test command.
In this way, the multiple tests carried out in data test device 260 can continue to carry out without interruption, and semiconductor survey is greatly decreased
The spent stand-by period is linked up in test system between software and hardware.
In addition, data processing equipment 240 can be to judge test command according to the response that data test device 260 returns
It is no to be appropriately carried out.If it is abnormal that data processing equipment 240 judges that the response that data test device 260 returns generates, can generate
Corresponding warning message enables research staff to correct and adjust in real time test program code, can so increase the efficiency of Abnormality remove.
Fig. 3 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.As shown in figure 3, the present embodiment half
Conductor test method includes the following steps：
Step 302：First data of the processing of data processing equipment 240 from data generating apparatus 220, generate the first order
And the first order is sent to data test device 260；
Step 304：Data test device 260 tests test system 280 according to the first order；
Step 306：The transmission of data processing equipment 240 first is responded to data generating apparatus 220；
Step 308：After the from data processing equipment 240 first response is had received, data generating apparatus 220 generates use
Data processing equipment 240 is sent in the second data of next record test, and by the second data；
Step 310：Data processing equipment 240 handles the second data and generates and ordered for the second of next record test；
Step 312：After data test device 260 completes the test of the first order, data processing equipment 240 is by second
Order is sent to data test device 260；And
Step 314：Data test device 260 tests test system 280 according to the second order.
It is noted that the difference of step 304 and priority in step 306 not necessarily existence time, that is to say, that step
304 can start simultaneously at progress with step 306.
Fig. 4 is painted the schematic diagram of the semiconductor test system 400 of one embodiment of the invention.As shown in figure 4, semiconductor test
System 400 includes data generating apparatus 420, data processing equipment 440 and data test device 460.Data generating apparatus 420,
Data processing equipment 440 and data test device 460 have the electrical connection that can transmit signal and instruction to each other.Test system
480 are installed on data test device 460.Data generating apparatus 420 includes memory 422.Data processing equipment 440 includes processing
Device 442 and memory 444.
In this embodiment, data generating apparatus 420 generates one according to the first of 440 transmission of data processing equipment the response
Test data.After data generating apparatus 420 generates a test data, test data data are not sent to directly
Processing unit 440, but first test data is stored in memory 422.Receiving second sound of one of the transmission of data processing equipment 440
Test data is sent to data processing equipment 440 by Ying Hou, 420 ability of data generating apparatus.
After a test command is sent to data test device 460 by data processing equipment 440, the first response is just sent
To data generating apparatus.And data processing equipment 440 can transmit the second response according to different situations.It is generally sayed, at data
When managing device 440 and complete the processing of current test data, and next record test data can be handled, transmission second is responded extremely
Data generating apparatus 420.
In this embodiment, data generating apparatus 420 generates survey according to the first of 440 transmission of data processing equipment the response
Data are tried, data generating apparatus 420 can be avoided constantly to generate test data, and from therefore reducing data generating apparatus 420
Memory usage amount.In addition, data processing equipment 440 can judge to test according to the response that data test device 460 returns
Whether order is appropriately carried out.The judgement of the transmission and exception of first response and the second response is performed by processor 442.If number
Judge that the response that data test device 460 returns generates exception according to processing unit 440, corresponding warning message can be generated, make to grind
Hair personnel can correct and adjust in real time test program code, can so increase the efficiency of Abnormality remove.
Fig. 5 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.Semiconductor test side shown in Fig. 5
Method corresponds to one of the semiconductor test system 400 shown in Fig. 4 part operation step.As shown in figure 5, the present embodiment is partly led
Body examination method for testing includes the following steps：
Step 502：The transmission of data processing equipment 440 first is responded to data generating apparatus 420；
Step 504：In response to first response, data generating apparatus 420 generate the first data and by the first data storage in
In memory 422；
Step 506：The transmission of data processing equipment 440 second is responded to data generating apparatus 420；And
Step 508：In response to the second response, data generating apparatus 420 transmits the first data being stored in memory 422
To data processing equipment 440.
Step 510：Data processing equipment 440 is by the first data storage in memory 444.
Fig. 6 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.Semiconductor test side shown in Fig. 6
Method may correspond to one of semiconductor test system shown in Fig. 2, Fig. 4, Fig. 7 and Fig. 9 part operation step.In order to illustrate side
Just, it is now illustrated by taking the semiconductor test system 200 shown in Fig. 2 as an example.
As shown in fig. 6, the semiconductor test method of the present embodiment includes the following steps：
Step 602：Data processing equipment 240 handles the second data from data generating apparatus 220 and generates the second life
It enables；
Step 604：Data test device 260 completes the test according to the first order；
Step 606：Data test device 260 transmits third and responds to data processing equipment 240；
Step 608：The transmission of data processing equipment 240 second is ordered to data test device 260；And
Step 610：Data test device 260 carries out the test according to the second order.
It is noted that in this embodiment, step 602 is in must be earlier than step 606, thus, in number on the time
Before the test according to the first order is completed according to test device 260, data processing equipment 240 has just completed the processing of the second data
And the second order is generated.In this way, data test device 260 carry out multiple tests can without interruption continue into
Row is greatly decreased and links up the spent stand-by period in semiconductor test system between software and hardware.
Fig. 7 is painted the schematic diagram of the semiconductor test system 700 of one embodiment of the invention.As shown in fig. 7, semiconductor test
System 700 includes data generating apparatus 720, data processing equipment 740 and data test device 760.Data generating apparatus 720,
Data processing equipment 740 and data test device 760 have the electrical connection that can transmit signal and instruction to each other.Test system
780 are installed on data test device 760.Data processing equipment 740 is comprising in processor 742, the first memory 744 and second
Deposit 746.
In this embodiment, the test data for passing through coding is sent to data processing equipment by data generating apparatus 720
740.After data processing equipment 740 has received encoded test data, first it is stored in the first memory 744.In warp knit
The test data of code is stored to the first memory 744, and data processing equipment 740 can return a response to data generating apparatus
720, data generating apparatus 720 is made to generate next record test data.The processor 742 of data processing equipment 740 can will be stored in
Test data in first memory 744 handles generation test command into row decoding.The test command of generation can be stored to second
In memory 746.Data processing equipment 740 can transmit a response to data generating apparatus 720 at this time, make data generating apparatus 720
The encoded test data of next record is transmitted to data processing equipment 740 and is stored in the first memory 744.
Whenever completing a test, data test device 760 can transmit a response to data processing equipment 740, then count
The test command being stored in the second memory 746 is just sent to data test device 760 according to processing unit 740.In second
It deposits the test command in 746 to be sent to after data test device 760, data processing equipment 740 will be stored in the first memory 744
In test data into row decoding, and handle generate next record test command.The next record test command of generation can be stored to
In two memories 746.
Fig. 8 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.Semiconductor test side shown in Fig. 8
Method corresponds to one of the semiconductor test system 700 shown in Fig. 7 part operation step.As shown in figure 8, the present embodiment is partly led
Body examination method for testing includes the following steps：
Step 802：The first data for passing through coding are sent to data processing equipment 740, data by data generating apparatus 720
Processing unit 740 is by the first encoded data storage in the first memory 744；
Step 804：First response of the transmission of data processing equipment 740 makes data generating apparatus to data generating apparatus 720
720 generate the second encoded data；
Step 806：Data processing equipment 740 decodes the first encoded data, and processing generates the first order and by first
Order is stored in the second memory 746；
Step 808：Second response of the transmission of data processing equipment 740 makes data generating apparatus to data generating apparatus 720
The second encoded data are transmitted to data processing equipment 740 and are stored in the first memory 744 by 720；And
Step 810：Data test device 760 transmits third and responds to data processing equipment 740, makes data processing equipment
First order is sent to data test device 760 by 740.
It is noted that in this embodiment, data generating apparatus 720 completes current survey in data test device 760
Before examination order, the data of next record test are just sent to data processing equipment 740 and are stored in the first memory.And number
Before completing current test command in data test device 760 according to processing unit 740, just decode and generated next record test
Order and be stored in the second memory.In this way, whenever data test device 760 completes a test, one response of passback
The order of next record test can be obtained after to data processing equipment 740 immediately.Therefore, multiple tests of progress can not be interrupted
Ground persistently carries out, and is greatly decreased and links up the spent stand-by period in semiconductor test system between software and hardware.
Fig. 9 is painted the schematic diagram of the semiconductor test system of one embodiment of the invention.As shown in figure 9, semiconductor test system
System 900 includes data generating apparatus 920, data processing equipment 940 and data test device 960.Data generating apparatus 920, number
There is the electrical connection that can transmit signal and instruction to each other according to processing unit 940 and data test device 960.Test system
980 are installed on data test device 960.Data processing equipment 940 includes processor 942, memory 944 and buffer 946.
In this embodiment, the test data for passing through coding is sent to data processing equipment by data generating apparatus 920
940.After data processing equipment 940 has received encoded test data, first it is stored in memory 944.Work as data processing
Device 940 receives the response of one of data test device 960, informs after having completed currently to test, 940 part of data processing equipment
Device 942 is managed by the test data being stored in memory 944 into row decoding, and simultaneously via 946 synchronous driving of buffer to data
Test device 960.Also that is, data processing equipment 940 is not required to the next record test command of generation being stored in memory.It can save
Save the memory usage amount of data processing equipment 940.
Figure 10 is painted the schematic diagram of the semiconductor test method of one embodiment of the invention.Semiconductor test shown in Figure 10
Method corresponds to one of the semiconductor test system 900 shown in Fig. 9 part operation step.As shown in Figure 10, the present embodiment it
Semiconductor test method includes the following steps：
Step 1002：The test data for passing through coding is sent to data processing equipment 940 by data generating apparatus 920；
Step 1004：Encoded test data is stored in memory 944 by data processing equipment 940；
Step 1006：The transmission of data test device 960 one is responded to data processing equipment 940；
Step 1008：Test data decoding encoded in memory 944 is generated test command by data processing equipment 940,
And via 946 synchronous driving of buffer to data test device 960.
Although the specific embodiment for having referred to the present invention describes and illustrates the present invention, these descriptions and explanation are not intended to limit
The present invention.Those who familiarize themselves with the technology should be understood that in the true essence for not departing from the present invention such as defined by appended claim
In the case of refreshing and scope, it can be variously modified and available equivalents replace.This specification and schema should be considered as illustrative
And not restrictive.It can modify, so that particular condition, method or component are adapted to the target of the present invention, spirit and scope.
All such modifications are intended in the scope of the claim in accompanying herein.Although referring to being performed in a specific order
Specific operation method disclosed herein is described, it should be appreciated that do not depart from the present invention teaching in the case of, can group
These operations are closed, divide again or re-sequenced to form equivalent method.Therefore, unless specific instruction herein, otherwise operates time
The limitation of sequence and grouping not to the present invention.
Claims (14)
1. a kind of system for testing semiconductor subassembly, it includes：
One data generating apparatus；
One data test device；And
One data processing equipment, the data processing equipment, which is configured to transmission one first, orders to the data test device simultaneously
Transmission one first is responded to the data generating apparatus after first order is transmitted,
Wherein after first response is received, data generating apparatus transmission one first data to the data processing fills
It puts.
2. system according to claim 1, wherein wherein described data processing equipment includes：
One processor；And
One first memory；
The processor is configured to handle first data and generates one second order, and by the described second order storage extremely
In first memory.
3. system according to claim 2, wherein the data generating apparatus is responded in response to described first to generate
State the first data.
4. system according to claim 2, wherein the data generating apparatus is in response to coming from the data processing equipment
One of the second response first data are sent to the data processing equipment.
5. system according to claim 4, wherein the data processing equipment be configured in response to a third respond with
Second order that will be stored in first memory is sent to the data test device.
6. system according to claim 5, wherein the data processing equipment that is transmitted in of first data receives institute
It states before third is responded and completes.
7. system according to claim 2, wherein
The data processing equipment further includes a buffer；And
The data processing equipment is configured to respond in response to a third, by described the being handled first data Tong Shi
Two orders are sent to the data test device via the cache synchronization.
8. system according to claim 2, wherein the data processing equipment further includes：
One second memory, wherein
The data processing equipment is configured to transmitting first response to before the data generating apparatus, by described the
Two orders are transferred to from first memory in second memory.
9. system according to claim 8 is incited somebody to action wherein the data processing equipment is configured to respond in response to a third
Second order being stored in second memory is sent to the data test device.
10. a kind of method for testing semiconductor subassembly, it includes:
One data generating apparatus is provided；
One data processing equipment is provided；And
One data test device is provided；
One first order is transmitted at the first time to the data test device one by the data processing equipment, makes the data
Test device is tested according to the described first order；
After the described first order is sent to the data test device, one first response of data processing equipment transmission to institute
State data generating apparatus；
The data generating apparatus is according to the first response one first data of transmission received to the data processing equipment.
11. according to the method described in claim 10, it is further included handles first number by the data processing equipment
According to and generate one second order.
12. according to the method described in claim 10, wherein
The data generating apparatus generates first data, and in response to coming from the data in response to the described first response
First data are sent to the data processing equipment by the response of one of processing unit second.
13. according to the method for claim 11, wherein the data processing equipment is responded in response to a third, in processing institute
That states the first data is sent to the data test device by second command synchronization simultaneously.
14. according to the method for claim 13, wherein the data processing equipment that is transmitted in of first data receives
The third is completed before responding.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105143111A TWI637177B (en) | 2016-12-23 | 2016-12-23 | System and method for testing semiconductor elements |
| TW105143111 | 2016-12-23 |
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| Publication Number | Publication Date |
|---|---|
| CN108241117A true CN108241117A (en) | 2018-07-03 |
| CN108241117B CN108241117B (en) | 2021-02-05 |
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| CN201710062839.1A Active CN108241117B (en) | 2016-12-23 | 2017-01-26 | System and method for testing semiconductor devices |
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| CN111856246A (en) * | 2020-07-13 | 2020-10-30 | 胜达克半导体科技(上海)有限公司 | High-speed synchronous trigger bus circuit and synchronous trigger method |
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| TW201823743A (en) | 2018-07-01 |
| CN108241117B (en) | 2021-02-05 |
| TWI637177B (en) | 2018-10-01 |
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