CN116340073B - Test method, device and system - Google Patents

Test method, device and system Download PDF

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Publication number
CN116340073B
CN116340073B CN202310602971.2A CN202310602971A CN116340073B CN 116340073 B CN116340073 B CN 116340073B CN 202310602971 A CN202310602971 A CN 202310602971A CN 116340073 B CN116340073 B CN 116340073B
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signal
tested
server
test
module
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CN116340073A (en
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赵肖
陈金龙
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application discloses a testing method, a testing device and a testing system, which relate to the technical field of servers and can reduce testing cost. The test device comprises: the AirMax connector is used for acquiring sideband signals from a server to be tested; the Expmax connector is used for acquiring a clock signal and a target signal from a server to be tested; the control unit is used for determining and transmitting the first timing signal to the first interface group according to the sideband signal; the first interface group is used for determining a first signal to be tested according to the first test signal, the first timing signal and the clock signal; the hard disk module is used for carrying out hard disk signal conversion based on a high-speed serial computer expansion bus standard protocol on the second test signal to obtain a second signal to be tested; the Examax connector is further used for sending the first signal to be tested and the second signal to be tested to the server to enable the server to be tested to determine a test result aiming at the first communication link.

Description

Test method, device and system
Technical Field
The present application relates to the field of server technologies, and in particular, to a testing method, device, and system.
Background
To ensure quality and performance of the server, testing is required before shipping for the communication link between the server and the graphics processor BOX (Graphics Processing Unit BOX, GPU BOX), mainly the communication link of the high speed serial computer expansion bus standard signal.
In the related art, a real GPU BOX module is mainly used for testing, but the cost of the GPU BOX is high due to high cost and easy damage, so that the testing cost is high.
Disclosure of Invention
The embodiment of the application aims to provide a testing method, a testing device and a testing system, which can reduce testing cost.
In order to solve the above technical problems, in a first aspect, an embodiment of the present application provides a testing device, which includes a control unit and a testing unit, where the testing unit includes an exomax connector and an AirMax connector for externally connecting a server to be tested, a first interface group and a hard disk module, the exomax connector is connected with the first interface group and the hard disk module, the AirMax connector is connected with the control unit, and the first interface group is connected with the control unit, where:
the AirMax connector is used for acquiring sideband signals from a server to be tested;
the Expmax connector is used for acquiring a clock signal and a target signal from a server to be tested, wherein the target signal comprises: a first test signal corresponding to the x 16-level high-speed serial computer expansion bus standard signal and a second test signal corresponding to the x 2-level high-speed serial computer expansion bus standard signal;
the control unit is used for determining a first timing signal according to the sideband signal and sending the first timing signal to the first interface group;
The first interface group is used for determining a first signal to be tested according to the first test signal, the first timing signal and the clock signal;
the hard disk module is used for carrying out hard disk signal conversion based on a high-speed serial computer expansion bus standard protocol on the second test signal to obtain a second signal to be tested;
the Expmax connector is also used for sending a first signal to be tested and a second signal to be tested to the server to enable the server to be tested to determine a test result aiming at a first communication link, wherein the first communication link is a communication link used for transmitting a high-speed serial computer expansion bus standard signal.
Optionally, the test device further includes a clock buffer module, and the control unit, the exomax connector and the first interface group are respectively connected with the clock buffer module, wherein:
the control unit is also used for sending a control enabling signal to the clock buffer module;
the clock buffer module is used for carrying out multipath clock signal expansion on the clock signal sent by the Expmax connector when receiving the control enabling signal, and respectively sending the clock signal to each interface in the first interface group.
Optionally, the control unit is further configured to send a control enable signal to the clock buffer module when the testing device is powered on and it is determined that the voltage of the server under test is normal.
Optionally, the first interface group is further configured to connect to a high-speed serial computer expansion bus standard signal device, input the first test signal, the first timing signal, and the clock signal to the high-speed serial computer expansion bus standard signal device, and determine a state of the high-speed serial computer expansion bus standard signal device as the first signal to be tested.
Optionally, the control unit is further configured to determine a test result for a second communication link according to the sideband signal, where the second communication link is a communication link for transmitting the sideband signal.
Optionally, the test unit further comprises a sensor module, the Examax connector being connected to the sensor module, wherein:
the sensor module is further configured to perform inter-integrated circuit signal transmission with the server to be tested via the exomax connector, so that the server to be tested determines a test result for a third communication link, where the third communication link is a communication link for transmitting inter-integrated circuit signals.
Optionally, the sensor module includes a plurality of independent sensors, one for transmitting an inter-integrated circuit signal with the server under test.
Optionally, the test unit further comprises a first universal serial bus module, the Examax connector is connected with the first universal serial bus module, the first universal serial bus module is connected with the control unit, wherein:
The Expmax connector is also used for acquiring a third test signal corresponding to the universal serial bus signal from the server to be tested;
the first universal serial bus module is used for carrying out universal asynchronous receiver-transmitter signal conversion on the third test signal to obtain a third signal to be tested;
the control unit is further configured to determine a test result for a fourth communication link according to the third signal to be tested, where the fourth communication link is a communication link for transmitting signals of the universal asynchronous receiver/transmitter.
Optionally, the device further includes a power supply interface and a voltage signal processing module, the power supply interface is used for being externally connected with the server to be tested, the power supply interface is connected with the voltage signal processing module, and the voltage signal processing module is connected with the control unit, wherein:
the power supply interface is used for acquiring the voltage of the server to be tested;
the voltage signal processing module is used for determining voltage information according to the voltage;
the control unit is used for determining a test result of the voltage of the server to be tested according to the voltage information.
Optionally, the device further comprises a power supply module, the power supply interface is connected with the power supply module, wherein:
the power supply module is also used for carrying out step-down processing on the voltage of the server to be tested and supplying power to the testing device.
Optionally, the device further comprises a second universal serial bus module and a first universal serial bus interface, the control unit is connected with the second universal serial bus module, and the second universal serial bus module is connected with the first universal serial bus interface, wherein:
the control unit is further configured to send a first universal asynchronous receiver-transmitter signal indicating a test result to the second universal serial bus module;
the second universal serial bus module is used for converting the first universal asynchronous receiver-transmitter signal into a first universal serial bus signal and transmitting the first universal serial bus signal to the first universal serial bus interface;
the first universal serial bus interface is used for outputting a test result according to the first universal serial bus signal.
Optionally, the control unit is further configured to send a first universal asynchronous receiver signal indicating a test result characterizing the anomaly to the second universal serial bus module if the test result characterizing the anomaly is determined.
Optionally, the control unit is further configured to generate a second timing signal according to a signal simulation rule, and send the second timing signal to the server to be tested, where the second timing signal is used to simulate a timing signal that needs to be sent by the server to be tested when the graphics processor box works.
Optionally, the device further includes a third universal serial bus module and a second universal serial bus interface, the control unit is connected with the third universal serial bus module, and the third universal serial bus module is connected with the second universal serial bus interface, wherein:
the second universal serial bus interface is used for sending a second universal serial bus signal indicating a new signal simulation rule to the third universal serial bus module;
the third universal serial bus module is used for converting the second universal serial bus signal into a second universal asynchronous transceiver signal and transmitting the second universal asynchronous transceiver signal to the control unit;
the control unit is used for adjusting the signal simulation rule of the control unit according to the signal of the second general asynchronous transceiver.
Optionally, the control unit is further configured to control the testing device to stop working when determining a test result indicating an abnormality.
Optionally, the control unit is configured to stop sending a third timing signal to the server to be tested when determining the test result characterizing the abnormality, where the third timing signal is used to simulate a timing signal that needs to be sent by the server to be tested when the graphics processor box works.
In a second aspect, an embodiment of the present application further provides a test system, where the test system includes a motherboard of a server to be tested, and a test device as described in the first aspect, and the motherboard of the server to be tested is connected to the test device.
Optionally, the test system further includes an exchange board of the server to be tested, the main board of the server to be tested is connected with the exchange board of the server to be tested, and the exchange board of the server to be tested is connected with the test device.
In a third aspect, an embodiment of the present application further provides a testing method applied to the control unit in the testing device according to the first aspect, where the method includes:
after the test device is electrified, detecting whether the voltage of the server to be tested is normal or not;
under the condition that the voltage of the server to be tested is normal, a control enabling signal is sent to a clock buffer module in the testing device, a first timing signal is determined and sent to each interface in a first interface group in the testing device according to a sideband signal sent by the server to be tested, the control enabling signal is used for enabling the clock buffer module to carry out multipath clock signal expansion on the clock signal sent by the server to be tested, and clock signals are sent to each interface in the first interface group;
and under the condition that the voltage of the server to be tested is abnormal, determining a test result representing the voltage abnormality of the server to be tested.
Optionally, the method further comprises:
after the test device is powered on, generating a second time sequence signal according to a signal simulation rule;
And sending a second time sequence signal to the server to be tested, wherein the second time sequence signal is used for simulating the time sequence signal which is required to be sent by the server to be tested when the graphics processor box works.
Optionally, the method further comprises:
and determining a test result for a second communication link according to the sideband signal, wherein the second communication link is a communication link for transmitting the sideband signal.
Optionally, the method further comprises:
acquiring a third to-be-tested signal determined by a first universal serial bus module in the testing device, wherein the third to-be-tested signal is determined by the first universal serial bus module according to a universal serial bus signal sent by a to-be-tested server;
and determining a test result aiming at a fourth communication link according to the third signal to be tested, wherein the fourth communication link is a communication link for transmitting the universal asynchronous receiver-transmitter signal.
Optionally, the method further comprises:
acquiring a fourth signal to be tested determined by a first universal serial bus module in the testing device, wherein the fourth signal to be tested is determined by the first universal serial bus module according to a fourth signal sent by a server to be tested, and the fourth signal is a universal serial bus signal;
determining a test result for a fourth communication link according to a fourth signal to be tested, wherein the fourth communication link is a communication link used for transmitting universal serial bus signals between the server to be tested and the graphics processor box
Optionally, the method further comprises:
and under the condition that the testing result representing the abnormality is determined, sending the testing result representing the abnormality to the server to be tested.
Optionally, the method further comprises:
and under the condition that the test result representing the abnormality is determined, controlling the test device to stop working.
According to the technical scheme, the testing device is connected with the server to be tested through the Expmax connector and the AirMax connector, the defect of high damage rate of the GPU BOX caused by short service life of the interface plug can be overcome, the testing device is more suitable for a server testing scene with high-frequency plug, the testing device obtains a testing related signal of the server to be tested through the testing unit, and a time sequence required by the operation of the testing unit is provided through the control unit, so that the testing device can replace the GPU BOX module to realize testing of a bus standard signal communication link of a high-speed serial computer, and the testing cost is effectively reduced.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a conventional test scheme provided by an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a testing device according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of another testing device according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a test scheme according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a test system according to an embodiment of the present application;
FIG. 6 is a flowchart of a test method according to an embodiment of the present application;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the present application;
fig. 8 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
The terms "comprising" and "having" and any variations thereof in the description and claims of the application and in the foregoing drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may include other steps or elements not expressly listed.
Servers can be currently classified into various servers such as a computing server and a storage server. For a compute-based server, a graphics processor (Graphics Processing Unit, GPU) is a necessary device for a high-end compute-based server (e.g., delta-Next server). In order to ensure the quality and performance of such a server configured with a GPU, the communication link with the GPU BOX module needs to be tested for its normality before the server leaves the factory.
At present, the factory test is carried out by using a real GPU BOX module, because the GPU BOX is noble, the number of times of plugging and unplugging the interface is limited, and under the condition that the server manufacturing end carries out a large number of tests by using the GPU BOX, the damage rate of the GPU BOX is higher, so that the test cost is improved.
In the conventional test scheme, as shown in fig. 1, the test target of the server product is a server motherboard and a Switch board (Switch board) matched with the server motherboard, and in order to realize the test of a communication link between the server motherboard end and the GPU BOX, to determine whether the related functions of the server motherboard are normal, a GPU board (including a plurality of GPUs) needs to be added as a companion test part (i.e., a companion test tool), so that the value of the companion test tool is far greater than that of the tested board, and the whole companion test part needs to be frequently plugged and pulled out to replace the server motherboard to be tested in the process of testing the plurality of server motherboards, and the service life of the GPU board is only tens of times due to the fact that the GPU interface is damaged due to the frequent plugging and pulling out, so that the function of the GPU board is abnormal or even damaged, and the product test cost is seriously affected.
In order to solve the problems in the related art, the application provides a testing device and a testing scheme for replacing a GPU BOX, which can reduce the testing cost.
The following describes in detail a testing device provided by the embodiment of the present application through some embodiments and application scenarios thereof with reference to the accompanying drawings.
In a first aspect, referring to fig. 2, a schematic structural diagram of a test device according to an embodiment of the present application is provided, where the test device includes a control unit and a test unit, the test unit includes an exomax connector and an AirMax connector for connecting a server to be tested, a first interface group and a hard disk module, the exomax connector is connected to the first interface group and the hard disk module, the AirMax connector is connected to the control unit, and the first interface group is connected to the control unit, where:
the AirMax connector is used for acquiring sideband signals from a server to be tested;
the Expmax connector is used for acquiring a clock signal and a target signal from a server to be tested, wherein the target signal comprises: a first test signal corresponding to the x 16-level high-speed serial computer expansion bus standard signal and a second test signal corresponding to the x 2-level high-speed serial computer expansion bus standard signal;
The control unit is used for determining a first timing signal according to the sideband signal and sending the first timing signal to the first interface group;
the first interface group is used for determining a first signal to be tested according to the first test signal, the first timing signal and the clock signal;
the hard disk module is used for carrying out hard disk signal conversion based on a high-speed serial computer expansion bus standard protocol on the second test signal to obtain a second signal to be tested;
the Expmax connector is also used for sending a first signal to be tested and a second signal to be tested to the server to enable the server to be tested to determine a test result aiming at a first communication link, wherein the first communication link is a communication link used for transmitting a high-speed serial computer expansion bus standard signal.
In this embodiment, the test device is connected to the server to be tested (the server to be tested at least includes a server motherboard and may also include a board-matched board), through a connector module formed by an Examax connector and an AirMax connector, for example, the connector module may be directly connected to the board of the server to be tested, or may be connected to the board through the board-matched board of the server to be tested.
The connector module includes a plurality of connectors that mate with the server interface to be tested. For example, the connector module may include a 6x8 Examax connector, a 4x8 Examax connector, and an AirMax connector. The number of various connectors included in the connector module may be determined according to the GPU BOX configuration (e.g., the number of GPU nodes in the GPU BOX) supported by the server to be tested, e.g., the connector module may include 1 6x8 Examax connector, 5 4x8 Examax connector, and 4 AirMax connector.
Wherein the 6x8 exomax connector is capable of transmitting high speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) signals, clock signals (CLK signals), inter-Integrated Circuit, I2C signals, and universal serial bus (Universal Serial Bus, USB) signals; the 4x8 Examax connector is capable of transmitting PCIE signals; the AirMax connector is capable of transmitting a sideband signal, which is a signal obtained by modulating a baseband signal according to a certain rule.
Taking a connector module including 16×8 Examax connector, 7 4×8 Examax connectors and 4 AirMax connectors as an example, at this time, a PCIE communication link between the testing device and the server to be tested may be used to transmit 8 sets of x16 PCIE signals, that is, an uplink 8 sets of x16 PCIE signals are connected to the server to be tested through the Examax connectors, a downlink 8 sets of x16 PCIE signals are respectively connected to each interface of the first interface set (that is, PCIE x16 slots of the board card), and the AirMax connectors send sideband signals sent by the server to be tested to the control unit.
The control unit may be a programmable control device such as a micro control unit (Microcontroller Unit, MCU) or a programmable system on chip (PSoC), and the control unit determines a first timing signal according to a data signal, a clock signal and other signals included in the sideband signal, and sends the first timing signal to each interface of the first interface group to provide timing information related to a PCIE signal, and the first interface group then detects a downlink 8-group x16 PCIE signal sent by the server to be tested according to the first test signal, the first timing signal and the clock signal sent by the server to be tested acquired by the Examax connector, so as to obtain a first signal to be tested, thereby implementing PCIE x16 signal transmission simulation from the server to the GPU BOX, and ensuring detectability of a communication link of the PCIE x16 signal. The server to be tested may then detect whether the first test signal corresponds to the x16 PCIE signal, for example, the first test signal actually obtained by the Examax connector is the x8 PCIE signal due to a communication link failure of the PCIE x16 signal, and then the testing device may use the x8 PCIE signal as the first signal to be tested, or use a signal corresponding to the x8 PCIE signal (e.g., a PCIE signal representing a status of the PCIE device externally connected to the first interface group) as the first signal to be tested, and return the first signal to the server to be tested, where the server to be tested may know that the communication link of the PCIE x16 signal is abnormal.
In order to simulate PCIE x2 signal transmission from the server to be tested to the GPU BOX, the testing device converts the second testing signal obtained by the Expmax connector into a hard disk signal (namely a second signal to be tested) through a hard disk module (such as a PCIE M.2 hard disk) based on PCIE protocol, so as to detect whether the PCIE x2 signal can be normally transmitted between the server to be tested and the testing server, further reduce the testing cost and ensure the detectability of a communication link of the PCIE x2 signal. Because the PCIE communication link between the server to be tested and the GPU BOX is mainly used for transmitting PCIE x2 signals and PCIE x16 signals, coverage test of the PCIE communication link between the server to be tested and the GPU BOX can be implemented according to the first signal to be tested and the second signal to be tested detected by the testing device.
As a possible implementation manner, the first interface group is further configured to connect to a high-speed serial computer expansion bus standard signaling device (PCIE device), input a first test signal, a first timing signal, and a clock signal to the PCIE device, and determine a state of the PCIE device as a first signal to be tested.
In this embodiment, the PCIE device may include a low-value PCIE card for inserting into each PCIE x16 slot, and the server to be tested may detect whether the state of each low-value PCIE card is normal (i.e. whether the PCIE x16 signal is normally acquired), and determine that the communication link function of the PCIE x16 signal between the server to be tested and the GPU BOX is normal under the condition that the state of each low-value PCIE card is normal.
It should be noted that, the GPU BOX is a complete machine equipment of a GPU, which includes a plurality of GPU nodes, and a configuration and measurement tool made based on the GPU BOX is connected with a server to be tested through a GPU high-density interface, so that functional abnormality or damage is easy to occur due to frequent plugging and unplugging. The service lives of the Examax connector and the AirMax connector are relatively long (for example, the Examax connector can be plugged and unplugged for more than 500 times), so that the conditions of abnormal functions or damage of the testing device and the accompanying testing tool comprising the testing device caused by frequent plugging and unplugging can be effectively reduced.
According to the technical scheme, the testing device is connected with the server to be tested through the Expmax connector and the AirMax connector, the defect of high damage rate of the GPU BOX caused by short service life of the interface plug can be overcome, the testing device is more suitable for a server testing scene with high-frequency plug, the testing device obtains a testing related signal of the server to be tested through the testing unit, and a time sequence required by the operation of the testing unit is provided through the control unit, so that the testing device can replace the GPU BOX module to realize testing of a bus standard signal communication link of a high-speed serial computer, and the testing cost is effectively reduced.
Optionally, in one embodiment, as shown in fig. 3, to ensure that the clock signal is normally provided to each interface in the first interface group, the test apparatus further includes a clock buffer module, and the control unit, the exomax connector and the first interface group are respectively connected to the clock buffer module, where:
the control unit is also used for sending a control enabling signal to the clock buffer module;
the clock buffer module is used for carrying out multipath clock signal expansion on the clock signal sent by the Expmax connector when receiving the control enabling signal, and respectively sending the clock signal to each interface in the first interface group.
In this embodiment, the clock buffer module expands the clock signals acquired by the exomax connector into a plurality of sets of clock signals equal to the number of interfaces in the first interface set, thereby providing a clock signal for each interface in the first interface set.
As a possible implementation manner, the control unit is further configured to send a control enable signal to the clock buffer module when the test device is powered on and it is determined that the voltage of the server under test is normal.
In this embodiment, as shown in fig. 4, after the test device is powered on, the control unit may detect whether the voltage of the server to be tested is normal, for example, the server to be tested may send a message indicating that the states of the voltage points of the server to be tested are normal to the control unit, or the control unit tests the voltage of the server to be tested, and after determining that the voltage of the server to be tested is normal, the control unit sends a control enabling signal to the clock buffer module, so that the clock buffer module provides a clock signal for the test device (such as the first interface group), thereby ensuring the reliability of the test result determined by the control unit and directed against the first communication link.
In order to realize the voltage test of the control unit to the server to be tested, the testing device can further comprise a power supply interface and a voltage signal processing module, wherein the power supply interface is used for being externally connected with the server to be tested, the power supply interface is connected with the voltage signal processing module, and the voltage signal processing module is connected with the control unit, wherein:
the power supply interface is used for acquiring the voltage of the server to be tested;
the voltage signal processing module is used for determining voltage information according to the voltage;
the control unit is used for determining a test result of the voltage of the server to be tested according to the voltage information.
In this embodiment, the power supply interface may include a set number of PwrMax connectors, the number of which is determined by the interface configuration of the server under test, e.g., the power supply interface may include 2 PwrMax connectors for acquiring the output voltage of the server under test. Considering that the output voltage of the server to be tested is generally higher, the voltage signal processing module can process the output voltage to obtain voltage information for the control unit to detect the voltage, for example, the voltage signal processing module can convert the 54V high voltage obtained by the power supply interface into a corresponding low level and input the corresponding low level to the control unit, and the control unit determines whether the server to be tested has abnormal voltage by detecting whether the low level accords with a preset value.
As a possible embodiment, the test device further comprises a power supply module, the power supply interface being connected to the power supply module, wherein: the power supply module is also used for carrying out step-down processing on the voltage of the server to be tested, for example, 54V voltage is converted into 12V voltage so as to supply power to the testing device.
In this embodiment, the testing device and other devices (such as PCIE devices) connected to the testing device may be powered by the server to be tested, and at this time, the control unit may use the voltage signal processing module to learn whether the power supply interface normally obtains the power supply voltage output by the server to be tested.
Optionally, in an embodiment, the control unit is further configured to generate a second timing signal according to a signal simulation rule, and send the second timing signal to the server to be tested, where the second timing signal is used to simulate a timing signal that needs to be sent to the server to be tested when the GPU BOX works.
In this embodiment, the control unit simulates GPU BOX timing signals (such as gpu_base_prsnt signal, gpu_base_ready signal, gpu_base_pwr_gd signal, and gpu_base_pwr_en, clk_en signal) according to a signal simulation rule, and simulates signals required to be fed back for triggering operation of a real GPU BOX, and feeds the simulated signals back to the server to be tested, so that the server to be tested can identify the testing device provided by the present application as the GPU BOX, and perform related signal transmission between the server to be tested and the GPU BOX.
Considering that the communication link between the server to be tested and the GPU BOX can also be used for transmitting sideband signals, I2C signals and USB signals, the testing device can also provide related communication link normality tests for the sideband signals, the I2C signals and the USB signals so as to realize function expansion of accompany testing tools.
Optionally, in an embodiment, the control unit is further configured to determine a test result for a second communication link based on the sideband signal, the second communication link being a communication link for transmitting the sideband signal.
In this embodiment, the control unit may detect, in addition to outputting the PCIE related timing signal according to the sideband signal, a signal form of the sideband signal, and so on, so as to implement a test on the second communication link between the server to be tested and the GPU BOX.
Optionally, in one embodiment, the test unit further comprises a sensor module, the Examax connector is connected to the sensor module, wherein:
the sensor module is further configured to transmit an inter-integrated circuit signal (I2C signal) with the server to be tested via the exomax connector, so that the server to be tested determines a test result for a third communication link, where the third communication link is a communication link for transmitting the inter-integrated circuit signal.
In this embodiment, the sensor module is configured to simulate the I2C device in the GPU BOX to perform I2C signal transmission with the server to be tested, for example, the sensor module may perform I2C signal transmission with the motherboard of the server to be tested through the Examax connector, so as to implement the detectability of the communication link of the I2C signal. Alternatively, the sensor module may include a plurality of independent sensors (such as a temperature sensor, a pressure sensor, etc.), where one sensor is used to transmit an inter-integrated circuit signal with the server to be tested, that is, each sensor may simulate an I2C signal receiving or transmitting action in the real GPU BOX.
Optionally, in one embodiment, the test unit may further comprise a first universal serial bus module (USB module), the Examax connector being connected to the first universal serial bus module, the first universal serial bus module being connected to the control unit, wherein:
the Expmax connector is also used for acquiring a third test signal corresponding to a universal serial bus signal (USB signal) from the server to be tested;
the first universal serial bus module is used for converting a third test signal into a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) signal to obtain a third signal to be tested;
The control unit is further configured to determine a test result for a fourth communication link according to the third signal to be tested, where the fourth communication link is a communication link for transmitting signals of the universal asynchronous receiver/transmitter.
In this embodiment, the USB module is configured to convert the USB signal into a UART signal that can be processed by the control unit, so that the control unit can test the transmission link of the USB signal for normal performance.
Considering that the USB module can be used for the mutual conversion between the USB signal and the UART signal, the control unit may perform test information interaction with external devices (such as a server to be tested, a client, etc.) through the USB module and the USB interface, so as to implement an automatic test.
Optionally, in one embodiment, the test device further includes a second universal serial bus module (USB module) and a first universal serial bus interface (USB interface), the control unit is connected to the second universal serial bus module, and the second universal serial bus module is connected to the first universal serial bus interface, wherein:
the control unit is further configured to send a first universal asynchronous receiver-transmitter signal indicating a test result to the second universal serial bus module;
the second universal serial bus module is used for converting the first universal asynchronous receiver-transmitter signal into a first universal serial bus signal and transmitting the first universal serial bus signal to the first universal serial bus interface;
The first universal serial bus interface is used for outputting a test result according to the first universal serial bus signal.
In this embodiment, the control unit may output the test result determined by the control unit, information of the detected related signal, and the like, through the Mini USB interface.
As a possible implementation manner, the control unit is further configured to send a first universal asynchronous receiver signal indicating a test result characterizing the anomaly to the second universal serial bus module in case the test result characterizing the anomaly is determined.
In this embodiment, if the control unit determines that a certain communication link is abnormal in the testing process, abnormal information is immediately output to the outside, for example, abnormal state information is immediately output to the server to be tested, so that the testing error information can be known and processed in time.
Optionally, in one embodiment, the test device further includes a third universal serial bus module (USB module) and a second universal serial bus interface (USB interface), the control unit is connected to the third universal serial bus module, and the third universal serial bus module is connected to the second universal serial bus interface, wherein:
The second universal serial bus interface is used for sending a second universal serial bus signal indicating a new signal simulation rule to the third universal serial bus module;
the third universal serial bus module is used for converting the second universal serial bus signal into a second universal asynchronous transceiver signal and transmitting the second universal asynchronous transceiver signal to the control unit;
the control unit is used for adjusting the signal simulation rule of the control unit according to the signal of the second general asynchronous transceiver.
In this embodiment, the control unit may output the detected information of the relevant signal to the outside through the USB interface, and the user may adjust the relevant signal of the GPU BOX required to be simulated by the control unit according to the information, correspondingly determine a new signal simulation rule, and write the new signal simulation rule into the control unit through the USB interface.
In order to force foolproof operation to leak test, the control unit can control the testing device to stop working when detecting the abnormal state of the test, namely, the control unit is also used for controlling the testing device to stop working under the condition that the testing result representing the abnormality is determined.
In the implementation, the control unit may power down the test device to control the test device to stop working when determining the test result characterizing the abnormality.
As a possible implementation manner, the control unit may be configured to stop sending the third timing signal to the server to be tested when the test result characterizing the abnormality is determined, where the third timing signal is used to simulate a timing signal that needs to be sent by the server to be tested when the graphics processor BOX works, and at this time, the server to be tested does not identify the control device as the GPU BOX to perform communication connection, so that the test is interrupted, that is, the test device stops working.
Based on the embodiment, the application realizes the link test between the substitute GPU BOX and the server to be tested by developing the low-value testing device, and can perform coverage test on PCIE link signals, voltage signals, I2C signals, sideband signals and the like, thereby realizing the link performance test from the server to the GPU without using a real GPU, and saving complicated work such as real GPU installation and unloading and the like by using a simple testing device under the condition of meeting the test coverage requirement, and effectively saving the testing cost of the server.
In a second aspect, referring to fig. 5, an embodiment of the present application provides a test system, where the test system includes a motherboard of a server to be tested and a test device as described in the first aspect, and the motherboard of the server to be tested is connected to the test device.
Optionally, the test system further includes an exchange board of the server to be tested, the main board of the server to be tested is connected with the exchange board of the server to be tested, and the exchange board of the server to be tested is connected with the test device.
According to the technical scheme, the testing device is connected with the server to be tested through the Expmax connector and the AirMax connector, the defect of high damage rate of the GPU BOX caused by short service life of the interface plug can be overcome, the testing device is more suitable for a server testing scene with high-frequency plug, the testing device obtains a testing related signal of the server to be tested through the testing unit, and a time sequence required by the operation of the testing unit is provided through the control unit, so that the testing device can replace the GPU BOX module to realize testing of a bus standard signal communication link of a high-speed serial computer, and the testing cost is effectively reduced.
In a third aspect, referring to fig. 6, a flowchart of an implementation of a testing method according to an embodiment of the present application, where the testing method is applied to a control unit in a testing device as disclosed in an embodiment of the first aspect, the method may include the following steps:
step S101: after the test device is electrified, detecting whether the voltage of the server to be tested is normal or not;
Step S102: under the condition that the voltage of the server to be tested is normal, a control enabling signal is sent to a clock buffer module in the testing device, a first timing signal is determined and sent to each interface in a first interface group in the testing device according to a sideband signal sent by the server to be tested, the control enabling signal is used for enabling the clock buffer module to carry out multipath clock signal expansion on the clock signal sent by the server to be tested, and clock signals are sent to each interface in the first interface group;
step S103: and under the condition that the voltage of the server to be tested is abnormal, determining a test result representing the voltage abnormality of the server to be tested.
For example, as shown in fig. 4, the test device is connected to the server to be tested, and the PCIE card is inserted into a PCIE slot in the test device. After the server to be tested is electrified, the testing device detects whether the server to be tested is electrified or not, and detects whether the states of all voltage points of the server to be tested are normal or not after the server to be tested is electrified.
And under the condition that the states of all voltage points of the server to be tested are abnormal, feeding back the abnormal conditions to the server to be tested, and then reporting the abnormal testing by the server to be tested.
Under the condition that the states of all voltage points of the server to be tested are normal, the control unit enables the clock buffer module to provide clock signals for PCIE slots and wait for time sequence triggering, under the condition of time sequence triggering, the control unit triggers time sequences for all PCIE slots and enables PCIE cards, then the server to be tested detects whether the states of the PCIE cards and the states of the hard disks in the hard disk module are abnormal, and under the condition that the states of the PCIE cards and the states of the hard disks are normal, the report test is normal.
The power supply interface can acquire output voltage of the server to be tested, the voltage signal processing module processes the output voltage to obtain voltage information for the control unit to detect voltage, for example, the voltage signal processing module can convert standard voltage (such as 54V high voltage) acquired by the power supply interface into corresponding low-level information (such as 0) and input the low-level information into the control unit, convert non-54V high voltage acquired by the power supply interface into corresponding high-level information (such as 1) and input the high-level information into the control unit, and the control unit can judge that the server to be tested has abnormal voltage when receiving non-0 level.
As a possible implementation manner, the method further comprises:
after the test device is powered on, generating a second time sequence signal according to a signal simulation rule;
and sending a second time sequence signal to the server to be tested, wherein the second time sequence signal is used for simulating the time sequence signal which is required to be sent by the server to be tested when the graphics processor box works.
As a possible implementation manner, the method further comprises:
and determining a test result for a second communication link according to the sideband signal, wherein the second communication link is a communication link for transmitting the sideband signal.
As a possible implementation manner, the method further comprises:
acquiring a third to-be-tested signal determined by a first universal serial bus module in the testing device, wherein the third to-be-tested signal is determined by the first universal serial bus module according to a universal serial bus signal sent by a to-be-tested server;
and determining a test result aiming at a fourth communication link according to the third signal to be tested, wherein the fourth communication link is a communication link for transmitting universal serial bus signals.
As a possible implementation manner, the method further comprises:
and under the condition that the testing result representing the abnormality is determined, sending the testing result representing the abnormality to the server to be tested.
As a possible implementation manner, the method further comprises:
and under the condition that the test result representing the abnormality is determined, controlling the test device to stop working.
According to the technical scheme, the testing device is connected with the server to be tested through the Expmax connector and the AirMax connector, the defect of high damage rate of the GPU BOX caused by short service life of the interface plug can be overcome, the testing device is more suitable for a server testing scene with high-frequency plug, the testing device obtains a testing related signal of the server to be tested through the testing unit, and a time sequence required by the operation of the testing unit is provided through the control unit, so that the testing device can replace the GPU BOX module to realize testing of a bus standard signal communication link of a high-speed serial computer, and the testing cost is effectively reduced.
The embodiment of the application also provides an electronic device, and referring to fig. 7, fig. 7 is a schematic diagram of the electronic device according to the embodiment of the application. As shown in fig. 7, the electronic device 100 includes: the memory 110 and the processor 120 are connected through a bus communication, and the memory 110 and the processor 120 store a computer program which can run on the processor 120, so as to realize the steps in the test method disclosed by the embodiment of the application.
The embodiment of the application also provides a computer readable storage medium, referring to fig. 8, and fig. 8 is a schematic diagram of the computer readable storage medium according to the embodiment of the application. As shown in fig. 8, a computer readable storage medium 200 has stored thereon a computer program/instruction 210, which computer program/instruction 210, when executed by a processor, implements the steps of the test method as disclosed in embodiments of the application.
Embodiments of the present application also provide a computer program product comprising a computer program/instruction which, when executed by a processor, implements the steps of the test method as disclosed in the embodiments of the present application.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, systems, apparatus, storage media and program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail a testing method, apparatus and system provided by the present application, and specific examples have been provided herein to illustrate the principles and embodiments of the present application, the above examples being provided only to assist in understanding the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.

Claims (23)

1. The test device is characterized by comprising a control unit and a test unit, wherein the test unit comprises an Expmax connector, an AirMax connector, a first interface group and a hard disk module, wherein the Expmax connector is used for being externally connected with a server to be tested, the Expmax connector is respectively connected with the first interface group and the hard disk module, the AirMax connector is connected with the control unit, and the first interface group is connected with the control unit, wherein:
the AirMax connector is used for acquiring sideband signals from the server to be tested;
the Expmax connector is used for obtaining a clock signal and a target signal from the server to be tested, and the target signal comprises: a first test signal corresponding to the x 16-level high-speed serial computer expansion bus standard signal and a second test signal corresponding to the x 2-level high-speed serial computer expansion bus standard signal;
the control unit is used for determining a first time sequence signal according to the sideband signal and sending the first time sequence signal to the first interface group;
the first interface group is used for determining a first signal to be tested according to the first test signal, the first timing signal and the clock signal;
The hard disk module is used for carrying out hard disk signal conversion based on a high-speed serial computer expansion bus standard protocol on the second test signal to obtain a second signal to be tested;
the Expmax connector is also used for sending the first signal to be tested and the second signal to be tested to the server to be tested, so that the server to be tested determines a test result aiming at a first communication link, and the first communication link is a communication link used for transmitting a high-speed serial computer expansion bus standard signal;
the first interface group is further configured to connect to a high-speed serial computer expansion bus standard signal device, input the first test signal, the first timing signal, and the clock signal to the high-speed serial computer expansion bus standard signal device, and determine a state of the high-speed serial computer expansion bus standard signal device as the first signal to be tested.
2. The apparatus of claim 1, wherein the test apparatus further comprises a clock buffer module, the control unit, the exomax connector, and the first interface group are respectively connected to the clock buffer module, wherein:
The control unit is further configured to send a control enable signal to the clock buffer module;
the clock buffer module is used for performing multipath clock signal expansion on the clock signal sent by the Expmax connector when the control enabling signal is received, and respectively sending the clock signal to each interface in the first interface group.
3. The apparatus of claim 2, wherein the control unit is further configured to send the control enable signal to the clock buffer module when the test apparatus is powered up and it is determined that the voltage of the server under test is normal.
4. The apparatus of claim 1, wherein the control unit is further configured to determine a test result for a second communication link based on the sideband signal, the second communication link being a communication link for transmitting the sideband signal.
5. The apparatus of claim 1, wherein the test unit further comprises a sensor module, the Examax connector being connected to the sensor module, wherein:
the sensor module is further configured to perform inter-integrated circuit signal transmission with the server to be tested via the exomax connector, so that the server to be tested determines a test result for a third communication link, where the third communication link is a communication link for transmitting inter-integrated circuit signals.
6. The apparatus of claim 5, wherein said sensor module comprises a plurality of individual sensors, one of said sensors being configured to communicate an inter-integrated circuit signal with said server under test.
7. The apparatus of claim 1, wherein the test unit further comprises a first universal serial bus module, the Examax connector being coupled to the first universal serial bus module, the first universal serial bus module being coupled to the control unit, wherein:
the Expmax connector is also used for acquiring a third test signal corresponding to the universal serial bus signal from the server to be tested;
the first universal serial bus module is used for carrying out universal asynchronous receiver-transmitter signal conversion on the third test signal to obtain a third signal to be tested;
the control unit is further configured to determine a test result for a fourth communication link according to the third signal to be tested, where the fourth communication link is a communication link for transmitting signals of the universal asynchronous receiver/transmitter.
8. The apparatus of claim 1, wherein the testing apparatus further comprises a power supply interface and a voltage signal processing module, the power supply interface is configured to connect to the server under test, the power supply interface is connected to the voltage signal processing module, and the voltage signal processing module is connected to the control unit, wherein:
The power supply interface is used for acquiring the voltage of the server to be tested;
the voltage signal processing module is used for determining voltage information according to the voltage;
and the control unit is used for determining a test result of the voltage of the server to be tested according to the voltage information.
9. The apparatus of claim 8, wherein the test apparatus further comprises a power module, the power interface and the power module being connected, wherein:
the power supply module is also used for carrying out step-down processing on the voltage of the server to be tested and supplying power to the testing device.
10. The apparatus according to any one of claims 4, 7, 8 and 9, wherein the testing apparatus further comprises a second universal serial bus module and a first universal serial bus interface, the control unit being connected to the second universal serial bus module, the second universal serial bus module being connected to the first universal serial bus interface, wherein:
the control unit is further configured to send a first universal asynchronous receiver-transmitter signal indicating the test result to the second universal serial bus module;
the second universal serial bus module is used for converting the first universal asynchronous receiver-transmitter signal into a first universal serial bus signal and transmitting the first universal serial bus signal to the first universal serial bus interface;
The first universal serial bus interface is used for outputting the test result according to the first universal serial bus signal.
11. The apparatus of claim 10, wherein the control unit is further configured to send a first universal asynchronous receiver transmitter signal to the second universal serial bus module indicating the test result characterizing the anomaly if the test result characterizing the anomaly is determined.
12. The apparatus of claim 1, wherein the control unit is further configured to generate a second timing signal according to a signal simulation rule, and send the second timing signal to the server under test, where the second timing signal is used to simulate a timing signal that is required to be sent to the server under test when the graphics processor box is operating.
13. The apparatus of claim 12, wherein the test apparatus further comprises a third universal serial bus module and a second universal serial bus interface, the control unit being coupled to the third universal serial bus module, the third universal serial bus module being coupled to the second universal serial bus interface, wherein:
The second universal serial bus interface is used for sending a second universal serial bus signal indicating a new signal simulation rule to the third universal serial bus module;
the third universal serial bus module is configured to convert the second universal serial bus signal into a second universal asynchronous transceiver signal, and send the second universal asynchronous transceiver signal to the control unit;
the control unit is used for adjusting the signal simulation rule of the control unit according to the second general asynchronous transceiver signal.
14. The device according to any one of claims 4, 7, 8 and 9, wherein the control unit is further configured to control the testing device to stop operating in case a test result characterizing an abnormality is determined.
15. The apparatus according to claim 14, wherein the control unit is configured to stop sending a third timing signal to the server under test in case that a test result characterizing an abnormality is determined, the third timing signal being used to simulate a timing signal that is required to be sent to the server under test when the graphics processor box is operating.
16. A test system, comprising a motherboard of a server to be tested, and a test device according to any one of claims 1-15, wherein the motherboard of the server to be tested is connected to the test device.
17. The system of claim 16, wherein the test system further comprises a switch board of the server under test, the motherboard of the server under test being coupled to the switch board of the server under test, the switch board of the server under test being coupled to the test device.
18. A test method, characterized by a control unit for use in a test device according to any of claims 1-15, the method comprising:
after the test device is electrified, detecting whether the voltage of the server to be tested is normal or not;
under the condition that the voltage of the server to be tested is normal, a control enabling signal is sent to a clock buffer module in the testing device, a first timing signal is determined and sent to each interface in a first interface group in the testing device according to a sideband signal sent by the server to be tested, and the control enabling signal is used for enabling the clock buffer module to carry out multipath clock signal expansion on the clock signal sent by the server to be tested and respectively sending the clock signal to each interface in the first interface group;
and under the condition that the voltage of the server to be tested is abnormal, determining a test result representing the voltage abnormality of the server to be tested.
19. The method of claim 18, wherein the method further comprises:
after the test device is powered on, generating a second time sequence signal according to a signal simulation rule;
and sending the second time sequence signal to the server to be tested, wherein the second time sequence signal is used for simulating the time sequence signal which is required to be sent to the server to be tested when the graphics processor box works.
20. The method of claim 18, wherein the method further comprises:
and determining a test result for a second communication link according to the sideband signal, wherein the second communication link is a communication link for transmitting the sideband signal.
21. The method of claim 18, wherein the method further comprises:
acquiring a third signal to be tested determined by a first universal serial bus module in the testing device, wherein the third signal to be tested is determined by the first universal serial bus module according to a universal serial bus signal sent by the server to be tested;
and determining a test result aiming at a fourth communication link according to the third signal to be tested, wherein the fourth communication link is a communication link for transmitting universal serial bus signals.
22. The method according to any one of claims 18-21, further comprising:
and under the condition that the testing result representing the abnormality is determined, sending the testing result representing the abnormality to the server to be tested.
23. The method according to any one of claims 18-21, further comprising:
and under the condition that the test result representing the abnormality is determined, controlling the test device to stop working.
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