CN116662091A - Method, device, equipment and storage medium for detecting high-speed cable of server - Google Patents
Method, device, equipment and storage medium for detecting high-speed cable of server Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a method for detecting a high-speed cable of a server, and relates to the technical field of servers. The method comprises the steps that a first high-speed connector to be detected is determined from a plurality of first high-speed connectors through a main board BMC, and other first high-speed connectors are used as first candidate high-speed connectors; the main board CPLD sends detection signals through a plurality of first high-speed connectors respectively; the method comprises the steps that a main board BMC obtains detection signals received by a plurality of second high-speed connectors, and determines the second to-be-detected high-speed connectors connected with the first to-be-detected high-speed connectors corresponding to second identifiers according to the identifiers in the detection signals, so that a target connection relationship between the first to-be-detected high-speed connectors and the second to-be-detected high-speed connectors is obtained; and the main board BMC detects the target connection relation according to the preset connection relation. The method supports high-speed cable detection of all the daughter cards on the basis of general design, has higher expansibility, solves the signal crosstalk problem caused by PWM waves in the prior art, and reduces CPLD pins and corresponding resource use.
Description
Technical Field
The present application relates to the field of server technologies, and in particular, to a method, an apparatus, a device, and a storage medium for detecting a high-speed cable of a server.
Background
Along with the continuous acceleration of the progress of the informatization age, various types of products are continuously updated, and the demands of users on high-performance and high-configuration servers are increasing. Various cables are often used in server designs to match different backplanes to achieve more configuration requirements. One high-speed connector on the motherboard can be used for butting a plurality of backplanes. How to determine whether the high-speed connector is connected or not and whether the high-speed connector is connected correctly in the current configuration is a problem which must be considered in the technical field of servers.
The current technical scheme is divided into two parts of hardware and software design, wherein the hardware design comprises: two pins in the CPLD of the server motherboard are connected to the high-speed connector and are respectively used for sending and receiving PWM pulse signals; the server backboard CPLD loops back the pulse signal after receiving the PWM pulse signal sent by the main board CPLD; the server RISER card loops back the two pin shorts. The software design comprises: the CPLD of the server main board sends PWM waveforms with different duty ratios to different high-speed connectors, and if the PWM waveforms are received to return, the high-speed connectors are judged to be connected by cables; the CPLD of the back panel of the server detects the PWM duty cycle sent by the main board and determines the cable connection mode; the server BMC accesses the main board and the backboard CPLD through a protocol, and judges whether the current cable is inserted or not and whether the partial cable connection is correct or not.
However, for the board card without the CPLD, the server cannot confirm the connection mode of the high-speed cable, and if the cables are crossed by mistake during assembly, the sequence of IO may be affected. For different high-speed connectors, the motherboard CPLD needs to send PWM pulse signals with different duty cycles. Although the faster the PWM wave frequency is, the faster the back plate response is, but crosstalk exists for a long time to other signals in the server, and in order to improve the detection reliability, the larger the step duty ratio of the PWM wave is required, the better the step duty ratio is, and the communication efficiency of the server is affected.
Disclosure of Invention
The application provides a method, a device, equipment and a storage medium for detecting a high-speed cable of a server, which are used for solving the signal crosstalk problem caused by PWM waves in the prior art and reducing CPLD pins and corresponding resource use.
In one aspect, the present application provides a method for detecting a high-speed cable of a server, which is applied to hardware configuration based on a general design of the server, where the hardware configuration includes: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the motherboard CPLD and the motherboard BMC, the motherboard pins of the motherboard CPLD are connected with a plurality of first high-speed connectors, the plurality of server backplates and the at least one RISER card are respectively and correspondingly connected with a second high-speed connector, and the first high-speed connector and the second high-speed connector are connected through a high-speed cable, the method comprises the following steps:
The main board BMC determines a first high-speed connector to be detected from the plurality of first high-speed connectors, and takes other first high-speed connectors as first candidate high-speed connectors;
the main board CPLD respectively sends detection signals through the plurality of first high-speed connectors, wherein the identification of the detection signals sent by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals sent by the first high-speed connectors to be detected is a second identification;
the main board BMC acquires detection signals received by a plurality of second high-speed connectors, and determines a second to-be-detected high-speed connector connected with a first to-be-detected high-speed connector corresponding to a second identification according to the identification in the detection signals, so as to obtain a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector;
and the main board BMC detects the target connection relation according to a preset connection relation.
Optionally, before the motherboard BMC determines the first to-be-detected high-speed connector from the plurality of first high-speed connectors, the method further includes:
the main board BMC writes the detection time sequence into a main board CPLD register through protocols such as IIC and the like, and the CPLD outputs a corresponding detection time sequence;
The main board BMC determines a first to-be-detected high-speed connector from the plurality of first high-speed connectors, and comprises the following steps:
and the main board BMC determines a first to-be-detected high-speed connector from the plurality of first high-speed connectors according to the detection time sequence.
Optionally, the detection signal includes a high-low level signal, and the main board CPLD sends the detection signal through the plurality of first high-speed connectors respectively, including:
the main board CPLD sends a high-level signal through the first high-speed connector to be detected, and the mark of the high-level signal is a second mark;
and the main board CPLD transmits a low-level signal through a plurality of first candidate high-speed connectors, and the identification of the low-level signal is a first identification.
Optionally, the determining, according to the identifier in the detection signal, the second to-be-detected high-speed connector connected to the first to-be-detected high-speed connector corresponding to the second identifier includes:
determining a high-level signal identified as a second identifier from the high-level signal and the low-level signal, and determining a second to-be-detected high-speed connector for receiving the high-level signal;
and determining a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
Optionally, the detecting, by the motherboard BMC, the target connection relationship according to a preset connection relationship includes:
the main board BMC acquires a socket list, wherein the socket list is used for indicating a preset connection relation between the first high-speed connector and the second high-speed connector;
the main board BMC determines a preset connection relation between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the socket list;
and detecting the connection of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the preset connection relation and the target connection relation.
Optionally, the detecting, according to the preset connection relationship and the target connection relationship, connection of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector includes:
judging whether the preset connection relation is the same as the target connection relation;
if yes, determining that the connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct;
if not, determining that the connection relation of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is abnormal.
Optionally, after the detecting the target connection relationship, the method further includes:
and the main board BMC determines a new first high-speed connector to be detected from the plurality of first high-speed connectors again according to the detection time sequence, takes other first high-speed connectors as new first candidate high-speed connectors, detects the connection relation of the new first high-speed connectors to be detected, and the new first high-speed connectors to be detected are the first high-speed connectors to be detected.
In a second aspect, the present application provides a server high-speed cable detection apparatus, applied to a hardware configuration based on a general design of a server, where the hardware configuration includes: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the mainboard CPLD and the mainboard BMC, the mainboard pin of mainboard CPLD be connected with a plurality of first high-speed connectors a plurality of server backplate with at least one RISER card corresponds respectively and is connected with the second high-speed connector, first high-speed connector with the second high-speed connector passes through high-speed cable connection, and this device includes:
the determining module is used for determining a first high-speed connector to be detected from the plurality of first high-speed connectors and taking other first high-speed connectors as first candidate high-speed connectors;
The transmission module is used for transmitting detection signals through a plurality of first high-speed connectors, wherein the identification of the detection signals transmitted by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals transmitted by the first high-speed connectors to be detected is a second identification;
the acquisition module is used for: the detection signals received by the plurality of second high-speed connectors are acquired;
the determining module is further used for determining a second to-be-detected high-speed connector connected with the first to-be-detected high-speed connector corresponding to the second identifier according to the identifier in the detection signal, and obtaining a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector;
and the detection module is used for detecting the target connection relation according to a preset connection relation.
Optionally, the acquiring module is further configured to acquire detection timings of the plurality of first high-speed connectors through IIC protocols, write the detection timings into a CPLD register of the main board, and output the CPLD corresponding to the detection timings
The determining module is further configured to determine a first to-be-detected high-speed connector from the plurality of first high-speed connectors.
Optionally, the sending module is further configured to send a high-level signal through the first to-be-detected high-speed connector, where an identifier of the high-level signal is a second identifier;
And transmitting a low-level signal through a plurality of first candidate high-speed connectors, wherein the identification of the low-level signal is a first identification.
Optionally, the determining module is further configured to determine a high-level signal identified as a second identifier from the high-low level signals, and determine a second to-be-detected high-speed connector that receives the high-level signal;
and determining a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
Optionally, the obtaining module is further configured to obtain a socket list, where the socket list is used to indicate a preset connection relationship between the first high-speed connector and the second high-speed connector;
the determining module is further configured to determine a preset connection relationship between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the socket list;
the detection module is further configured to detect connection of a high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the preset connection relationship and the target connection relationship.
Optionally, the apparatus further includes: a judging module;
the judging module is used for judging whether the preset connection relation is the same as the target connection relation;
The determining module is further configured to determine that a connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct when the preset connection relationship is the same as the target connection relationship;
the determining module is further configured to determine that a connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is abnormal when the preset connection relationship and the target connection relationship are different.
Optionally, the detection module is further configured to re-determine a new first to-be-detected high-speed connector from the plurality of first high-speed connectors according to the detection timing sequence, take the other first high-speed connectors as new first candidate high-speed connectors, and detect a connection relationship of the new first to-be-detected high-speed connectors, where the new first to-be-detected high-speed connector is the first to-be-detected high-speed connector.
In a third aspect, the present application provides a server high-speed cable detection apparatus device, including:
a memory;
a processor;
wherein the memory stores computer-executable instructions;
the processor executes the computer-executable instructions stored in the memory to implement the server high-speed cable detection method as described in the first aspect and various possible implementations of the first aspect.
In a fourth aspect, the present application provides a computer storage medium having stored thereon computer-executable instructions that are executed by a processor to implement the server high-speed cable detection method as described in the first aspect and various possible implementations of the first aspect.
According to the method for detecting the high-speed cable of the server, the first high-speed connectors to be detected are determined from the plurality of first high-speed connectors through the main board BMC, and other first high-speed connectors are used as first candidate high-speed connectors; the main board CPLD respectively sends detection signals through the plurality of first high-speed connectors, wherein the identification of the detection signals sent by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals sent by the first high-speed connectors to be detected is a second identification; the main board BMC acquires detection signals received by a plurality of second high-speed connectors, and determines a second to-be-detected high-speed connector connected with a first to-be-detected high-speed connector corresponding to a second identification according to the identification in the detection signals, so as to obtain a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector; and the main board BMC detects the target connection relation according to a preset connection relation. The method supports high-speed cable detection of all the daughter cards on the basis of general design, has higher expansibility, solves the signal crosstalk problem caused by PWM waves in the prior art, and reduces CPLD pins and corresponding resource use.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a scenario of high-speed cable detection in the prior art provided by the present application;
fig. 2 is a schematic diagram of a scenario of a method for detecting a high-speed cable of a server provided by the present application;
FIG. 3 is a flowchart of a method for detecting a high-speed cable of a server according to the present application;
FIG. 4 is a second flowchart of a method for detecting a high-speed cable of a server according to the present application;
fig. 5 is a schematic structural diagram of a high-speed cable detection device of a server provided by the application;
fig. 6 is a schematic structural diagram of a server high-speed cable detection device provided by the application.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
First, the terms related to the present application will be explained.
Server motherboard: the server motherboard is installed in the chassis, and is one of the fundamental and most important components of the server. The server motherboard is a motherboard specially developed for meeting the requirements of the application of the server in the environment with high stability, high performance and high compatibility. The server's requirements on the server's motherboard are quite stringent due to the high operating time, high operating strength, and large amounts of data conversion, power consumption, and I/O throughput of the server.
Server backboard: the server backboard is a substrate and is responsible for bearing the functional boards including the daughter boards or the line cards. The main task of the server back plane is to carry the daughter boards and distribute power to the function boards for electrical connection and signal transmission. Thus, system functionality may be obtained through cooperation between the server backplane and its daughterboards.
RISER card: the RISER card is an expansion card which is introduced because various Option cards such as a network card, an HBA card, a video card and the like cannot be directly inserted on a main board due to the structural design limit of a server. The server motherboard provides a relatively long slot on which the risr card is inserted, while the risr card provides a standard PCIe slot on which various Option cards are inserted.
CPLD: CPLD (Complex Programmable Logic Device) is a digital integrated circuit in which the user constructs logic functions by himself as desired. The basic design method is to use integrated development software platform, using schematic diagram, hardware description language and other methods to generate corresponding target file, and transmitting code to target chip through downloading cable to realize designed digital system.
BMC: the BMC, collectively referred to as baseboard management controller (Baseboard Management Controller), is a specialized service processor that uses sensors to monitor the status of a computer, web server, or other hardware driven device and communicates with the system administrator via separate connection lines. The sensors of the BMC are used to measure internal physical variables such as: temperature, supply voltage, fan speed, communication parameters, and operating system functions. Any of these variables are outside of the scope of the established limits and the BMC will notify the administrator.
9555: PCA9555 consists of two 8-bit configurations, an input port, an output port, and a polarity inversion register. At power up, the I/O is configured as an input. The system host controller may initiate I/O as either input or output by writing I/O configuration bits. Each input or output data is stored in a respective input or output register. The polarity of the input port registers may be switched by means of a polarity inversion register. All registers are readable by the system master.
PWM: PWM (Pulse width modulation) is pulse width modulated, i.e. a pulse shape with a variable duty cycle. Pulse width modulation is a method of digitally encoding the analog signal level. With the use of a high resolution counter, the duty cycle of the square wave is modulated to encode the level of a particular analog signal. The PWM signal is still digital in that at any given moment, the full magnitude dc supply is either completely or completely absent. The voltage or current source is applied to the analog load in an on or off repetitive pulse sequence. The on time is when the direct current power supply is applied to the load, and the off time is when the power supply is disconnected. Any analog value can be encoded using PWM as long as the bandwidth is sufficient.
Along with the continuous acceleration of the progress of the informatization age, various types of products are continuously updated, and the demands of users on high-performance and high-configuration servers are increasing. Various cables are often used in server designs to match different backplanes to achieve more configuration requirements. One high-speed connector on the motherboard can be used for butting a plurality of backplanes. How to determine whether the high-speed connector is connected or not and whether the high-speed connector is connected correctly in the current configuration is a problem which must be considered in the technical field of servers.
Fig. 1 is a schematic diagram of a scenario of high-speed cable detection in the prior art provided by the present application. As shown in fig. 1, the server hardware design includes: the server comprises a server main board, a plurality of server back boards and at least one RISER card, wherein two pins in the server main board CPLD are connected to a high-speed connector, the plurality of server back boards CPLD are directly connected with the server main board high-speed connector through the back board high-speed connector, and the RISER card high-speed connector is in short circuit.
When the server high-speed cable detection is performed, the server motherboard CPLD sends PWM waveforms with different duty cycles to different high-speed connectors to be detected. Different PWM waveforms are used for distinguishing different high-speed connectors to be detected, the server backboard CPLD and the server RISER card loop back pulse signals after receiving the PWM waveforms sent by the main board CPLD, if the server main board CPLD receives the PWM waveforms and returns, the server BMC accesses the main board CPLD and the backboard CPLD through a protocol, and judges whether the current cable is inserted and whether part of the cable connection is correct.
However, for the board card without the CPLD, the server cannot confirm the connection mode of the high-speed cable, and if the cables are crossed by mistake during assembly, the sequence of IO may be affected. For different high-speed connectors, the motherboard CPLD needs to send PWM pulse signals with different duty cycles. Although the faster the PWM wave frequency is, the faster the back plate response is, but crosstalk exists for a long time to other signals in the server, and in order to improve the detection reliability, the larger the step duty ratio of the PWM wave is required, the better the step duty ratio is, and the communication efficiency of the server is affected.
The application provides a method for detecting a high-speed cable of a server. Fig. 2 is a schematic diagram of a scenario of the method for detecting a high-speed cable of a server according to the present application. As shown in fig. 2, the hardware configuration of the present embodiment applied to the general design of the server includes, as can be seen from fig. 2: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the motherboard CPLD and the motherboard BMC are connected with a plurality of first high-speed connectors through motherboard pins of the motherboard CPLD, a plurality of server back boards and at least one RISER card are correspondingly connected with second high-speed connectors respectively, and the first high-speed connectors and the second high-speed connectors are connected through high-speed cables.
According to the method for detecting the high-speed cable of the server, different identifiers are adopted to distinguish the detection signals sent by the high-speed connector to be detected from the detection signals sent by other high-speed connectors, and then the identifiers of the detection signals received by the high-speed connectors on the backboard and the RISER card are identified, so that the connection relation between the high-speed connector to be detected and the high-speed connectors on the backboard and the RISER card is determined, and the high-speed cable corresponding to the connection relation is detected. The method supports high-speed cable detection of all the daughter cards on the basis of general design, has higher expansibility, solves the signal crosstalk problem caused by PWM waves in the prior art, and reduces CPLD pins and corresponding resource use.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
Fig. 3 is a flowchart of a method for detecting a high-speed cable of a server according to an embodiment of the present application. As can be seen from fig. 2, the hardware configuration of the present embodiment applied to the general design of the server includes: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the motherboard CPLD and the motherboard BMC are connected with a plurality of first high-speed connectors through motherboard pins of the motherboard CPLD, a plurality of server back boards and at least one RISER card are correspondingly connected with second high-speed connectors respectively, and the first high-speed connectors and the second high-speed connectors are connected through high-speed cables. The method for detecting the high-speed cable of the server shown in the embodiment comprises the following steps:
S101: the main board BMC determines a first high-speed connector to be detected from the plurality of first high-speed connectors, and takes other first high-speed connectors as first high-speed connectors to be detected.
The first high-speed connectors are a plurality of high-speed connectors connected with the CPLD, the first high-speed connector to be detected is a first high-speed connector selected by the BMC and connected with the high-speed cable to be detected, and the rest of the first high-speed connectors are used as first candidate high-speed connectors. The main board BMC may, for example, randomly select one of the plurality of first high-speed connectors as a first to-be-detected high-speed connector, or may select a corresponding first to-be-detected high-speed connector according to a preset detection timing sequence.
S102: the main board CPLD respectively sends detection signals through the plurality of first high-speed connectors, wherein the identification of the detection signals sent by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals sent by the first high-speed connectors to be detected is a second identification.
The first identifier is used for indicating that the corresponding first high-speed connector is not detected currently, the second identifier is used for indicating that the corresponding first high-speed connector is required to be detected currently, and the first identifier is different from the second identifier; namely: the main board CPLD transmits a detection signal with a second mark through a first high-speed connector to be detected, and transmits a detection signal with a first mark through the first high-speed connector to be detected.
It may be appreciated that the detection signal may be, for example, a high-low level signal, the first identifier may indicate that the detection signal sent by the corresponding first high-speed connector is a low level signal, and the second identifier may indicate that the detection signal sent by the corresponding first high-speed connector is a high level signal.
The method is the same as the control variable method in principle, and in the subsequent steps, the main board BMC can identify the corresponding second high-speed connector to be detected through the detection signal identifiers received by the second high-speed connector connected on the backboard CPLD and the RISER card.
S103: the main board BMC acquires detection signals received by the second high-speed connectors, determines second connectors to be detected, which are connected with the first connectors to be detected and correspond to the second identifiers, according to the identifiers in the detection signals, and obtains a target connection relation between the first connectors to be detected and the second connectors to be detected.
The second high-speed connector is a high-speed connector connected with the backboard CPLD and/or the RISER card, and receives detection signals sent by the mainboard CPLD through the first high-speed connector; the second to-be-detected high-speed connector is a second high-speed connector which receives a detection signal with a second identifier, sent by the main board CPLD through the first to-be-detected high-speed connector, in the second high-speed connector.
It can be understood that, because the first to-be-detected high-speed connector and the second to-be-detected high-speed connector are connected through the high-speed cable, the detection signal which is sent by the first to-be-detected high-speed connector and is marked as the second mark can be received by the second to-be-detected high-speed connector, so that the high-speed cable connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector, namely the target connection relationship, can be obtained.
S104: and the main board BMC detects the target connection relation according to a preset connection relation.
The preset connection relationship is a connection relationship between a high-speed connector connected with a motherboard CPLD preset by the server system and a high-speed connector connected with the backplane CPLD and the RISER card, namely the preset connection relationship comprises connection relationships between all first high-speed connectors and all second high-speed connectors.
The main board BMC can determine whether the high-speed cable corresponding to the target connection relationship is connected correctly or not by inquiring the preset connection relationship, namely, the target connection relationship is detected.
For example: whether the target connection relationship is recorded in a preset connection relationship or not can be judged, if yes, the corresponding high-speed cable is indicated to be connected correctly, and if not, the corresponding high-speed cable is indicated to be connected incorrectly.
The method for detecting the high-speed cable of the server is applied to hardware configuration based on general design of the server, and a main board BMC determines a first high-speed connector to be detected from a plurality of first high-speed connectors and takes other first high-speed connectors as first candidate high-speed connectors; after the first high-speed connectors to be detected are determined, the main board CPLD respectively sends detection signals through a plurality of first high-speed connectors, wherein the identification of the detection signals sent by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals sent by the first high-speed connectors to be detected is a second identification; after the first high-speed connector sends a detection signal, the main board BMC acquires detection signals received by a plurality of second high-speed connectors, and determines a second to-be-detected high-speed connector connected with the first to-be-detected high-speed connector corresponding to a second identifier according to the identifier in the detection signals, so as to obtain a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector; and the main board BMC detects the target connection relation according to the preset connection relation. The method supports high-speed cable detection of all the daughter cards on the basis of general design, has higher expansibility, solves the signal crosstalk problem caused by PWM waves in the prior art, and reduces CPLD pins and corresponding resource use.
Fig. 4 is a flowchart of a method for detecting a high-speed cable of a server according to an embodiment of the present application. The hardware configuration applied to the general design of the server, as shown in fig. 2, includes: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the motherboard CPLD and the motherboard BMC are connected with a plurality of first high-speed connectors through motherboard pins of the motherboard CPLD, a plurality of server back boards and at least one RISER card are correspondingly connected with second high-speed connectors respectively, and the first high-speed connectors and the second high-speed connectors are connected through high-speed cables. The present embodiment is a detailed description of a method for detecting a high-speed cable of a server based on the embodiment of fig. 3. As shown in fig. 4, the method for detecting a high-speed cable of a server according to the present embodiment includes:
s201: and the main board BMC writes the detection time sequence into a main board CPLD register through protocols such as IIC and the like, and the CPLD outputs a corresponding detection time sequence.
The detection sequence is a detection sequence of a first high-speed connector to be detected, which is preset by the server system. The registers are registers of the motherboard CPLD, and one byte may correspond to eight of the registers. The detection timing stored in the register may be, for example, the order of all signals sent to the high-speed connector by the motherboard CPLD.
It can be understood that the main board BMC writes the detection timing sequence into the main board CPLD register through the IIC and other protocols, and the CPLD outputs the corresponding detection timing sequence, and at the same time, the main board BMC can detect the connection condition of the high-speed cable according to the detection timing sequence.
S202: and the main board BMC determines a first high-speed connector to be detected from the plurality of first high-speed connectors according to the detection time sequence, and takes other first high-speed connectors as first candidate high-speed connectors.
The first high-speed connectors are a plurality of high-speed connectors connected with the CPLD, the first high-speed connector to be detected is a first high-speed connector selected by the BMC and connected with the high-speed cable to be detected, and the rest of the first high-speed connectors are used as first candidate high-speed connectors.
The main board BMC determines a first to-be-detected high-speed connector, and the first to-be-detected high-speed connector sends a detection signal different from that sent by the first candidate high-speed connector. It will be appreciated that the identification of the detection signal sent by the first high speed connector to be detected is also different from the first candidate high speed connector. That is, the purpose of distinguishing the first high-speed connector to be detected from the first high-speed connector to be detected is to detect the high-speed cable connection condition by the detection signals of different identifications.
S203: the method comprises the steps that a main board CPLD sends a high-level signal through a first high-speed connector to be detected, and the identification of the high-level signal is a second identification; the motherboard CPLD transmits a low-level signal through a plurality of first candidate high-speed connectors, and the identification of the low-level signal is a first identification.
Where high and low are a term of physics, high refers to a high signal, high voltage, low refers to zero voltage or low. A voltage higher than 0V may be referred to as a high level, and a voltage lower than 0V may be referred to as a low level. In a digital logic circuit, a low level indicates 0, a high level indicates 1, and a low level of 0 to 0.25V and a high level of 3.5 to 5V are generally prescribed.
In the hardware configuration of the present application, 9555 devices connected to the backplane CPLD and the RISER card are used to receive the high-low level signals sent by the first high-speed connector. The different level signals have different identifications, the identification of the high level signal is a second identification, the identification of the low level signal is a first identification, the first identification and the second identification are different, the first identification can be 0 for example, for indicating that the type of the detection signal is the low level signal, and the second identification can be 1 for example, for indicating that the type of the detection signal is the high level signal. The method is the same as the control variable method in principle, and in the subsequent steps, the main board BMC can identify the corresponding second high-speed connector to be detected through the detection signal identifiers received by the second high-speed connector connected on the backboard CPLD and the RISER card.
S204: the main board BMC acquires detection signals received by the plurality of second high-speed connectors, determines a high-level signal marked as a second mark from the high-level signal and the low-level signal, and determines a second connector to be detected, which receives the high-level signal.
The second high-speed connector is a high-speed connector connected with the backboard CPLD and/or the RISER card, and receives detection signals sent by the mainboard CPLD through the first high-speed connector; the second to-be-detected high-speed connector is a second high-speed connector which receives a detection signal with a second identifier, sent by the main board CPLD through the first to-be-detected high-speed connector, in the second high-speed connector.
It can be understood that the detection signals received by the second high-speed connectors except the second high-speed connector to be detected are all low-level signals marked as the first mark, and the main board BMC can acquire the detection signals received by the plurality of second high-speed connectors and determine the second high-speed connector to be detected which receives the high-level signals marked as the second mark.
S205: and determining a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
The first to-be-detected high-speed connector and the second to-be-detected high-speed connector are connected through the high-speed cable, so that a detection signal which is sent by the first to-be-detected high-speed connector and is marked as a second mark can be received by the second to-be-detected high-speed connector, and a high-speed cable connection relationship, namely the target connection relationship, between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector can be obtained.
It can be understood that the target connection relationship is a connection relationship between a first to-be-detected high-speed connector and a second to-be-detected high-speed connector connected to the to-be-detected high-speed cable. The step of determining the target connection relationship may be, for example: the main board high-speed connector 1 sends a detection signal with a detection signal mark of 1, the rest main board high-speed connectors send detection signals with detection signal marks of 0, the RISER1 card high-speed connector receives the detection signals with the detection signal marks of 1, and cable connection between the main board high-speed connector 1 and the RISER1 card high-speed connector is indicated, namely, a target connection relation is determined.
S206: the BMC acquires a socket list, and determines a preset connection relation between the second to-be-detected high-speed connector and the first generation high-speed connector according to the socket list.
The preset connection relationship is a connection relationship between a high-speed connector connected with a motherboard CPLD preset by the server system and a high-speed connector connected with the backplane CPLD and the RISER card, namely the preset connection relationship comprises connection relationships between all first high-speed connectors and all second high-speed connectors.
It can be understood that the connection relationship between the high-speed connector connected to the motherboard CPLD and the high-speed connector connected to the backplane CPLD and the RISER card has a socket list corresponding to the connection relationship, and the motherboard BMC can obtain a preset connection relationship between the second to-be-detected high-speed connector and the first generation high-speed connector according to the socket list. It can be understood that the preset connection relationship is a connection relationship when the high-speed cable between the second to-be-detected high-speed connector and the first generation high-speed connector is correctly connected.
S207: judging whether the preset connection relation is the same as the target connection relation; if yes, step S209 is executed, and if no, step S208 is executed.
The judgment of whether the preset connection relation is the same as the target connection relation can obtain whether the connection relation between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct, so that the detection purpose of the server high-speed cable detection scheme is achieved.
S208: and determining that the connection relation of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is abnormal.
The difference between the preset connection relation and the target connection relation indicates that the connection relation of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is abnormal, namely the connection error of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected. The cause of the error may be, for example: when the system assembles the high-speed cable, the cable is crossed by mistake, and the end part of the high-speed cable which is connected with the second high-speed connector to be detected and the first high-speed connector to be detected is not inserted into the socket or the socket is loosened when the end part of the high-speed cable is inserted into the socket.
S209: and determining that the connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct.
The preset connection relation and the target connection relation are the same, so that the connection relation of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is correct, namely the connection of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is correct.
Optionally, after the high-speed cable is detected, the detection can be performed on other high-speed cables, and the specific steps are as follows: the main board BMC determines a new first to-be-detected high-speed connector from the plurality of first high-speed connectors again according to the detection timing sequence, uses the other first high-speed connectors as new first candidate high-speed connectors, and detects the connection relationship of the new first to-be-detected high-speed connectors, and the steps are similar to the steps S101 to S104 described above, and will not be repeated here.
The method for detecting the high-speed cable of the server is applied to hardware configuration based on general design of the server, and the main board CPLD firstly acquires detection time sequences of a plurality of first high-speed connectors and stores the detection time sequences in a register; after the main board CPLD acquires the detection time sequence, the main board BMC determines a first high-speed connector to be detected from the plurality of first high-speed connectors according to the detection time sequence, and takes other first high-speed connectors as first candidate high-speed connectors; after the first high-speed connector to be detected is determined, the main board CPLD sends a high-level signal marked as a second mark through the first high-speed connector to be detected, and sends a low-level signal marked as a first mark through a plurality of first candidate high-speed connectors; the method comprises the steps that a main board BMC obtains detection signals received by a plurality of second high-speed connectors, determines a high-level signal marked as a second mark from high-low-level signals, determines a second to-be-detected high-speed connector for receiving the high-level signal, and determines a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector; the method comprises the steps that a main board BMC obtains a socket list, and a preset connection relation between a second to-be-detected high-speed connector and a first generation high-speed connector is determined according to the socket list; judging whether the preset connection relation is the same as the target connection relation, if so, indicating that the high-speed cable is connected correctly, and if not, indicating that the connection is wrong. And then, the main board BMC determines a new first high-speed connector to be detected from the plurality of first high-speed connectors according to the detection time sequence, takes other first high-speed connectors as new first candidate high-speed connectors, and detects the connection relation of the new first high-speed connectors to be detected. The method provides a novel method for detecting high-speed cable connection on the basis of general design, and effectively solves the problems of incomplete, difficult expansion and signal crosstalk in the existing cable detection mode. The high-speed cable detection of all the daughter cards is supported, the expansibility is high, the signal crosstalk problem caused by PWM waves in the prior art is solved, and CPLD pins and corresponding resource use are reduced.
Fig. 5 is a schematic structural diagram of the high-speed cable detection device of the server provided by the application. The device is applied to hardware configuration based on server general design, and the hardware configuration comprises: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the main board CPLD and the main board BMC, the main board pin of the main board CPLD is connected with a plurality of first high-speed connectors, a plurality of server backplates and at least one RISER card are respectively correspondingly connected with a second high-speed connector, and the first high-speed connector and the second high-speed connector are connected through a high-speed cable, and the device 400 comprises:
a determining module 401, configured to determine a first to-be-detected high-speed connector from a plurality of first high-speed connectors, and use other first high-speed connectors as first candidate high-speed connectors;
a transmitting module 402, configured to transmit detection signals through a plurality of first high-speed connectors, where the identifiers of the detection signals transmitted by the plurality of first candidate high-speed connectors are first identifiers, and the identifiers of the detection signals transmitted by the first high-speed connectors to be detected are second identifiers;
an acquiring module 403, configured to acquire detection signals received by a plurality of second high-speed connectors;
The determining module 401 is further configured to determine, according to the identifier in the detection signal, a second to-be-detected high-speed connector connected to the first to-be-detected high-speed connector corresponding to the second identifier, to obtain a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector;
and the detection module 404 is configured to detect the target connection relationship according to a preset connection relationship.
Optionally, the acquiring module 403 is further configured to write the detection timing sequence into the CPLD register of the main board through protocols such as IIC, and the CPLD outputs a corresponding detection timing sequence;
the determining module 401 is further configured to determine a first to-be-detected high-speed connector from the plurality of first high-speed connectors.
Optionally, the sending module 402 is further configured to send a high-level signal through the first to-be-detected high-speed connector, where an identifier of the high-level signal is a second identifier;
and transmitting a low-level signal through a plurality of first candidate high-speed connectors, wherein the identification of the low-level signal is a first identification.
Optionally, the determining module 401 is further configured to determine a high-level signal identified as a second identifier from the high-low level signals, and determine a second to-be-detected high-speed connector that receives the high-level signal;
And determining a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
Optionally, the obtaining module 403 is further configured to obtain a socket list, where the socket list is used to indicate a preset connection relationship between the first high-speed connector and the second high-speed connector;
the determining module 401 is further configured to determine a preset connection relationship between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the socket list;
the detection module 404 is further configured to detect, according to the preset connection relationship and the target connection relationship, connection of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
Optionally, the apparatus further includes: a judgment module 405;
the judging module 405 is configured to judge whether the preset connection relationship is the same as the target connection relationship;
the determining module 401 is further configured to determine that a connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct when the preset connection relationship is the same as the target connection relationship;
The determining module 401 is further configured to determine that a connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is abnormal when the preset connection relationship and the target connection relationship are different.
Optionally, the detecting module 404 is further configured to re-determine a new first to-be-detected high-speed connector from the plurality of first high-speed connectors according to the detection timing sequence, take the other first high-speed connectors as new first candidate high-speed connectors, and detect a connection relationship of the new first to-be-detected high-speed connector, where the new first to-be-detected high-speed connector is the first to-be-detected high-speed connector.
Fig. 6 is a schematic structural diagram of a high-speed cable detection device of a server according to the present application. As shown in fig. 6, the present application provides a server high-speed cable detection apparatus, the server high-speed cable detection apparatus 500 comprising: a receiver 501, a transmitter 502, a processor 503 and a memory 504.
A receiver 501 for receiving instructions and data;
a transmitter 502 for transmitting instructions and data;
memory 504 for storing computer-executable instructions;
a processor 503 for executing computer-executable instructions stored in a memory 504 to implement the steps executed by the server high-speed cable detection method in the above embodiment. Reference may be made in particular to the description of the foregoing embodiments of the method for detecting a high-speed cable of a server.
Alternatively, the memory 504 may be separate or integrated with the processor 503.
When the memory 504 is provided separately, the electronic device further comprises a bus for connecting the memory 504 and the processor 503.
The application also provides a computer storage medium, wherein computer execution instructions are stored in the computer storage medium, and when the processor executes the computer execution instructions, the method for detecting the high-speed cable of the server, which is executed by the device for detecting the high-speed cable of the server, is realized.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the present application has been described with reference to the preferred embodiments shown in the drawings, it will be readily understood by those skilled in the art that the scope of the application is not limited to those specific embodiments, and the above examples are only for illustrating the technical solution of the application, not for limiting it; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (10)
1. A server high-speed cable detection method is applied to hardware configuration based on a server general design, and the hardware configuration comprises the following steps: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the mainboard CPLD and the mainboard BMC, the mainboard pin of mainboard CPLD be connected with a plurality of first high-speed connectors a plurality of server backplate with at least one RISER card corresponds respectively and is connected with the second high-speed connector, first high-speed connector with the second high-speed connector passes through high-speed cable connection, its characterized in that includes:
The main board BMC determines a first high-speed connector to be detected from the plurality of first high-speed connectors, and takes other first high-speed connectors as first candidate high-speed connectors;
the main board CPLD respectively sends detection signals through the plurality of first high-speed connectors, wherein the identification of the detection signals sent by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals sent by the first high-speed connectors to be detected is a second identification;
the main board BMC acquires detection signals received by a plurality of second high-speed connectors, and determines a second to-be-detected high-speed connector connected with a first to-be-detected high-speed connector corresponding to a second identification according to the identification in the detection signals, so as to obtain a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector;
and the main board BMC detects the target connection relation according to a preset connection relation.
2. The method of claim 1, wherein before the motherboard BMC determines a first high speed connector to be tested from the plurality of first high speed connectors, the method further comprises:
the main board BMC writes the detection time sequence into a main board CPLD register through protocols such as IIC and the like, and the CPLD outputs a corresponding detection time sequence; the main board BMC determines a first to-be-detected high-speed connector from the plurality of first high-speed connectors, and comprises the following steps:
And the main board BMC determines a first to-be-detected high-speed connector from the plurality of first high-speed connectors according to the detection time sequence.
3. The method according to claim 1, wherein the detection signals include high-low level signals, and the motherboard CPLD sends the detection signals through the plurality of first high-speed connectors, respectively, comprising:
the main board CPLD sends a high-level signal through the first high-speed connector to be detected, and the mark of the high-level signal is a second mark;
and the main board CPLD transmits a low-level signal through a plurality of first candidate high-speed connectors, and the identification of the low-level signal is a first identification.
4. A method according to claim 3, wherein the determining, according to the identifier in the detection signal, the second to-be-detected high-speed connector to which the first to-be-detected high-speed connector corresponding to the second identifier is connected, includes:
determining a high-level signal identified as a second identifier from the high-level signal and the low-level signal, and determining a second to-be-detected high-speed connector for receiving the high-level signal;
and determining a target connection relation according to the second to-be-detected high-speed connector and the first to-be-detected high-speed connector.
5. The method of claim 1, wherein the detecting the target connection relationship by the motherboard BMC according to a preset connection relationship comprises:
the main board BMC acquires a socket list, wherein the socket list is used for indicating a preset connection relation between the first high-speed connector and the second high-speed connector;
the main board BMC determines a preset connection relation between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the socket list;
and detecting the connection of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector according to the preset connection relation and the target connection relation.
6. The method of claim 5, wherein detecting the connection of the high-speed cable between the second high-speed connector to be tested and the first high-speed connector according to the preset connection relationship and the target connection relationship comprises:
judging whether the preset connection relation is the same as the target connection relation;
if yes, determining that the connection relationship of the high-speed cable between the second to-be-detected high-speed connector and the first to-be-detected high-speed connector is correct;
If not, determining that the connection relation of the high-speed cable between the second high-speed connector to be detected and the first high-speed connector to be detected is abnormal.
7. The method of claim 2, wherein after the detecting the target connection relationship, the method further comprises:
and the main board BMC determines a new first high-speed connector to be detected from the plurality of first high-speed connectors again according to the detection time sequence, takes other first high-speed connectors as new first candidate high-speed connectors, detects the connection relation of the new first high-speed connectors to be detected, and the new first high-speed connectors to be detected are the first high-speed connectors to be detected.
8. A server high-speed cable inspection device, characterized by being applied to a hardware configuration based on a server general design, the hardware configuration comprising: server motherboard, a plurality of server backplates and at least one RISER card, the server motherboard comprising: the motherboard CPLD and the motherboard BMC, the motherboard pin of the motherboard CPLD is connected with a plurality of first high-speed connectors, a plurality of server back boards and at least one RISER card are respectively correspondingly connected with a second high-speed connector, and the first high-speed connector is connected with the second high-speed connector through a high-speed cable, and the device comprises:
The determining module is used for determining a first high-speed connector to be detected from the plurality of first high-speed connectors and taking other first high-speed connectors as first candidate high-speed connectors;
the transmission module is used for transmitting detection signals through a plurality of first high-speed connectors, wherein the identification of the detection signals transmitted by the plurality of first candidate high-speed connectors is a first identification, and the identification of the detection signals transmitted by the first high-speed connectors to be detected is a second identification;
the acquisition module is used for: the detection signals received by the plurality of second high-speed connectors are acquired;
the determining module is further used for determining a second to-be-detected high-speed connector connected with the first to-be-detected high-speed connector corresponding to the second identifier according to the identifier in the detection signal, and obtaining a target connection relationship between the first to-be-detected high-speed connector and the second to-be-detected high-speed connector;
and the detection module is used for detecting the target connection relation according to a preset connection relation.
9. A server high-speed cable inspection apparatus, comprising:
a memory;
a processor;
wherein the memory stores computer-executable instructions;
the processor executes computer-executable instructions stored in the memory to implement the server high-speed cable detection method of any one of claims 1-7.
10. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are for implementing the server high speed cable detection method as recited in any of claims 1-7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116990725A (en) * | 2023-09-27 | 2023-11-03 | 成都电科星拓科技有限公司 | Cable in-place signal indication system and method |
| CN117667818A (en) * | 2024-01-31 | 2024-03-08 | 苏州元脑智能科技有限公司 | Signal transmission structure, server and signal transmission method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116990725A (en) * | 2023-09-27 | 2023-11-03 | 成都电科星拓科技有限公司 | Cable in-place signal indication system and method |
| CN116990725B (en) * | 2023-09-27 | 2023-12-12 | 成都电科星拓科技有限公司 | Cable in-place signal indication system and method |
| CN117667818A (en) * | 2024-01-31 | 2024-03-08 | 苏州元脑智能科技有限公司 | Signal transmission structure, server and signal transmission method |
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