CN111966419A - Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment - Google Patents
Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment Download PDFInfo
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- CN111966419A CN111966419A CN202011018469.XA CN202011018469A CN111966419A CN 111966419 A CN111966419 A CN 111966419A CN 202011018469 A CN202011018469 A CN 202011018469A CN 111966419 A CN111966419 A CN 111966419A
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- 230000003750 conditioning effect Effects 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000001105 regulatory effect Effects 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 8
- 210000001503 joint Anatomy 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/4408—Boot device selection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses a method and a device for automatically distributing VPP (virtual private point) addresses to signal conditioning equipment.A substrate management controller reads an FRU (field replaceable unit) electronic tag in the signal conditioning equipment to acquire a current slot as the signal conditioning equipment, and then determines what address the signal conditioning equipment should provide for each cable connector according to the topological relation between the slot of a mainboard and the management bus equipment, wherein each slot is connected to which group of management bus ports of a CPU (central processing unit), an IO (input/output) extension circuit is added in the signal conditioning equipment, and after a BMC (baseboard management controller) acquires the topological relation between the signal conditioning equipment and the management bus ports of the CPU, the VPP lighting address of a corresponding Nvme hard disk is automatically distributed. Through the mode, the automatic VPP address allocation method can automatically realize VPP address automatic allocation, avoid manual operation of a production line, and improve the operation efficiency and accuracy of the production line.
Description
Technical Field
The invention relates to the technical field of server hard disks, in particular to a method and a device for automatically distributing VPP addresses by signal conditioning equipment.
Background
In the current scenario where the NVME hard disk is docked with the motherboard CPU, the address of the VPP, such as the PCIE port and the CPU source, is determined by the address pin in the slim line cable connector, and each slim line connector and cable includes 8 pairs of PCIE signals, and also includes a 3-bit CPU address and a 4-bit PCIE port address. The address pin is pulled up and down differently in the mainboard according to the source of the PCIE in the slim line connector, so that the PCIE received in the hard disk backplane is ensured to be strictly consistent with the address pin.
However, for a scene where the timer device is in butt joint with the NVME hard disk, the mainboard is connected with the timer device through the standard PCIE slot, the address pin cannot be transmitted, the CPLD of the hard disk backplane cannot sense the VPP address, and the lighting behavior of the CPU cannot be analyzed for which NVME hard disk. The current solution is, connect the address pin of slim line connector to dial switch in the timer card on, when production equipment, insert the different slot at the mainboard according to the PCIE card, dock different CPU's different PCIE ports, dial the dial in the timer equipment to corresponding CPU address and PCIE port address, backplate CPLD receives the distribution of corresponding address completion NVME signal of lighting a lamp from the slim line, realizes that the NVME hard disk correctly lights a lamp.
The main disadvantages of the implementation mode are that the manual dial operation of the production line is relied on, the automatic identification cannot be realized, the production efficiency is reduced, and errors are easy to generate.
Disclosure of Invention
The invention mainly solves the technical problem of providing a method and a device for automatically distributing VPP addresses by signal conditioning equipment, which can automatically distribute the VPP lighting addresses of corresponding NVME hard disks, replace the original production line dial switch scheme, improve the production efficiency of a production line and reduce the error probability of the production line.
In order to solve the technical problems, the invention adopts a technical scheme that: there is provided a method of a signal conditioning apparatus for automatically allocating a VPP address, comprising: the method comprises the steps that firstly, a server is powered on, a substrate controller is started, the substrate controller detects a reset signal in a PCIE slot, and a PCIE board card is confirmed to be installed in the PCIE slot; step two, the substrate controller reads the electronic tag in the PCIE board card in a traversing manner, so as to judge whether the PCIE board card is the signal conditioning equipment; thirdly, if the signal conditioning equipment is the signal conditioning equipment, the substrate controller confirms the VPP address of the signal conditioning equipment in butt joint according to the topology prestored in the system; fourthly, the substrate controller converts the VPP address into a VPP address corresponding to the signal conditioning equipment; the substrate controller writes the VPP address corresponding to the signal regulating equipment into an IO expansion circuit of the signal regulating equipment, and the hard disk backboard is lighted; and fifthly, powering on the server and starting the CPU.
Further, in the first step, when the reset signal in the PCIE slot is detected, the server provides the reset signal for the PCIE slot and the PCIE board, and if the reset signal in the PCIE slot is valid, it is determined that the PCIE board is installed in the PCIE slot.
Further, the electronic tag is stored in a board information area of the PCIE board; the electronic tag is an FRU electronic tag.
Further, the storage mode of the FRU electronic tag is a management FRU information storage mode in an intelligent platform management interface.
Further, the system pre-stored topology is a topological relation between slots of the mainboard and the PCIE board card.
Further, the topology relationship between the slots of the motherboard and the PCIE board card can identify the VPP address corresponding to the signal conditioning device.
Further, the VPP address includes a CPU address and a PCIE interface address.
An apparatus for a signal conditioning device to automatically assign VPP addresses, comprising: CPU, BMC, signal conditioning equipment, hard disk backboard; the signal conditioning equipment is provided with a signal conditioning chip, an erasable programmable read-only memory module and an IO expansion circuit module; the signal regulating chip, the erasable programmable read-only memory module and the IO expansion circuit module are all inserted into the signal regulating equipment slot; the hard disk backboard is provided with a complex programmable logic device and an Nvme hard disk; the IO expansion circuit module is connected with the complex programmable logic device through a connector; the CPU is connected with the signal adjusting chip through a PCIE interface in the slot; the CPU is connected with the complex programmable logic device through an I2C bus; the signal adjusting chip is connected to the Nvme hard disk through the PCIE interface; the BMC is connected with the erasable programmable read-only memory module and the IO expansion circuit module through an I2C bus.
Further, a lighting IO is arranged on the complex programmable logic device.
The invention has the beneficial effects that: according to the invention, the FRU electronic tag and the IO expander circuit are used in the timer equipment, the position topology of the timer equipment is automatically identified by the BMC, the VPP lighting address of the corresponding NVME hard disk is automatically distributed, the original scheme of a dial switch of a production line is replaced, the production efficiency of the production line is improved, and the error probability of the production line is reduced.
Drawings
FIG. 1 is a flow chart of a preferred embodiment of a method for signal conditioning equipment to automatically allocate VPP addresses in accordance with the present invention;
FIG. 2 is a connection diagram of an apparatus for automatically assigning VPP addresses by a signal conditioning device according to the present invention;
fig. 3 is a topological relation table between slots of a motherboard and PCIE devices in the present invention.
Detailed Description
The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.
Referring to fig. 1 to 3, an embodiment of the present invention includes:
a method for a signal conditioning device to automatically assign VPP addresses, comprising: firstly, a server is powered on, a BMC is started, the BMC detects a PRsnt signal in a PCIE slot and confirms a PCIE board card in the PCIE slot; secondly, the BMC reads the FRU electronic tag in the PCIE board card in a traversing manner, so as to judge whether the PCIE board card is a timer device; thirdly, if the equipment is the timer equipment, the BMC confirms the VPP address butted by the timer equipment according to the pre-stored topology of the system; fourthly, converting the BMC into a VPP address corresponding to the timer device, wherein the VPP address comprises a CPU address and a PCIE port address; the BMC is written into the IO expander of the timer device and is used for lighting the NVme hard disk backboard; and fifthly, powering on the server and starting the CPU.
The PRsnt signal is a global reset signal and is provided by the processor system, and the processor system needs to provide the reset signal for the PCIE slot and the PCIE device. The PCIE device uses this signal to reset the internal logic. When the signal is valid, the PCIE device performs a reset operation. The timer device is a standard PCIE board card realized based on a timer chip, and is used for increasing the driving capacity of PCIE signals in a server.
In the first step, when the reset signal in the PCIE slot is detected, the server provides the reset signal for the PCIE slot and the PCIE board, and if the reset signal in the PCIE slot is valid, it is determined that the PCIE board is installed in the PCIE slot.
In the second step, when the BMC reads the FRU electronic tag in the PCIE board card through traversal, the FRU electronic tag is identified from the PCIE board card information area, and whether the PCIE board card in the current PCIE slot is a timer device is judged; and the storage mode of the FRU electronic tag is a management FRU information storage mode in the intelligent platform management interface.
Referring to fig. 3, in the third step, the system prestores a topology as a topological relationship between a slot of the motherboard and a PCIE port, can identify a CPU and a PCIE port number corresponding to the timer device, writes the identified addresses (CPU _ ADDR and port _ ADDR) into the IO expander, and outputs the addresses to the address pin in the slim connector.
Hardware aspects
The BMC reads an FRU electronic tag in the timer device to judge whether a current slot is the timer device, and then through the topological relation between the slots of the mainboard and the PCIE ports, each slot is connected to which PCIE port of the CPU, so that what address the timer device should provide for each slim connector is determined.
And adding an IO expander in the timer device, after the BMC acquires the topological relation between the timer device and the PCIE port of the CPU, the BMC operates the IO expander to output a proper VPP address including the CPU address and the PCIE port address, connects the VPP address to the slim connector, and sends the VPP address to the backboard for the CPLD to analyze the VPP lighting signal.
Software aspects
The acquisition mode of the single Board Information uses an FRU electronic tag, the Information Storage mode of the single Board Information accords with a protocol ipmi-Platform Management FRU Information Storage Definition, after the BMC is started, the slots with the PCIE boards are identified to be in place through a reset signal of the PCIE boards, then the FRU electronic tags of all the PCIE boards in place are read in a traversing manner, and whether the current slot is a timer device or not is identified from the Board Info Area.
Based on the same inventive concept as the method for automatically allocating a VPP address by a signal conditioning apparatus in the foregoing embodiments, an embodiment of the present specification further provides an apparatus for automatically allocating a VPP address by a signal conditioning apparatus, including: CPU, BMC, signal conditioning equipment, hard disk backboard; the signal conditioning equipment is provided with a signal conditioning chip, an erasable programmable read-only memory module and an IO expansion circuit module; the signal regulating chip, the erasable programmable read-only memory module and the IO expansion circuit module are all inserted into the signal regulating equipment slot; the hard disk backboard is provided with a complex programmable logic device and an Nvme hard disk; a lighting IO is arranged on the complex programmable logic device; the IO expansion circuit module is connected with the complex programmable logic device through a connector; the CPU is connected with the signal adjusting chip through a PCIE interface in the slot; the CPU is connected with the complex programmable logic device through an I2C bus; the signal adjusting chip is connected to the Nvme hard disk through the PCIE interface; the BMC is connected with the erasable programmable read-only memory module and the IO expansion circuit module through an I2C bus.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A method for a signal conditioning device to automatically assign VPP addresses, comprising: the method comprises the steps that firstly, a server is powered on, a substrate controller is started, the substrate controller detects a reset signal in a PCIE slot, and a PCIE board card is confirmed to be installed in the PCIE slot; step two, the substrate controller reads the electronic tag in the PCIE board card in a traversing manner and judges whether the PCIE board card is the signal adjusting equipment or not; thirdly, if the signal conditioning equipment is the signal conditioning equipment, the substrate controller confirms the VPP address of the signal conditioning equipment in butt joint according to the topology prestored in the system; fourthly, the substrate controller converts the VPP address into a VPP address corresponding to the signal conditioning equipment; the substrate controller writes the VPP address corresponding to the signal regulating equipment into an IO expansion circuit of the signal regulating equipment, and the hard disk backboard is lighted; and fifthly, powering on the server and starting the CPU.
2. The method of claim 1, wherein the signal conditioning apparatus automatically allocates a VPP address, and further comprising: in the first step, when the reset signal in the PCIE slot is detected, the server provides the reset signal for the PCIE slot and the PCIE board, and if the reset signal in the PCIE slot is valid, it is determined that the PCIE board is installed in the PCIE slot.
3. The method of claim 1, wherein the signal conditioning apparatus automatically allocates a VPP address, and further comprising: the electronic tag is stored in a board card information area of the PCIE board card; the electronic tag is an FRU electronic tag.
4. A method of automatically assigning VPP addresses according to claim 3, wherein: the storage mode of the FRU electronic tag is a management FRU information storage mode in an intelligent platform management interface.
5. The method of claim 1, wherein the signal conditioning apparatus automatically allocates a VPP address, and further comprising: the system pre-stored topology is a topological relation between slots of the mainboard and the PCIE board card.
6. The method of claim 5, wherein the signal conditioning apparatus automatically allocates a VPP address, wherein: and the VPP address corresponding to the signal adjusting equipment can be identified by the topological relation between the slot of the mainboard and the PCIE board card.
7. The method of claim 6, wherein the signal conditioning apparatus automatically allocates a VPP address, wherein: the VPP address comprises a CPU address and a PCIE interface address.
8. An apparatus for a signal conditioning device to automatically assign VPP addresses, comprising: CPU, BMC, signal conditioning equipment, hard disk backboard; the signal conditioning equipment is provided with a signal conditioning chip, an erasable programmable read-only memory module and an IO expansion circuit module; the signal regulating chip, the erasable programmable read-only memory module and the IO expansion circuit module are all inserted into the signal regulating equipment slot; the hard disk backboard is provided with a complex programmable logic device and an Nvme hard disk; the IO expansion circuit module is connected with the complex programmable logic device through a connector; the CPU is connected with the signal adjusting chip through a PCIE interface in the slot; the CPU is connected with the complex programmable logic device through an I2C bus; the signal adjusting chip is connected to the Nvme hard disk through the PCIE interface; the BMC is connected with the erasable programmable read-only memory module and the IO expansion circuit module through an I2C bus.
9. The apparatus of claim 8, wherein the signal conditioning device automatically assigns a VPP address, and further comprising: and a lighting IO is arranged on the complex programmable logic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011018469.XA CN111966419A (en) | 2020-09-24 | 2020-09-24 | Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011018469.XA CN111966419A (en) | 2020-09-24 | 2020-09-24 | Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment |
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| CN111966419A true CN111966419A (en) | 2020-11-20 |
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| CN202011018469.XA Withdrawn CN111966419A (en) | 2020-09-24 | 2020-09-24 | Method and device for automatically distributing VPP (virtual private Point) addresses by signal conditioning equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113434443A (en) * | 2021-06-11 | 2021-09-24 | 苏州浪潮智能科技有限公司 | System and method for supporting automatic switching of PCIE (peripheral component interface express) clock |
| CN113872796A (en) * | 2021-08-26 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | Server and node equipment information acquisition method, device, equipment and medium thereof |
| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
| CN117472289A (en) * | 2023-12-27 | 2024-01-30 | 苏州元脑智能科技有限公司 | Storage configuration adjustment method, device, system, equipment and medium of server |
-
2020
- 2020-09-24 CN CN202011018469.XA patent/CN111966419A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113434443A (en) * | 2021-06-11 | 2021-09-24 | 苏州浪潮智能科技有限公司 | System and method for supporting automatic switching of PCIE (peripheral component interface express) clock |
| CN113872796A (en) * | 2021-08-26 | 2021-12-31 | 浪潮电子信息产业股份有限公司 | Server and node equipment information acquisition method, device, equipment and medium thereof |
| CN113872796B (en) * | 2021-08-26 | 2024-04-23 | 浪潮电子信息产业股份有限公司 | Server and node equipment information acquisition method, device, equipment and medium thereof |
| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
| CN114328314B (en) * | 2021-12-31 | 2024-05-28 | 华勤通讯香港有限公司 | Automatic address acquisition method and device, terminal equipment and storage medium |
| CN117472289A (en) * | 2023-12-27 | 2024-01-30 | 苏州元脑智能科技有限公司 | Storage configuration adjustment method, device, system, equipment and medium of server |
| CN117472289B (en) * | 2023-12-27 | 2024-03-15 | 苏州元脑智能科技有限公司 | Storage configuration adjustment method, device, system, equipment and medium of server |
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Application publication date: 20201120 |