CN111159085B - Automatic configuration method of PCIE (peripheral component interface express) bandwidth, server mainboard and server - Google Patents
Automatic configuration method of PCIE (peripheral component interface express) bandwidth, server mainboard and server Download PDFInfo
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Abstract
The invention discloses an automatic configuration method of PCIE (peripheral component interface express) bandwidth, a server mainboard and a server, wherein in the scheme, a BMC (baseboard management controller) can acquire identification information of a Riser card connected with a slot on the server mainboard, bandwidth configuration information of PCIE equipment inserted in a slot of the Riser card and information of the slot, the Riser card can transfer and distribute the bandwidth of the slot to each slot on the Riser card, a BIOS (basic input output system) chip can determine the bandwidth of the slot inserted by the PCIE equipment according to the identification information and the identification information of the slot, and after the bandwidth required by the PCIE equipment is determined according to the bandwidth configuration information, the bandwidth of the slot inserted by the PCIE equipment is reconfigured, so that the bandwidth of the distributed slot accords with the bandwidth of the PCIE equipment. The scheme does not need to release different BIOS chip versions for different machine types and packages, so that the BIOS chips are convenient to maintain; the manual participation is not needed, and the reliability and the automation degree are high.
Description
Technical Field
The present invention relates to the technical field of bandwidth configuration, and in particular, to an automatic configuration method of a PCIE bandwidth, a server board, and a server.
Background
With the higher integration level of the server, the simplified and intelligent human-computer interaction during the production of the server is highly emphasized by manufacturers and customers. In order to provide more flexible customized services for clients, a server configures multiple types of packages for a server motherboard, and considering that the number of slots on the server motherboard is constant, in order to meet the requirement of connecting multiple PCIE (peripheral component interconnect express) devices with the server motherboard, a Riser card (also called a Riser card) is usually disposed on the server motherboard. Different types of PCIE add-in card devices are collocated through different types of Riser cards, such as a network card, an intelligent network card, a RAID (Redundant Arrays of Independent Drives) card, and the like.
Specifically, a BIOS (Basic Input Output System) chip configures a bandwidth to which a PCIE device is plugged based on bandwidth configuration information, and since the bandwidth configuration information corresponding to the PCIE devices of different models and packages may also be different, in the prior art, the bandwidth configuration information is stored in the BIOS firmware in advance, and if the bandwidth configuration information of the PCIE device is not stored in the BIOS firmware, a user needs to manually reissue different BIOS versions to obtain the bandwidth configuration information of the PCIE device, which may be seen that the existing bandwidth configuration mode makes the adaptability of the BIOS version poor.
Disclosure of Invention
The invention aims to provide a PCIE bandwidth automatic configuration method, a server mainboard and a server, which do not need to issue different BIOS chip versions for different machine types and packages, are convenient for the maintenance of BIOS chips and have high adaptability of the BIOS chips; in addition, the scheme realizes the automatic configuration of the bandwidth of the PCIE equipment, does not need manual participation and has high reliability and automation degree.
In order to solve the above technical problem, the present invention provides an automatic configuration method for a PCIE bandwidth, which is applied to a server motherboard, where the server motherboard includes a BMC, a BIOS chip, and a slot, and the method includes:
the BMC acquires identification information of a Riser card connected with the slot, bandwidth configuration information of PCIE equipment inserted in a card slot of the Riser card and information of the card slot;
the BIOS chip determines the bandwidth of the card slot according to the identification information and the information of the card slot;
and the BIOS chip determines the bandwidth required by the PCIE equipment according to the bandwidth configuration information, and reconfigures the bandwidth of the card slot so that the bandwidth of the card slot meets the bandwidth required by the PCIE equipment.
Preferably, the identification information of the Riser card is the model of the Riser card.
Preferably, the server motherboard further includes a CPLD and a CPU, and before the BIOS chip determines the bandwidth of the card slot according to the identification information, the method further includes:
the BMC acquires CPU information connected with the Riser card, wherein the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD stores the identification information and the bandwidth configuration information into an LPC register corresponding to the CPU information according to a preset CPU and LPC register corresponding relation;
and the BIOS chip acquires the identification information and the bandwidth configuration information from the LPC register based on a preset LPC address.
Preferably, the method further comprises the following steps:
when receiving CPU information, identification information and the bandwidth configuration information newly sent by the BMC, the CPLD judges whether the stored identification information and the bandwidth configuration information exist in an LPC register corresponding to the CPU information;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
In order to solve the above technical problem, the present invention further provides a server motherboard, which includes a slot, and further includes:
the BMC is used for acquiring identification information of the Riser card connected with the slot, bandwidth configuration information of PCIE equipment inserted in a card slot of the Riser card and information of the card slot;
the BIOS chip is used for determining the bandwidth of the card slot according to the identification information and the information of the card slot; determining the bandwidth required by the PCIE equipment according to the bandwidth configuration information, and reconfiguring the bandwidth of the card slot so that the bandwidth of the card slot meets the bandwidth required by the PCIE equipment.
Preferably, the identification information of the Riser card is the model of the Riser card.
Preferably, the server motherboard further comprises a CPLD and a CPU;
the BMC is further used for acquiring CPU information connected with the Riser card, and the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD is used for storing the identification information and the bandwidth configuration information into an LPC register corresponding to the CPU information according to a preset CPU and LPC register corresponding relation;
the BIOS chip is further configured to obtain the identification information and the bandwidth configuration information from the LPC register based on a preset LPC address.
Preferably, the CPLD is further configured to:
when CPU information, identification information and the bandwidth configuration information which are newly sent by BMC are received, judging whether the newly sent CPU information exists in the LPC register;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
In order to solve the technical problem, the invention further provides a server, which comprises a Riser card, a PCIE device connected with the Riser card, and the server motherboard.
Preferably, the PCIE device is an intelligent network card or a RAID card.
The invention provides an automatic configuration method of PCIE (peripheral component interface express) bandwidth, in the scheme, a BMC (baseboard management controller) can acquire identification information of a Riser card connected with a slot on a server mainboard, bandwidth configuration information of PCIE equipment inserted in a slot of the Riser card and information of the slot, the Riser card can transfer and distribute the bandwidth of the slot to each slot on the Riser card, a BIOS (basic input output system) chip can determine the bandwidth of the slot inserted by the PCIE equipment according to the identification information and the identification information of the slot, and after the bandwidth required by the PCIE equipment is determined according to the bandwidth configuration information, the bandwidth of the slot inserted by the PCIE equipment is reconfigured, so that the bandwidth of the slot after distribution accords with the bandwidth of the PCIE equipment. Therefore, by the mode, the BMC can acquire the bandwidth information of various PCIE devices, the BIOS chip acquires the bandwidth configuration information from the BMC and configures the bandwidth of the PCIE devices according to the bandwidth configuration information, different BIOS chip versions do not need to be issued for different machine types and packages, the BIOS chip is convenient to maintain, and the adaptability of the BIOS chip is high; in addition, the scheme realizes the automatic configuration of the bandwidth of the PCIE equipment, does not need manual participation and has high reliability and automation degree.
The invention also provides a server mainboard and a server, and the server mainboard and the server have the same beneficial effects as the automatic configuration method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of an automatic configuration method for PCIE bandwidth provided in the present invention;
fig. 2 is a schematic structural diagram of a server according to the present invention.
Detailed Description
The core of the invention is to provide a PCIE bandwidth automatic configuration method, a server mainboard and a server, which do not need to issue different BIOS chip versions aiming at different machine types and packages, and are convenient for the maintenance of the BIOS chips; in addition, the scheme realizes the automatic configuration of the bandwidth of the PCIE equipment, does not need manual participation and has high reliability and automation degree.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of an automatic configuration method for PCIE bandwidth provided in the present invention.
The automatic configuration method is applied to a server mainboard, the server mainboard comprises a BMC, a BIOS chip and a slot, and the method comprises the following steps:
s11: a BMC (Baseboard Management Controller) acquires identification information of a Riser card connected with a slot, bandwidth configuration information of PCIE (peripheral component interface express) equipment inserted in a slot of the Riser card and information of the slot;
s12: the BIOS chip determines the bandwidth of the card slot according to the identification information and the information of the card slot;
s13: the BIOS chip determines the bandwidth required by the PCIE equipment according to the bandwidth configuration information, and reconfigures the bandwidth of the card slot so that the bandwidth of the card slot meets the bandwidth required by the PCIE equipment.
Considering that the number of slots on a server motherboard is fixed, for the requirement of connecting multiple PCIE devices with the server motherboard, a Riser card connected to a slot on the server motherboard is usually set, where the Riser card is used to convert the bandwidth of the slot, for example, the slot has a bandwidth of x32, some Riser cards may convert the slot having a bandwidth of x32 into 2 slots, and the bandwidth of each slot is x 16; some Riser cards can convert slots with the bandwidth of x32 into 4 slots, and the bandwidth of each slot is x 8; the card slot and bandwidth converted by different types of Riser cards are also different. The PCIE device is connected to the server motherboard through the Riser card, assuming that the PCIE device is an intelligent network card and needs a bandwidth of x8, taking the example that the Riser card converts x32 into 2 x16, at this time, the bandwidth of the card slot of the Riser card needs to be reconfigured, specifically, the bandwidth of the card slot into which the intelligent network card is plugged is reconfigured from x16 to 2 x 8.
In order to automatically implement the configuration process, in this application, it is considered that the BMC may initialize after the server is powered on, the BMC may scan and monitor hardware on the server motherboard in the initialization process, and may acquire information of the Riser card and the PCIE device connected to the slot through the I2C interface, specifically, it may communicate with the Riser card through the IC2 to acquire identification information capable of representing the type of the Riser card and information capable of determining which card slot of the Riser card the PCIE device is plugged in, and may also communicate with the PCIE device through the IC2 to acquire bandwidth configuration information capable of determining a bandwidth required by the PCIE device. After the server is started, the BIOS chip may obtain identification information of the Riser card, bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card, and information of the card slot from the BMC through an IPMI (Intelligent Platform Management Interface) command, and determine the type of the Riser card according to the identification information, and may know, according to the type of the Riser card, a conversion of the Riser card to the bandwidth of the slot, that is, the bandwidth of each card slot thereon, and may determine the bandwidth of the card slot to which the PCIE is plugged based on the information of the card slot. Then, the BIOS chip determines the bandwidth required by the PCIE device according to the bandwidth configuration information, and reconfigures the bandwidth of the card slot to which the PCIE device is plugged based on the bandwidth, so that the bandwidth of the card slot can satisfy the bandwidth required by the PCIE device.
Therefore, by the mode, the BMC can acquire the bandwidth information of various PCIE devices, the BIOS chip acquires the bandwidth configuration information from the BMC and configures the bandwidth of the PCIE devices according to the bandwidth configuration information, different BIOS chip versions do not need to be issued for different machine types and packages, the BIOS chip is convenient to maintain, and the adaptability of the BIOS chip is high; in addition, the scheme realizes the automatic configuration of the bandwidth of the PCIE equipment, does not need manual participation and has high reliability and automation degree.
On the basis of the above-described embodiment:
as a preferred embodiment, the identification information of the Riser card is the model number of the Riser card.
In this embodiment, the identification information of the Riser card is the model number of the Riser card, and the type of the Riser card can be determined by the signal of the Riser card, and of course, the type of the Riser card can also be determined by other manners, which is not particularly limited in this application.
As a preferred embodiment, the server motherboard further includes a CPLD (Complex Programmable Logic Device) and a CPU, and before the BIOS chip determines the bandwidth of the card slot according to the identification information, the method further includes:
the BMC acquires CPU information connected with the Riser card, wherein the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD stores the identification information and the bandwidth configuration information into an LPC register corresponding to the CPU information according to the preset corresponding relation between the CPU and the LPC register;
and the BIOS chip acquires the identification information and the bandwidth configuration information from the LPC register based on a preset LPC address.
In the above embodiment, after the BMC acquires the identification information of the Riser card, the bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card, and the information of the card slot, the BIOS chip may acquire the identification information of the Riser card in the BMC, the bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card, and the information of the card slot through an instruction, but there is a risk of error and the information acquisition speed is relatively slow by using this method. In addition, if the BMC fails during the initialization process, the bandwidth of the PCIE device may not be configured, and the reliability is low.
In order to solve the above technical problem, in this embodiment, after acquiring the identification information of the Riser card, the bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card, and the information of the card slot, the BMC stores the identification information of the Riser card and the bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card into an LPC register in the CPLD, so that a subsequent BIOS chip acquires relevant information from the LPC register. In the process of implementing the above functions, it is also considered that there may be multiple PCUs on the server motherboard, and/or multiple connection slots are provided on the CPU, and the Riser card will be connected with the connection slot on the CPU through the slot. Therefore, the BMC can also obtain CPU information connected with the Riser card, where the CPU information includes CPU identification information for determining which specific CPU is connected with the Riser card and connection slot information for determining which connection slot is connected with the Riser card, and the CPLD stores the identification information and bandwidth configuration information into the LPC register corresponding to the CPU information according to the preset correspondence between the CPU and the LPC register after determining the CPU connected with the Riser card and the specific connection slot thereof. In the subsequent process, the BIOS chip can obtain the identification information and the bandwidth configuration information from the corresponding LPC register based on the preset LPC address. By adopting the mode, on one hand, the reliability is higher, and the error rate is extremely low; on the other hand, the information acquisition speed is high, and in addition, even if the BMC fails, the acquisition of the identification information and the bandwidth configuration information is not influenced, so that the configuration of the bandwidth of the PCIE equipment is ensured, and the reliability is further improved.
Specifically, please refer to table 1 and table 2, where table 1 is a table of correspondence between LPC addresses and data in an LPC register provided by the present invention, and table 2 is a table of correspondence between LPC addresses and data in an LPC register provided by the present invention.
TABLE 1 LPC register LPC Address and LPC register data mapping Table
TABLE 2 table of the correspondence between LPC address and data in LPC register
In fig. 2, the Riser card is only one type, so that the identification information is not written, and the CPU0 and the CPU1 are CPU identification information and represent two CPUs on the server motherboard; PE0, PE1, PE2, and PE3 are specific connection slot information indicating 4 connection slots on the CPU. 0111. 1011, 1101, 1110, 0011, 0101 are bandwidth configuration information.
Specifically, assuming that the Riser card is connected to the first connection slot of the CPU0 and the bandwidth configuration information is 0101, it is not difficult to obtain the bandwidth configuration information, the CPLD may determine that the data corresponding to the information is byte2 according to the first connection slot of the CPU0, fill the bandwidth configuration information into the byte2, the BIOS chip may know the relationship between the LPC address and the data in the LPC register in advance, and subsequently, when the bandwidth configuration information 0101 is obtained from the byte2, it may be determined that the bandwidth required by the PCIE device is x4, and the BIOS chip may reconfigure the card slot of x16 of the Riser card to 4 x4, thereby satisfying the bandwidth requirement of the PCIE device.
As a preferred embodiment, further comprising:
when receiving CPU information, identification information and bandwidth configuration information newly sent by the BMC, the CPLD judges whether the stored identification information and bandwidth configuration information exist in an LPC register corresponding to the CPU information;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
Specifically, considering that the BMC reacquires the identification information of the Riser card connected to the slot and the bandwidth configuration information of the PCIE device plugged in the card slot of the Riser card every time the server is powered on, if the information is updated regardless of the difference from the stored information every time, the time for updating the information is increased before the bandwidth configuration under the condition that the information is the same as the stored information, so that the efficiency of PCIE bandwidth configuration is reduced.
In the application, after receiving the CPU information, the identification information and the bandwidth configuration information newly sent by the BMC, the CPLD first determines whether the stored identification information and the bandwidth configuration information exist in the LPC register corresponding to the CPU information, and if so, determines whether the newly sent identification information and the bandwidth configuration information are the same as the previously stored identification information and the bandwidth configuration information, and if so, does not change the stored identification information and the bandwidth configuration information; and if not, updating the stored identification information and bandwidth configuration information based on the newly transmitted identification information and bandwidth configuration information. If the information does not exist, the information is newly added, and the identification information and the bandwidth configuration information which are newly transmitted need to be stored in the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register. For example, in table 2, if there is no bandwidth configuration information in the data corresponding to the third connection slot of the CPU0, the received bandwidth configuration information may be written into byte 4. It can be seen that configuration efficiency can be improved in this way.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a server according to the present invention.
This server mainboard includes the slot, still includes:
the BMC 1 is used for acquiring identification information of a Riser card 3 connected with the slot, bandwidth configuration information of a PCIE device 4 inserted in a card slot of the Riser card 3 and information of the card slot;
the BIOS chip 2 is used for determining the bandwidth of the card slot according to the identification information and the information of the card slot; and determining the bandwidth required by the PCIE device 4 according to the bandwidth configuration information, and reconfiguring the bandwidth of the card slot to enable the bandwidth of the card slot to meet the bandwidth required by the PCIE device 4.
As a preferred embodiment, the identification information of the Riser card 3 is the model number of the Riser card 3.
As a preferred embodiment, the server motherboard further comprises a CPLD and a CPU;
the BMC 1 is further used for acquiring CPU information connected with the Riser card 3, and the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD is used for storing the identification information and the bandwidth configuration information into the LPC register corresponding to the CPU information according to the preset corresponding relation between the CPU and the LPC register;
the BIOS chip 2 is further configured to obtain identification information and bandwidth configuration information from the LPC register based on a preset LPC address.
As a preferred embodiment, the CPLD is further configured to:
when CPU information, identification information and bandwidth configuration information newly sent by BMC 1 are received, whether the stored identification information and bandwidth configuration information exist in an LPC register corresponding to the CPU information or not is judged;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
For the introduction of the server motherboard provided by the present invention, please refer to the above method embodiment, which is not described herein again.
The invention also provides a server, which comprises a Riser card 3, a PCIE device 4 connected with the Riser card 3 and the server mainboard.
As a preferred embodiment, the PCIE device 4 is an intelligent network card or a RAID card.
Of course, the PCIE device 4 herein may also be another type of PCIE device, and the present application is not particularly limited herein.
For the introduction of a server provided by the present invention, please refer to the above method embodiment, which is not described herein again.
It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. An automatic configuration method of PCIE bandwidth is applied to a server mainboard, and is characterized in that the server mainboard comprises a BMC, a BIOS chip and a slot, and the method comprises the following steps:
the BMC acquires identification information of a Riser card connected with the slot, bandwidth configuration information of PCIE equipment inserted in a card slot of the Riser card and information of the card slot;
the BIOS chip determines the bandwidth of the card slot according to the identification information and the information of the card slot;
the BIOS chip determines the bandwidth required by the PCIE equipment according to the bandwidth configuration information, and reconfigures the bandwidth of the card slot so that the bandwidth of the card slot meets the bandwidth required by the PCIE equipment;
the server motherboard further includes a CPLD and a CPU, and before the BIOS chip determines the bandwidth of the card slot according to the identification information, the method further includes:
the BMC acquires CPU information connected with the Riser card, wherein the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD stores the identification information and the bandwidth configuration information into an LPC register corresponding to the CPU information according to a preset CPU and LPC register corresponding relation;
the BIOS chip acquires the identification information and the bandwidth configuration information from the LPC register based on a preset LPC address;
further comprising:
when receiving CPU information, identification information and the bandwidth configuration information newly sent by the BMC, the CPLD judges whether the stored identification information and the bandwidth configuration information exist in an LPC register corresponding to the CPU information;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
2. The automatic configuration method for PCIE bandwidth according to claim 1, wherein the identification information of the Riser card is a model number of the Riser card.
3. The utility model provides a server mainboard, its characterized in that includes the slot, still includes:
the BMC is used for acquiring identification information of the Riser card connected with the slot, bandwidth configuration information of PCIE equipment inserted in a card slot of the Riser card and information of the card slot;
the BIOS chip is used for determining the bandwidth of the card slot according to the identification information and the information of the card slot; determining the bandwidth required by the PCIE equipment according to the bandwidth configuration information, and reconfiguring the bandwidth of the card slot so that the bandwidth of the card slot meets the bandwidth required by the PCIE equipment;
the server mainboard further comprises a CPLD and a CPU;
the BMC is further used for acquiring CPU information connected with the Riser card, and the CPU information comprises CPU identification information and specific connecting groove information;
the CPLD is used for storing the identification information and the bandwidth configuration information into an LPC register corresponding to the CPU information according to a preset CPU and LPC register corresponding relation;
the BIOS chip is also used for acquiring the identification information and the bandwidth configuration information from the LPC register based on a preset LPC address;
the CPLD is further configured to:
when CPU information, identification information and the bandwidth configuration information which are newly sent by a BMC are received, whether the stored identification information and the stored bandwidth configuration information exist in an LPC register corresponding to the CPU information is judged;
if the identification information and the bandwidth configuration information exist, judging whether the newly sent identification information and the bandwidth configuration information are the same as the identification information and the bandwidth configuration information which are stored previously;
if the identification information and the bandwidth configuration information are the same, the stored identification information and the stored bandwidth configuration information are not changed;
if the identification information and the bandwidth configuration information are different, updating the stored identification information and the stored bandwidth configuration information based on the newly sent identification information and the newly sent bandwidth configuration information;
and if the CPU information does not exist, storing the newly transmitted identification information and the bandwidth configuration information into the LPC register corresponding to the newly transmitted CPU information according to the preset corresponding relation between the CPU and the LPC register.
4. The server main board according to claim 3, wherein the identification information of the Riser card is a model number of the Riser card.
5. A server, comprising a Riser card and a PCIE device connected with the Riser card, further comprising the server motherboard of claim 4.
6. The server of claim 5, wherein the PCIE device is a smart card or a RAID card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911402875.3A CN111159085B (en) | 2019-12-30 | 2019-12-30 | Automatic configuration method of PCIE (peripheral component interface express) bandwidth, server mainboard and server |
Applications Claiming Priority (1)
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| CN111752871A (en) * | 2020-05-29 | 2020-10-09 | 苏州浪潮智能科技有限公司 | PCIE equipment, device and method for realizing compatibility of same PCIE slot position with different PCIE bandwidths |
| CN111930660B (en) * | 2020-07-30 | 2022-04-15 | 长沙景嘉微电子股份有限公司 | PCIE path configuration method, device, terminal and medium |
| CN112015477B (en) * | 2020-08-06 | 2022-10-25 | 苏州浪潮智能科技有限公司 | PCIE link splitting method, system and expansion device |
| CN112398684A (en) * | 2020-11-02 | 2021-02-23 | 英业达科技有限公司 | PCIe bandwidth automatic allocation system and method |
| CN113010462B (en) | 2021-03-12 | 2023-02-17 | 英业达科技有限公司 | Circuit structure and method for automatically adjusting PCIe channel configuration |
| CN113064654A (en) * | 2021-04-21 | 2021-07-02 | 山东英信计算机技术有限公司 | BIOS-based Retimer card bandwidth configuration method, device and equipment |
| CN113220619A (en) * | 2021-04-30 | 2021-08-06 | 山东英信计算机技术有限公司 | Method, system and medium for distributing PCIE channel bandwidth |
| CN113448903B (en) * | 2021-05-21 | 2023-02-28 | 山东英信计算机技术有限公司 | PCIe bandwidth adjustment method, device, equipment and storage medium for NVMe expansion card |
| CN113407397B (en) * | 2021-06-10 | 2022-12-27 | 浪潮电子信息产业股份有限公司 | Display method, device, equipment and medium for screen printing of equipment cabinet |
| CN114003535B (en) * | 2021-10-14 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Device bandwidth configuration method and system, electronic device and storage medium |
| CN113688087B (en) * | 2021-10-25 | 2022-02-18 | 苏州浪潮智能科技有限公司 | PCIE (peripheral component interface express) device enumeration method, system, storage medium and device |
| TWI815255B (en) * | 2021-12-22 | 2023-09-11 | 神雲科技股份有限公司 | Detection method of riser board |
| CN115442239B (en) * | 2022-08-01 | 2024-02-09 | 河南昆仑技术有限公司 | Bandwidth resource allocation method, PCIe channel switcher and electronic device |
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