CN113220619A - Method, system and medium for distributing PCIE channel bandwidth - Google Patents
Method, system and medium for distributing PCIE channel bandwidth Download PDFInfo
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Abstract
The invention discloses a method, a system and a medium for distributing PCIE channel bandwidth, wherein the method comprises the following steps: writing the digital quasi-potential voltage value, the board card type and the bandwidth required by the board card for establishing the mapping relation into a board card bandwidth mapping table; executing a resistance ratio obtaining step, and configuring a first bandwidth identification device according to an execution result; the first bandwidth identification device is arranged on the board card, so that the BMC can identify the type of the board card, an ADC is arranged in the BMC, and the quasi-level voltage value can be converted into a binary quasi-level voltage value through the ADC; executing a binary quasi-bit voltage value acquisition step to acquire a binary quasi-bit voltage value; executing a reference voltage value comparison step, and acquiring the type of the board card and the bandwidth required by the board card according to an execution result; the BIOS distributes the bandwidth required by the board card; through the mode, the invention can reduce the using quantity of the resistors in the bandwidth identification device and does not occupy GPIO interface resources.
Description
Technical Field
The present invention relates to the field of board bandwidth allocation, and in particular, to a method, a system, and a medium for allocating PCIE channel bandwidth.
Background
In the server system, a CPU on a mainboard is connected with board cards with different functions through a PCIE interface, and different board cards occupy different PCIE channel bandwidths;
before a server system is started, a CPU on a mainboard needs to know which board cards, the types of the board cards and PCIE channel bandwidths occupied by different board cards in the server, so that a BIOS can allocate appropriate PCIE channel bandwidths to the board cards when the server system is started, and the situation that the board cards are unusable when the server system is started cannot be caused;
each board card is provided with a plurality of bandwidth identification devices, the bandwidth identification devices on each board card are connected with a GPIO (general purpose input/output) interface of a BMC (baseboard management controller) through cables and connectors, the BMC knows which board cards are arranged in a server system by detecting the state of the GPIO interface connected with the bandwidth identification devices, and simultaneously acquires PCIE channel bandwidth required by the board card which is required to be allocated by each board card, and after the server system is started, a BIOS acquires the board cards stored in the BMC and information such as PCIE channel bandwidth required by the board cards, and allocates the PCIE channel bandwidth to each board card;
the defects in the prior art are obvious, each board card is provided with a plurality of bandwidth identification devices, and each bandwidth identification device is provided with a plurality of resistors, so that a large number of resistors are used in the whole server system to greatly occupy the layout space of the server system;
each bandwidth identification device is connected with the GPIO interface on the BMC, so that a large number of pin resources of the GPIO interface and pin resources of the connector can be occupied, excessive cables can be used, the detection cost is increased, and the competitiveness of products is reduced.
Disclosure of Invention
The invention mainly solves the problems that a CPU (central processing unit) occupies a large amount of pin resources of GPIO (general purpose input/output) interfaces and pin resources of connectors when carrying out board card bandwidth detection, uses excessive cables and occupies a large amount of layout space.
In order to solve the technical problems, the invention adopts a technical scheme that: a method for allocating PCIE channel bandwidth is provided, which comprises the following steps:
writing the digital level voltage value, the board type and the required bandwidth of the board which are used for establishing the mapping relation into a board bandwidth mapping table
Executing a resistance ratio obtaining step according to the digital level voltage value, and configuring a first bandwidth identification device according to an execution result of the resistance ratio obtaining step;
the first bandwidth identification device is arranged on a board card, and an ADC is arranged in a BMC;
executing a binary level voltage value acquisition step through the BMC, the ADC and the first bandwidth identification device to acquire a binary level voltage value;
executing a quasi-position voltage value comparison step according to the digital quasi-position voltage value and the binary quasi-position voltage value, and acquiring and recording the type of the board card and the bandwidth required by the board card by the BMC according to an execution result of the quasi-position voltage value comparison step;
and the BIOS allocates the bandwidth required by the board card.
Preferably, the mapping relationship is: and obtaining the corresponding board card type and the bandwidth required by the board card according to the digital quasi-potential voltage value.
Preferably, the resistance ratio obtaining step further includes:
setting the voltage of the first bandwidth identification device, and recording the voltage as the voltage of the first bandwidth identification device;
converting the digital level voltage value into an analog voltage value, and recording the analog voltage value as an analog level voltage value;
and calculating the ratio of the resistance value of the first resistor and the resistance value of the second resistor in the first bandwidth identification device according to the voltage of the first bandwidth identification device, the analog level voltage value and a voltage division theorem, and recording the ratio as a first ratio.
Preferably, the step of configuring the first bandwidth identification device according to the execution result of the resistance ratio acquisition step further includes: selecting the first resistor and the second resistor according to the first ratio, and installing the first resistor and the second resistor in the first bandwidth identification device.
Preferably, the binary level voltage value obtaining step further includes: the BMC detects a voltage value of a node between the first resistor and the second resistor to obtain a quasi-level voltage value, and the quasi-level voltage value is converted into a binary quasi-level voltage value through the ADC, and the binary quasi-level voltage value is recorded as a binary quasi-level voltage value.
Preferably, the step of comparing the level voltage value further comprises: and the BMC acquires the binary quasi-bit voltage value, and retrieves the digital quasi-bit voltage value which is the same as the binary quasi-bit voltage value from the board card bandwidth mapping table.
Preferably, the step of allocating the bandwidth required by the board by the BIOS further includes: and the BIOS acquires the board card type recorded in the BMC and the corresponding bandwidth required by the board card, and distributes the bandwidth required by the board card to the board card corresponding to the board card type.
The invention also provides a system for distributing PCIE channel bandwidth, which comprises: the system comprises a BMC, a board card and a board card bandwidth allocation module;
the BMC is respectively connected with the board card and the board card bandwidth allocation module;
the BMC includes: the device comprises a mapping table establishing module, a resistance ratio acquiring module, a setting module, an ADC and a board card bandwidth acquiring module;
the board card is provided with a first bandwidth identification device;
the first bandwidth identification device is connected with the ADC;
the mapping table establishing module is used for writing the digital level voltage value for establishing the mapping relation, the board card type and the bandwidth required by the board card into a board card bandwidth mapping table;
the resistance ratio acquisition module is used for acquiring the resistance ratio in the first bandwidth identification device;
the setting module is used for setting the first bandwidth identification device on the board card and setting the ADC in the BMC;
the ADC is used for converting the voltage value measured from the first bandwidth identification device into a binary quasi-bit voltage value;
the board card bandwidth obtaining module is used for obtaining the board card type and the bandwidth required by the board card;
the board bandwidth allocation module is used for allocating the bandwidth required by the board.
Preferably, the board bandwidth obtaining module includes: the device comprises a reference voltage value comparison module and a bandwidth acquisition recording module;
the quasi-position voltage value comparison module is used for retrieving the digital quasi-position voltage value which is the same as the binary quasi-position voltage value from the board card bandwidth mapping table;
the bandwidth acquiring and recording module is used for acquiring and recording the board card type and the required bandwidth of the board card corresponding to the retrieved digital level voltage value.
The present invention further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the method for allocating PCIE channel bandwidth is implemented.
The invention has the beneficial effects that:
1. the method for distributing the PCIE channel bandwidth can reduce the using number of resistors in the bandwidth identification device, does not occupy GPIO interface resources any more, reduces the number of cables between a board card and a BMC, reduces the using of connecting pins of a connector, can select the connector with fewer pins and lower cost in the subsequent production process, and increases the competitiveness of products;
2. according to the system for distributing the PCIE channel bandwidth, the number of cable connection times between the bandwidth identification device and the connector can be reduced by reducing the resistance in the bandwidth identification device, the mode of detecting the quasi-level voltage in the bandwidth identification device is optimized, and the use pressure of a GPIO interface is greatly relieved by the mode of no occupying GPIO interface resources any more;
3. the medium for distributing the PCIE channel bandwidth can realize the direct connection with the bandwidth identification device by utilizing the analog-to-digital converter, does not occupy GPIO interface resources, reduces the pin positions of the connector, reduces the using number of resistors, reduces the using number of cables in the system and reduces the overall production cost of the server system.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart of a method for allocating a PCIE channel bandwidth according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram illustrating a connection between a first bandwidth identification device and a BMC in a board card according to a method for allocating a PCIE channel bandwidth described in embodiment 1 of the present invention;
fig. 3 is a schematic diagram illustrating a connection between a conventional bandwidth identification device and a BMC in a board card of the method for allocating a PCIE channel bandwidth according to embodiment 1 of the present invention;
fig. 4 is a schematic diagram of a system architecture for allocating PCIE channel bandwidth according to embodiment 2 of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "in", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," and "eighth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
It should be noted that, in the description of the present invention:
the CPU (central processing unit) is a central processing unit;
the BMC (baseboard Management controller) is a baseboard Management controller, and can perform operations such as firmware upgrade and checking of machine devices on a machine in a state that the machine is not started;
bwid (bandwidth identification) is a bandwidth identification means;
GPIO (General-purpose input/output) is General purpose input/output, a PIN can be freely used by a user through program control, and a PIN PIN can be used as General purpose input or General purpose output or General purpose input and output according to practical consideration;
BIOS (basic Input Output System) is a basic Input Output system, which is a set of programs solidified on a ROM chip on a main board in a computer;
PCIE (peripheral Component Interconnect express) is a high-speed serial computer expansion bus;
ADC (analog to Digital converter) is an analog-to-Digital converter that converts an input voltage signal into an output Digital signal.
Example 1
The embodiment of the present invention provides a method for allocating a PCIE channel bandwidth, please refer to fig. 1, which includes the following steps:
s100, establishing a mapping relation among a digital level voltage value, a board card type and a bandwidth required by a board card, and configuring a mapping table for mapping the relation among the digital level voltage value, the board card type and the bandwidth required by the board card in a baseboard management controller, wherein the mapping table is recorded as a board card bandwidth mapping table; three columns are set in the board card bandwidth mapping table, which are respectively: the digital quasi-potential voltage value, the type of the board card and the bandwidth required by the board card;
the digital level voltage value column writes a digital level voltage value set for each board card, wherein the digital level voltage value refers to a binary digital signal form of voltage values at intermediate nodes of 2 resistors connected in series in the bandwidth identification device on each board card, such as a first digital level voltage value, a second digital level voltage value, a third digital level voltage value, a fourth digital level voltage value and the like corresponding to each board card type;
the board type column writes the type of each board in the server system, for example: the types of different board cards such as a first board card type, a second board card type, a third board card type and a fourth board card type;
the bandwidth required by the board card is written into the PCIE channel bandwidth required by each board card under the column of bandwidth required by the board card, for example: the bandwidth required by the first board card, the bandwidth required by the second board card, the bandwidth required by the third board card, the bandwidth required by the fourth board card, and the like, where the bandwidth required by each board card may be a PCIE channel bandwidth 2 times as wide as the bandwidth, may be a PCIE channel bandwidth 4 times as wide as the bandwidth, may be a PCIE channel bandwidth 8 times as wide as the bandwidth, and may also be a PCIE channel bandwidth 16 times as wide as the bandwidth required by each board card;
in the board bandwidth mapping table, for example, the first digital level voltage value, the first board type, and the PCIE channel bandwidth required by the first board are in the same row to indicate the relationship of the mutual mapping among the first digital level voltage value, the first board type, and the PCIE channel required by the first board type; the second digital level voltage value, the second board card type and the PCIE channel bandwidth required by the second board card are in the same row to indicate the relationship of mutual mapping among the second digital level voltage value, the second board card type and the PCIE channel required by the second board card; the third digital level voltage value, the third board card type and the PCIE channel bandwidth required by the third board card are in the same column to indicate the relationship of mutual mapping among the third digital level voltage value, the third board card type and the PCIE channel required by the third board card, and the like;
s200, please refer to fig. 2, where only a connection relationship between the board and the BMC is shown, in order to reduce the use of resistors in the bandwidth identification device and not occupy excessive pin positions of the connector, only one group of resistors is arranged in the novel bandwidth identification device arranged on each board, the novel bandwidth identification device is denoted as a first bandwidth identification device, a potential difference between two ends of each group of resistors in each first bandwidth identification device on each board is set to be P3V3 and denoted as a first bandwidth identification device voltage, and the first bandwidth identification device has two resistors connected in series in the group of resistors and denoted as a first resistor RS1 and a second resistor RS 2; the first resistor RS1 and the second resistor RS2 calculate the ratio between the first resistor RS1 and the second resistor RS2 in the first bandwidth identification device according to the potential difference between two ends of each group of resistors in each first bandwidth identification device, the analog level voltage value represented by the corresponding digital level voltage value in the board card bandwidth mapping table of each board card and the voltage division theorem, select the respective resistance values of RS1 and RS2 according to the ratio, install the resistors RS1 and RS2 with the selected resistance values in the first bandwidth identification device, set the first bandwidth identification device on the corresponding board card, and set the ADC in the BMC;
for example, assuming that in the server system, we determine that the type of the board card is the first board card type through a nameplate or other board card features on the board, we find a digital level voltage value corresponding to the first board card type according to the board card bandwidth mapping table set in the step S100, calculate an analog level voltage value represented by the first digital level voltage value, which is denoted as the first analog level voltage value, calculate a second analog level voltage value, a third analog level voltage value, a fourth analog level voltage value, and the like by analogy, then start to set the first bandwidth identification device on the board card whose board card type is the first board card type, and set voltages at two ends of a group of resistors in the first bandwidth identification device to be P3V3 through the voltage source;
assuming that the first analog level voltage value is P2V2 and the potential difference across a set of resistors in the bandwidth identification device is P3V3, the obtained potential difference U1 across RS1 is P3V3-P2V2, which is P1V 1; the potential difference U2 between the two ends of the RS2 is P3V3-P1V1 ═ P2V2, and then the ratio of the resistances of the first resistor RS1 and the second resistor RS2 is 1/2 by the voltage division theorem of the series circuit U1/U2 ═ RS1/RS2 ═ P1V1/P2V2 ═ 1/2, so that the resistances of the first resistor RS1 and the second resistor RS2 meeting the first ratio can be selected according to the simulation, for example, the resistance of the RS1 is 1 ohm, and the resistance of the RS2 is 2 ohms; or RS1 is 2 ohms, RS2 is 4 ohms, and the novel bandwidth identification device provided with the first resistor RS1 and the second resistor RS2 is arranged on a first board card, where the first board card is a board card with a first board card type;
assuming that the second analog level voltage value is P1V1 and the potential difference across a set of resistors in the bandwidth identification device is P3V3, the obtained potential difference U1 across RS1 is P3V3-P1V1, which is P2V 2; the potential difference U2 between the two ends of the RS2 is P3V3-P2V2 ═ P1V1, and then the ratio of the resistances of the first resistor RS1 and the second resistor RS2 is 2 according to the voltage division theorem U1/U2 ═ RS1/RS2 ═ P2V2/P1V1 ═ 2/1, so that the resistances of the first resistor RS1 and the second resistor RS2 meeting the first ratio can be selected according to the simulation, for example, the resistance of the RS1 is 2 ohms, and the resistance of the RS2 is 1 ohm; or RS1 is 4 ohms, RS2 is 2 ohms, and the novel bandwidth identification device provided with the first resistor RS1 and the second resistor RS2 is arranged on a second board card, where the second board card is a board card with a board card type of a second board card type;
by the way in the above example, the resistance values of the first resistor RS1 and the second resistor RS2 which are connected in series in the novel bandwidth identification device are selected, and the novel bandwidth identification device with the selected resistance values of the first resistor RS1 and the second resistor RS2 is installed on the corresponding board card;
the prior bandwidth identification device is provided with three groups of resistors which are connected in parallel under the same voltage source, the voltages at two ends of each group of resistors are consistent, the potential difference between two ends of the three groups of resistors which are connected in parallel on each board card is set as P3V3, each group of resistors are formed by connecting two resistors with the same resistance in series, each resistor can execute the operation of whether each resistor is electrified or not according to the type of the board card on which the bandwidth identification device is installed, nodes between the two resistors which are connected in series in each group of resistors are connected to pins of a connector through cables, the connector is inserted into a GPIO (general purpose input/output) interface on a BMC (baseboard management controller) through a connector plug, and the BMC detects the state of the GPIO interface through a voltage digital detection method to distinguish;
for example, referring to fig. 3, in the conventional bandwidth identification apparatus, three groups of resistors are provided, each group includes two resistors connected in series, two resistors in the first group are respectively denoted as a third resistor RS3 and a fourth resistor RS4, two resistors in the second group are respectively denoted as a fifth resistor RS5 and a sixth resistor RS6, and two resistors in the third group are respectively denoted as a seventh resistor RS7 and an eighth resistor RS 8;
if the third resistor RS3, the fifth resistor RS5 and the seventh resistor RS7 are powered on, and the fourth resistor RS4, the sixth resistor RS6 and the eighth resistor RS8 are not powered on, the potential value detected by the BMC through the voltage digital detection method is 1:1: 1; the voltage digital detection method is characterized in that the detected voltage is digitally processed according to high and low potentials, so that the BMC can conveniently identify and process the voltage;
s300, arranging a first bandwidth identification device on each board card; an ADC (analog-to-digital converter) is arranged in a BMC (baseboard management controller) in the server system;
s400, recording a node between the first resistor RS1 and the second resistor RS2 as a reference voltage detection point, and connecting an ADC (analog to digital converter) in the BMC with the reference voltage detection point in the novel bandwidth identification device on each board;
before the server system is started and in a standby time period, the BMC acquires a voltage value of a reference voltage detection point in a first bandwidth identification device on each board card, and records the voltage value as the reference voltage value, the ADC converts the reference voltage value acquired from each board card into a corresponding binary signal through connection with the reference voltage detection point on each board card, and records the binary signal as the binary reference voltage value, and the meaning of converting the reference voltage value into the binary reference voltage value by the ADC is that the BMC can conveniently perform operation processing and recording on the reference voltage value in a digital signal form;
for example, before the server system is powered on and in a standby time period, the BMC is connected to the first board card to obtain a level voltage value P2V2 of a level voltage detection point of the first board card, and the ADC converts the P2V2 into a binary digital level voltage value, which is recorded as a first binary level voltage value; the BMC is connected with the second board card to obtain a quasi-level voltage value P1V1 of a quasi-level voltage detection point of the second board card, the ADC converts the P1V1 into another binary digital quasi-level voltage value, the binary quasi-level voltage value is recorded as a second binary quasi-level voltage value, and by analogy, the BMC obtains binary quasi-level voltage values corresponding to quasi-level voltage values on all board cards such as a first binary quasi-level voltage value, a second binary quasi-level voltage value, a third binary quasi-level voltage value, a fourth binary quasi-level voltage value and the like, and records the obtained binary quasi-level voltage values corresponding to voltage values on all quasi-level board cards such as the first binary quasi-level voltage value, the second binary quasi-level voltage value, the third binary quasi-level voltage value, the fourth binary quasi-level voltage value and the like;
s500, the BMC selects a first binary level voltage value, then searches and compares the first binary level voltage value with each digital level voltage value below the digital level voltage value in the board bandwidth mapping table, finds a first digital level voltage value in the board bandwidth mapping table which is the same as the first binary level voltage value recorded by the BMC, and records a first board type corresponding to the first digital level voltage value in the board bandwidth mapping table and a bandwidth required by the first board in the BMC;
the BMC selects a second binary quasi-bit voltage value, then searches and compares each digital quasi-bit voltage value below the digital quasi-bit voltage value in the board card bandwidth mapping table, finds a second digital quasi-bit voltage value in the board card bandwidth mapping table which is the same as the second binary quasi-bit voltage value recorded by the BMC, and records a second board card type corresponding to the second digital quasi-bit voltage value in the board card bandwidth mapping table and a bandwidth required by the second board card into the BMC;
by analogy, finding out the board card types of all the board cards connected with the BMC and the required bandwidth of the board card corresponding to the board card types, and recording the board card types of all the board cards connected with the BMC and the required bandwidth of the board card corresponding to the board card types, which are found by searching and comparing, into the BMC;
s600, the BIOS is connected with the BMC through the SMBus bus, when the server system is started, the BIOS acquires the board card type recorded in the BMC and the bandwidth required by the board card corresponding to the board card type through the SMBus bus, and allocates PCIE channel bandwidth to the board card of each board card type.
Example 2
An embodiment of the present invention further provides a system for allocating a PCIE channel bandwidth, please refer to fig. 4, including: the system comprises a BMC, a board card and a board card bandwidth allocation module;
the BMC is connected with a board card in the server through a cable and a connector;
the board card bandwidth allocation module is connected with the BMC through the SMBus bus;
the BMC includes: the device comprises a mapping table establishing module, a resistance ratio acquiring module, a setting module, an ADC and a board card bandwidth acquiring module;
the board card is provided with a first bandwidth identification device;
the ADC and the first bandwidth identification device are connected through a cable and a connector;
the mapping table establishing module is used for establishing a mapping relation among the digital level voltage value, the board card type and the bandwidth required by the board card and writing the mapping relation into a board card bandwidth mapping table;
the resistance ratio acquisition module is used for acquiring the ratio relation of the resistance in the first bandwidth identification device according to the digital quasi-position voltage value;
the setting module is used for setting the first bandwidth identification device on the board card and setting the ADC in the BMC;
the ADC is used for converting the analog voltage value of the middle node of the resistor in the first bandwidth identification device into a binary quasi-bit voltage value;
the board card bandwidth obtaining module is used for obtaining the board card type and the bandwidth required by the board card;
the board card bandwidth acquisition module comprises a reference voltage value comparison module and a bandwidth acquisition recording module;
the quasi-position voltage value comparison module is used for comparing the obtained binary quasi-position voltage value with all digital quasi-position voltage values in the board card bandwidth mapping table to find out the digital quasi-position voltage value which is the same as the binary quasi-position voltage value;
the bandwidth acquiring and recording module is used for acquiring and recording the board card type corresponding to the found digital quasi-potential voltage value and the bandwidth required by the board card;
and the board bandwidth allocation module is used for allocating the required PCIE channel bandwidth to each board according to the acquired board type and the bandwidth required by the board.
Example 3
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate, all or part of the processes in the methods of the above embodiments may be implemented by a computer program to instruct related hardware, and when the program is executed, the processes may include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A method for allocating PCIE channel bandwidth is characterized by comprising the following steps:
writing the digital quasi-potential voltage value, the board card type and the bandwidth required by the board card for establishing the mapping relation into a board card bandwidth mapping table;
executing a resistance ratio obtaining step according to the digital level voltage value, and configuring a first bandwidth identification device according to an execution result of the resistance ratio obtaining step;
the first bandwidth identification device is arranged on a board card, and an ADC is arranged in a BMC;
executing a binary level voltage value acquisition step through the BMC, the ADC and the first bandwidth identification device to acquire a binary level voltage value;
executing a quasi-position voltage value comparison step according to the digital quasi-position voltage value and the binary quasi-position voltage value, and acquiring and recording the board card type and the bandwidth required by the board card by the BMC according to an execution result of the quasi-position voltage value comparison step;
and the BIOS allocates the bandwidth required by the board card.
2. The method of claim 1, wherein the mapping relationship is: and obtaining the corresponding board card type and the bandwidth required by the board card according to the digital quasi-potential voltage value.
3. The method of claim 1, wherein the obtaining of the resistance ratio further comprises:
setting the voltage of the first bandwidth identification device, and recording the voltage as the voltage of the first bandwidth identification device;
converting the digital level voltage value into an analog voltage value, and recording the analog voltage value as an analog level voltage value;
and calculating the ratio of the resistance value of the first resistor and the resistance value of the second resistor in the first bandwidth identification device according to the voltage of the first bandwidth identification device, the analog level voltage value and a voltage division theorem, and recording the ratio as a first ratio.
4. The method of claim 3, wherein the step of configuring the first bandwidth identification device according to the execution result of the resistance ratio obtaining step further comprises: selecting the first resistor and the second resistor according to the first ratio, and installing the first resistor and the second resistor in the first bandwidth identification device.
5. The method of claim 1, wherein the obtaining of the voltage value of the binary level further comprises: the BMC detects a voltage value of a node between the first resistor and the second resistor to obtain a quasi-level voltage value, and the quasi-level voltage value is converted into a binary quasi-level voltage value through the ADC, and the binary quasi-level voltage value is recorded as a binary quasi-level voltage value.
6. The method of claim 5, wherein the step of comparing the level voltage values further comprises: and the BMC acquires the binary quasi-bit voltage value, and retrieves the digital quasi-bit voltage value which is the same as the binary quasi-bit voltage value from the board card bandwidth mapping table.
7. The method of claim 1, wherein the step of the BIOS allocating the bandwidth required by the board further comprises: and the BIOS acquires the board card type recorded in the BMC and the corresponding bandwidth required by the board card, and distributes the bandwidth required by the board card to the board card corresponding to the board card type.
8. A system for allocating PCIE channel bandwidth, comprising: the system comprises a BMC, a board card and a board card bandwidth allocation module;
the BMC is respectively connected with the board card and the board card bandwidth allocation module;
the BMC includes: the device comprises a mapping table establishing module, a resistance ratio acquiring module, a setting module, an ADC and a board card bandwidth acquiring module;
the board card is provided with a first bandwidth identification device;
the first bandwidth identification device is connected with the ADC;
the mapping table establishing module is used for writing the digital level voltage value for establishing the mapping relation, the board card type and the bandwidth required by the board card into a board card bandwidth mapping table;
the resistance ratio acquisition module is used for acquiring the resistance ratio in the first bandwidth identification device;
the setting module is used for setting the first bandwidth identification device on the board card and setting the ADC in the BMC;
the ADC is used for converting the voltage value measured from the first bandwidth identification device into a binary quasi-bit voltage value;
the board card bandwidth obtaining module is used for obtaining the board card type and the bandwidth required by the board card;
the board bandwidth allocation module is used for allocating the bandwidth required by the board.
9. The system according to claim 8, wherein the board bandwidth obtaining module includes: the device comprises a reference voltage value comparison module and a bandwidth acquisition recording module;
the quasi-position voltage value comparison module is used for retrieving the digital quasi-position voltage value which is the same as the binary quasi-position voltage value from the board card bandwidth mapping table;
the bandwidth acquiring and recording module is used for acquiring and recording the board card type and the required bandwidth of the board card corresponding to the retrieved digital level voltage value.
10. A computer readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method steps of allocating PCIE channel bandwidth of any one of claims 1 to 7.
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