CN216719081U

CN216719081U - Server testing arrangement based on SOC chip

Info

Publication number: CN216719081U
Application number: CN202220155932.3U
Authority: CN
Inventors: 王云胜
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-06-10
Anticipated expiration: 2032-01-20

Abstract

The utility model relates to the field of server testing, and particularly discloses a server testing device based on an SOC chip, which comprises a board card, wherein the board card is provided with the SOC chip and a power supply conversion chip for providing various power supplies; the serial clock line and the serial data line of the I2C protocol are led out from the SOC chip, and the end parts of the serial clock line and the serial data line are provided with a plug interface to be connected with a board to be tested for data transmission between the SOC chip and the board to be tested; the power conversion chip is led out of a plurality of power lines, each power line corresponds to one power supply, and the end part of each power line is provided with a plug-pull interface to be connected with a board to be tested so as to provide power for the board to be tested. The device reduces the complexity of the test of the small server board card I2C, saves the test time, reduces the workload of testers, reduces the test cost, and improves the test efficiency and the test effectiveness.

Description

Server testing arrangement based on SOC chip

Technical Field

The utility model relates to the field of server testing, in particular to a server testing device based on an SOC chip.

Background

Currently, as the trend of server customization increases, the number of server boards increases sharply, and the I2C functional test on the server boards is a necessary test item for the server boards. After the data of the server board card is increased, great inconvenience is brought to the server board card test. The current I2C test on the server board card is complex, long in test time and low in efficiency. Therefore, it is necessary to develop a testing apparatus to reduce the testing complexity and improve the testing efficiency.

Disclosure of Invention

In order to solve the problems, the utility model provides the server testing device based on the SOC chip, which reduces the complexity of the I2C test of the server small board card, saves the testing time, reduces the workload of testing personnel, reduces the testing cost, and improves the testing efficiency and the testing effectiveness.

The technical scheme of the utility model is as follows: a server testing device based on an SOC chip comprises a board card, wherein the board card is provided with the SOC chip and a power conversion chip for providing various power supplies;

the SOC chip leads out a serial clock line and a serial data line, and the end parts of the serial clock line and the serial data line are provided with a plug interface to be connected with a board to be tested for data transmission between the SOC chip and the board to be tested;

the power conversion chip is led out with a plurality of power lines, each power line corresponds to a power supply, and the end part of each power line is provided with a plug interface to be connected with a board card to be tested so as to provide power for the board card to be tested.

Further, the power conversion chip provides 12V, 5V and 3.3V power.

Further, when the board card to be tested is the backboard, a 12V power line led out by the power conversion chip is connected with the power chip on the backboard, and a serial clock line and a serial data line led out by the SOC chip are connected with the memory on the backboard to acquire FRU information of the backboard or connected with the temperature sensor on the backboard to acquire the temperature of the backboard.

Further, when the board card to be tested is the adapter plate, a 5V power line led out by the power conversion chip is connected with the power chip on the adapter plate, and a serial clock line and a serial data line led out by the SOC chip are connected with a memory on the adapter plate to acquire FRU information of the adapter plate or connected with a temperature sensor on the adapter plate to acquire the temperature of the adapter plate.

Further, a temperature sensor is further arranged on the board card.

Further, when the board card to be tested is an IO board, a 3.3V power line led out by the power conversion chip is connected with a power chip on the IO board, a serial clock line and a serial data line led out by the SOC chip are connected with one end of an I2C line on the IO board, and the other end of the I2C line is connected with a temperature sensor on the board card.

According to the SOC chip-based server testing device provided by the utility model, SCL and SDA signals of an I2C protocol are led out through an SOC chip, and meanwhile, a VR chip is used for leading out a common power supply of a server board card, so that reading and writing of FRU information of the server board card and detection testing of the temperature range of the server board card are realized, and a low-cost and high-reliability temperature chip of an I2C protocol is preferably added for I2C load equipment in a special scene to detect the temperature of the I2C load equipment, so that whether the I2C load equipment is accessed or not is further tested. The board card and the board card to be tested are automatically plugged and unplugged through the plugging interface, so that the complexity of the function test of the server small board card I2C is reduced, the test time is saved, the workload of testers is reduced, the test cost is reduced, and the test efficiency and the test effectiveness are improved.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic block diagram of a server testing device based on an SOC chip according to the present invention.

Fig. 2 is a schematic block diagram of a connection structure between a server testing device based on an SOC chip and a backplane provided in the present invention.

Fig. 3 is a schematic block diagram of a connection structure between a server testing device based on an SOC chip and an interposer provided in the present invention.

Fig. 4 is a schematic block diagram of a connection structure between a server testing device based on an SOC chip and an IO board backplane provided by the present invention.

In the figure, 100-board card, 101-SOC chip, 102-power conversion chip, 103-plug interface, 104-backboard, 105-adapter board, 106-IO board and 107-temperature sensor on the board card 100.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

As shown in fig. 1, the server testing apparatus based on a System On Chip (SOC) Chip provided in this embodiment includes a board 100, where the board 100 is provided with an SOC Chip 101 and a Voltage conversion (VR) Chip 102, and the power conversion Chip 102 provides multiple power supplies for using various server boards 100.

The serial clock line (SCL line) and the serial data line (SDA line) of the I2C protocol are led out from the SOC chip 101, and the ends of the serial clock line and the serial data line are provided with a plug interface 103 to be connected with the board under test for data transmission between the SOC chip 101 and the board under test. The plug-in interface 103 is plugged with the board card to be tested, so that the operation convenience is improved. Meanwhile, the SOC chip 101 communicates with the board card to be tested through the serial clock line and the serial data line to obtain the I2C device information of the board card to be tested, thereby implementing the I2C function test of the board card to be tested.

The power conversion chip 102 is led out a plurality of power lines, each power line corresponds to a power supply, and the end of each power line is provided with a plug-pull interface 103 to be connected with a board to be tested so as to provide power for the board to be tested. The plug-in interface 103 is plugged with the board card to be tested, so that the operation convenience is improved. The power conversion chip 102 on the board 100 provides power for the board to be tested to start the board to be tested, so that the test is normally performed.

It should be noted that the board 100 is powered by an external power supply device to the SOC chip 101 and the power conversion chip 102, and the power conversion chip 102 converts the externally supplied power into a plurality of power supplies. In order to adapt to different boards to be tested, the power conversion chip 102 can provide three power supplies, namely 12V power supply, 5V power supply and 3.3V power supply. It can be understood that, in order to provide power for the board to be tested, a ground wire is further led out from the board 100 to be connected with the power chip on the board to be tested, so as to provide a ground signal for the power chip on the board to be tested. In addition, the SOC chip 101 also provides a ground line, and is connected to the I2C device or the I2C line on the board to be tested, so as to provide a ground signal for the I2C device or the I2C line of the board to be tested.

As shown in fig. 2, when the board to be tested is an I2C board of a high-power external device such as a backplane 104, the normal power-on of the board to be tested is ensured by the 12V power supply of the board 100. Taking the backplane 104 as an example, a 12V power line led out by the power conversion chip 102 is connected to a power chip on the backplane 104, and a serial clock line and a serial data line led out by the SOC chip 101 are connected to a memory on the backplane 104 to acquire FRU information of the backplane 104 or connected to a temperature sensor on the backplane 104 to acquire the temperature of the backplane 104. The tester chooses to read the FRU signal or obtain temperature information as needed. If the I2C function test is performed by reading FRU information, the serial clock line and the serial data line led out from the SOC chip 101 are connected to the memory on the backplane 104 to obtain FRU (Field replaceable Unit) information in the memory, and if the FRU information is normally obtained, the I2C function is normal. If the I2C function test is performed by temperature detection, the serial clock line and the serial data line led out from the SOC chip 101 are connected to the temperature sensor on the backplane 104 to acquire the detected temperature, and if the detected temperature is normally acquired, the I2C function is normal.

As shown in fig. 3, when the board to be tested is an I2C board of a universal 5V external device such as the interposer 105, the normal power-on of the board to be tested is ensured by the 5V power supply of the board 100. Taking the adapter board 105 as an example, the 5V power line led out from the power conversion chip 102 is connected to the power chip on the adapter board 105, and the serial clock line and the serial data line led out from the SOC chip 101 are connected to the memory on the adapter board 105 to obtain the FRU information of the adapter board 105 or connected to the temperature sensor on the adapter board 105 to obtain the temperature of the adapter board 105. The testing principle is similar to that of the back plate 104.

It can be understood that, based on the device, the FRU information burning of the back plate 104, the adapter plate 105 and the like can also be realized.

As shown in fig. 4, when the board to be tested is an I2C board of a low-power external device such as the IO board 106, taking the IO board 106 as an example, the IO board 106 is only used for signal transfer, and does not have an I2C device, so the temperature sensor 107 is arranged on the board 100, the I2C line of the IO board 106 is connected with the temperature sensor 107, and the SOC chip 101 on the board 100 acquires temperature detection data of the temperature sensor 107 to determine whether the I2C line on the IO board 106 is connected. Wherein the temperature sensor 107 on the board 100 can be an EMC1413 type sensor. The board card to be tested is normally powered on through the 3V power supply of the board card 100. Taking the IO board 106 as an example, a 3.3V power line led out from the power conversion chip 102 is connected to a power chip on the IO board 106, a serial clock line and a serial data line led out from the SOC chip 101 are connected to one end of an I2C line on the IO board 106, and the other end of the I2C line is connected to the temperature sensor 107 on the board card 100. The SOC chip 101 acquires the detection data of the temperature sensor 107, and if the detection data can be normally acquired, the I2C line of the IO board 106 is normal, and the I2C function is normal.

The above disclosure is only for the preferred embodiments of the present invention, but the present invention is not limited thereto, and any non-inventive changes that can be made by those skilled in the art and several modifications and amendments made without departing from the principle of the present invention shall fall within the protection scope of the present invention.

Claims

1. A server testing device based on an SOC chip is characterized by comprising a board card, wherein the board card is provided with the SOC chip and a power conversion chip for providing various power supplies;

a serial clock line and a serial data line of an I2C protocol are led out from the SOC chip, and the end parts of the serial clock line and the serial data line are provided with a plug interface to be connected with a board to be tested for data transmission between the SOC chip and the board to be tested;

2. The SOC chip based server test apparatus of claim 1, wherein the power conversion chip provides 12V, 5V and 3.3V power.

3. The SOC chip-based server testing device of claim 2, wherein when the board to be tested is a backplane, a 12V power line led out by the power conversion chip is connected with a power chip on the backplane, and a serial clock line and a serial data line led out by the SOC chip are connected with a memory on the backplane to acquire FRU information of the backplane or connected with a temperature sensor on the backplane to acquire backplane temperature.

4. The SOC chip-based server testing device as recited in claim 2, wherein when the board to be tested is an adapter board, a 5V power line led out from a power conversion chip is connected with the power chip on the adapter board, and a serial clock line and a serial data line led out from the SOC chip are connected with a memory on the adapter board to acquire FRU information of the adapter board or connected with a temperature sensor on the adapter board to acquire the temperature of the adapter board.

5. The SOC chip-based server testing apparatus of claim 2, wherein the board card is further provided with a temperature sensor running I2C protocol.

6. The SOC chip-based server testing device as claimed in claim 5, wherein when the board to be tested is an IO board, a 3.3V power line led out by the power conversion chip is connected to a power chip on the IO board, a serial clock line and a serial data line led out by the SOC chip are connected to one end of an I2C line on the IO board, and the other end of the I2C line is connected to a temperature sensor on the board.