CN116166486A - Chip mass production testing method and system - Google Patents

Chip mass production testing method and system Download PDF

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Publication number
CN116166486A
CN116166486A CN202211646128.6A CN202211646128A CN116166486A CN 116166486 A CN116166486 A CN 116166486A CN 202211646128 A CN202211646128 A CN 202211646128A CN 116166486 A CN116166486 A CN 116166486A
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chip
platform
protocol
test program
tested
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梁永元
黄明强
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Zhuhai Amicro Semiconductor Co Ltd
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Zhuhai Amicro Semiconductor Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/36—Software reuse
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/76—Adapting program code to run in a different environment; Porting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
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  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a chip mass production test method and a system, wherein the test method comprises the following steps: step S1, based on a bus protocol and a bus protocol library of a chip to be tested, an upper computer carries out protocol processing on a test program to obtain a protocol-processed test program; step S2, based on the type of the ATE platform and an ATE platform vector library, the upper computer carries out the platformization of the test program after the protocol is carried out, and the test program after the platformization is obtained; step S3, the upper computer transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, the test program after platform meets the operation requirement of the current ATE platform, and the chip to be tested receives the test program processed by the ATE platform through the bus interface. The test method is particularly suitable for chip mass production test, and greatly reduces the cost required by chip test.

Description

Chip mass production testing method and system
Technical Field
The application relates to the field of chip testing, in particular to a chip mass production testing method and system.
Background
The chips are subjected to mass production test by a testing factory before production and delivery, and the chips with defects are further processed to ensure that the chips delivered to customers are good products with good characteristic parameters and good functions. Currently, each manufacturer can push out ATE automatic testing machines with different performances and resources for chips in different application fields so as to test the chips. However, in the current chip test method, when a test mode is designed, an IO port with an excessive number of common functions is required to be used as a test mode pin, so that an ATE automatic test machine cannot save channel resources, the number of chips which can be tested at the same time is reduced, and the test cost cannot be adjusted down. In addition, test items and test patterns cannot be reused among different ATE automatic testers, so that the difficulty in test development is high, and testers are required to have the capability of mastering various test tools. And the test modes of DFT designs of different chips are different, and the test scheme is incompatible, so that the test codes are repeated and the efficiency is low.
Disclosure of Invention
The application provides a chip mass production test method and system, and the specific technical scheme is as follows:
a chip mass production testing method specifically comprises the following steps: step S1, based on a bus protocol and a bus protocol library of a chip to be tested, an upper computer carries out protocol processing on a test program to obtain a protocol-processed test program; step S2, based on the type of the ATE platform and an ATE platform vector library, the upper computer carries out the platformization of the test program after the protocol is carried out, and the test program after the platformization is obtained; step S3, the upper computer transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, the test program after platform meets the operation requirement of the current ATE platform, and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
Further, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin.
Further, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
Further, the method for obtaining the test program after the protocol specifically includes the steps of: the upper computer detects a bus protocol of the chip to be tested, sends a read-write request to the chip to be tested, judges that the chip to be tested uses an SWD protocol if the chip returns a preset level signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol; if the chip returns a low-level ACK signal, judging that the chip to be tested uses an IIC protocol, and then inserting a frame head and a frame tail into a test program by an upper computer to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol.
Further, when the chip to be tested uses SWD protocol, the frame header specifically includes: resetting the chip to be tested; controlling the chip to be tested to enter a debugging mode; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory.
Further, when the chip to be tested uses the IIC protocol, the frame header specifically includes: generating an IIC protocol start signal; designating an address frame of a chip to be tested and an address frame of an accessed register or memory; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: generating an IIC protocol ending signal; after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory.
Further, the ATE platform vector library comprises at least one of 93K ATE platform function, J750 ATE platform function and 3380D ATE platform function.
Further, the method for obtaining the test program after the platfonn by the upper computer to platfonn the test program after the protocol specifically comprises the following steps: the upper computer detects the type of the current ATE platform, then calls a 93K ATE platform function or a J750 ATE platform function or a 3380D ATE platform function in an ATE platform vector library according to the type of the current ATE platform, and inserts a specified instruction column, a time column and/or a symbol column before and/or after the code column of the test program to obtain a test program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the current ATE platform.
Further, the method for obtaining the test program after the platfonn by the upper computer to platfonn the test program after the protocol specifically comprises the following steps: step A1, an upper computer detects the type of a current ATE platform, and when detecting that the type of the current ATE platform is a 93K ATE platform, the method enters step A2; step A2, the upper computer inserts a time column before a code column of the test program, and then enters step A3; step A3, the upper computer inserts an instruction column in front of the time column to obtain a testing program after being flattened; the testing program after being subjected to the platform treatment meets the operation requirement of a 93K ATE platform.
Further, the method for obtaining the test program after the platfonn by the upper computer to platfonn the test program after the protocol specifically comprises the following steps: step B1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a J750 ATE platform, the upper computer enters step B2; step B2, the upper computer inserts a time column before the code column of the test program, and then enters step B3; step B3, the upper computer inserts a first symbol row in front of the time row, and then enters step B4; step B4, the upper computer inserts an instruction column in front of the column of the first symbol column, and then enters step B5; step B5, the upper computer inserts a second symbol row after the code row to obtain a testing program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the J750 ATE platform.
Further, the method for obtaining the test program after the platfonn by the upper computer to platfonn the test program after the protocol specifically comprises the following steps: step C1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a 3380D ATE platform, the upper computer enters step C2; step C2, the upper computer inserts a first symbol row in front of the code row of the test program, and then enters step C3; step C3, the upper computer inserts a second symbol row after the row of the code row, and then enters step C4; step C4, inserting an instruction column into the upper computer after the second symbol column to obtain a testing program after the platform is formed; the test program after being subjected to the platform meets the operation requirement of the 3380D ATE platform.
The system is used for realizing the chip mass production test method, and comprises an upper computer, an ATE platform and a chip to be tested, wherein the upper computer comprises a bus protocol library and an ATE platform vector library, the bus protocol library is used for carrying out protocol formation on a test program, the test program after protocol formation meets the transmission requirement of a bus protocol of the chip to be tested, the ATE platform vector library is used for carrying out platform formation on the test program, and the test program after platform formation meets the running requirement of the current ATE platform; the ATE platform is connected with the upper computer, receives and processes the testing program after being subjected to the platform treatment, and then sends the testing program to the chip to be tested for chip testing; the chip to be tested is connected with the ATE platform, and receives the test program processed by the ATE platform through the bus interface so as to test the chip.
Further, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested is connected with a digital channel of an SWDCLK tube heel ATE platform through the SWDIO pin and the SWDCLK pin.
Further, the chip to be tested further comprises a reset pin, and the reset pin is connected with a digital channel of the ATE platform and used for controlling the chip to be tested to execute a test.
Further, the bus protocol library comprises an IIC protocol function, when the bus protocol is the IIC protocol, the bus interface is an IIC interface, the IIC interface comprises an SDA pin and an SCLK pin, and the chip to be tested is connected with a digital channel of an ATE platform through the SDA pin and the SCLK pipe heel.
Furthermore, the ATE platform comprises a plurality of freely definable digital channels, wherein the digital channels are connected with bus interfaces of the chips to be tested, and the ATE platform can be connected with the chips to be tested with different bus interfaces through the digital channels.
According to the chip mass production test method, the test program is subjected to protocol processing through the bus protocol library, and the protocol processed test program meets the transmission requirement of the bus protocol of the chip to be tested, so that the test program can be transmitted to the chip to be tested through the bus interface, other IO ports of the chip to be tested do not need to be additionally occupied to serve as test mode pins, and precious pin resources of the chip are saved. Furthermore, channel resources required by testing a single chip by the ATE platform are reduced, so that the ATE platform can test more chips at the same time, maximized site parallel testing is realized, and testing cost is greatly reduced. Meanwhile, the test program is subjected to platform formation through the ATE platform vector library, the operation requirements of different ATE platforms can be met by the test program after platform formation, multiplexing and transplanting of test codes are realized among different ATE platforms, the test development difficulty is greatly reduced, and moreover, a proper ATE platform can be selected according to the test cost and the precision requirements, so that the flexibility of chip test and the test development efficiency are improved. In conclusion, the test system is particularly suitable for chip mass production test, and the cost required by chip test is greatly reduced.
Drawings
Fig. 1 is a flow chart of a method for testing chip mass production according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a chip mass production test system according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a test device with a bus interface of a chip to be tested being an SW-DP interface according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will also be understood that the term "and/or" as used in this application refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this application, the term "if" may be interpreted as "when …" or "upon" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application, the terms "first," "second," "third," etc. are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance. Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
In the current chip test method, when a test mode is designed, an IO port with excessive common functions is required to be used as a test mode pin, so that an ATE automatic tester cannot save channel resources, the number of chips which can be tested at the same time is reduced, and the test cost cannot be adjusted down. In addition, test items and test patterns cannot be reused among different ATE automatic testers, so that the difficulty in test development is high, and testers are required to have the capability of mastering various test tools. And the test modes of DFT designs of different chips are different, and the test scheme is incompatible, so that the test codes are repeated and the efficiency is low.
In order to solve the above problems, an embodiment of the present application provides a method for testing chip mass production, as shown in fig. 1, where the method specifically includes the following steps:
step S1, based on a bus protocol and a bus protocol library of a chip to be tested, an upper computer carries out protocol processing on a test program to obtain a protocol-processed test program;
step S2, based on the type of the ATE platform and an ATE platform vector library, the upper computer carries out the platformization of the test program after the protocol is carried out, and the test program after the platformization is obtained;
step S3, the upper computer transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, the test program after platform meets the operation requirement of the current ATE platform, and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
It should be noted that, the ATE (Automatic Test Equipment) platform refers to an automatic integrated circuit tester in this application, and is a device for detecting the functional integrity of an integrated circuit. The bus protocol library is essentially a library of functions that contains a series of functions that can be extended to convert compiled test programs into a format that meets the transmission requirements of the corresponding bus protocol. The ATE platform vector library is also essentially a library of functions that contains a series of functions that can be extended to transform compiled test programs into a format that conforms to the execution of the corresponding ATE platform.
As one implementation mode, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin. The SW-DP interface (Serial Wire Debug Port) is a programming and debugging interface developed by ARM corporation for ARM processors, through which the bus, and thus the registers, peripheral circuits, and memory units of the CPU, are accessible.
Based on the above embodiment, the method for obtaining the test program after the protocol by the upper computer performing the protocol on the test program specifically includes: the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, if the chip returns a preset level signal, such as a 001 three-bit level signal, the chip to be detected is judged to use the SWD protocol, and then the upper computer inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol.
Based on the above embodiment, when the SWD protocol is used by the chip under test, the frame header specifically includes: resetting the chip to be tested; controlling the chip to be tested to enter a debugging mode; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory. Further, a register or a memory of the chip to be tested may also be read to determine whether the written data is correct. And on the rising edge of SWDCLK, the upper computer serially transmits the test program to the chip to be tested through SWDIO.
As one implementation manner, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
Based on the above embodiment, the method for obtaining the test program after the protocol by the upper computer performing the protocol on the test program specifically includes: the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, judges that the chip to be detected uses an IIC protocol if the chip returns a low-level ACK signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; wherein the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol, and the ACK (ACKnowledge Character, acknowledgement character) signal indicates that the data sent by the acknowledgement is accepted without errors in the transmission of data communication.
Based on the above embodiment, when the chip to be tested uses the IIC protocol, the frame header specifically includes: generating an IIC protocol start signal; designating an address frame of a chip to be tested and an address frame of an accessed register or memory; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: generating an IIC protocol ending signal; after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory. The IIC protocol starting signal is generated by changing the SDA signal from a high level to a low level when the SCLK signal is at a high level. The end signal of the IIC protocol is generated by changing the SDA signal from a low level to a high level when the SCLK signal is at a high level. Waiting for preset time, reserving response time for writing operation, ensuring that after the test program is successfully written, the ATE platform controls the chip to be tested to be electrified again, so that the chip to be tested is reset, and then executing the test program from a register or a memory to realize chip test.
According to the chip mass production test method, the test program is subjected to protocol processing through the bus protocol library, and the protocol processed test program meets the transmission requirement of the bus protocol of the chip to be tested, so that the test program can be transmitted to the chip to be tested through the bus interface, other IO ports of the chip to be tested do not need to be additionally occupied to serve as test mode pins, and precious pin resources of the chip are saved.
As one implementation, the ATE platform vector library includes at least one of 93K ATE platform function, J750 ATE platform function, and 3380D ATE platform function. The ATE platform vector library is essentially a library of functions that contains a series of functions that can be extended to transform compiled test programs into a format that conforms to the execution of the corresponding ATE platform.
As one embodiment, the method for obtaining the test program after being flattened by the upper computer specifically includes: the upper computer detects the type of the current ATE platform, then calls a 93K ATE platform function or a J750 ATE platform function or a 3380D ATE platform function in an ATE platform vector library according to the type of the current ATE platform, and inserts a specified instruction column, a time column and/or a symbol column before and/or after the code column of the test program to obtain a test program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the current ATE platform.
Based on the foregoing embodiments, the present application provides an embodiment, where the method for the host computer to platform the test program to obtain the platform test program specifically includes: step A1, an upper computer detects the type of a current ATE platform, and when detecting that the type of the current ATE platform is a 93K ATE platform, the method enters step A2; step A2, the upper computer inserts a time column before a code column of the test program, and then enters step A3; step A3, the upper computer inserts an instruction column in front of the time column to obtain a testing program after being flattened; the testing program after being subjected to the platform treatment meets the operation requirement of a 93K ATE platform.
Based on the foregoing embodiments, the present application provides another embodiment, where the method for the host computer to platform the test program to obtain the platform test program specifically includes: step B1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a J750 ATE platform, the upper computer enters step B2; step B2, the upper computer inserts a time column before the code column of the test program, and then enters step B3; step B3, the upper computer inserts a first symbol row in front of the time row, and then enters step B4; step B4, the upper computer inserts an instruction column in front of the column of the first symbol column, and then enters step B5; step B5, the upper computer inserts a second symbol row after the code row to obtain a testing program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the J750 ATE platform.
Based on the foregoing embodiments, the present application provides another embodiment, where the method for the host computer to platform the test program to obtain the platform test program specifically includes: step C1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a 3380D ATE platform, the upper computer enters step C2; step C2, the upper computer inserts a first symbol row in front of the code row of the test program, and then enters step C3; step C3, the upper computer inserts a second symbol row after the row of the code row, and then enters step C4; step C4, inserting an instruction column into the upper computer after the second symbol column to obtain a testing program after the platform is formed; the test program after being subjected to the platform meets the operation requirement of the 3380D ATE platform.
It should be noted that the instruction sequence, the time sequence, and the symbol sequence may have different expressions on different ATE platforms. For example, on a 93K ATE platform, instruction R2 indicates that the code of the current line is executed twice repeatedly, while on a J750 ATE platform, the code of the current line needs to be written as repeat2. The writing of specific instruction sequences, time sequences, and symbol sequences is not limited in this application, as long as the operational requirements of different ATE platforms are met. In particular, in an instruction column, if a row of code is not given a corresponding instruction, the instruction for that row may be omitted from writing.
According to the chip testing method suitable for different ATE platforms, the testing program is subjected to platform formation through the ATE platform vector library, the testing program after platform formation can meet the operation requirements of different ATE platforms, multiplexing and transplanting of testing codes are achieved among various different ATE platforms, the testing development difficulty is greatly reduced, and moreover, a proper ATE platform can be selected according to the testing cost and the precision requirements, so that the flexibility of chip testing and the testing development efficiency are improved.
Referring to fig. 2, an embodiment of the present application provides a chip mass production test system, where the system is configured to implement the foregoing chip mass production test method, and the system includes a host computer, an ATE platform, and a chip to be tested, where the host computer includes a bus protocol library and an ATE platform vector library, the bus protocol library is configured to protocol a test program, the protocol test program meets a transmission requirement of a bus protocol of the chip to be tested, the ATE platform vector library is configured to platform the test program, and the platform test program meets an operation requirement of a current ATE platform; the ATE platform is connected with the upper computer, receives and processes the testing program after being subjected to the platform treatment, and then sends the testing program to the chip to be tested for chip testing; the chip to be tested is connected with the ATE platform, and receives the test program processed by the ATE platform through the bus interface so as to test the chip.
As one embodiment, the host computer and the ATE platform communicate with each other through a GPIB interface (General-Purpose Interface Bus, universal instrument bus) or a USB interface. In one embodiment, the host computer is connected to the ATE platform through a GPIB interface, and further, the host computer detects the type of the ATE platform through the GPIB interface. Each ATE platform contains a unique address associated with its GPIB interface, so that based on that address, the host computer can automatically detect the type of ATE platform to which it is connected.
As one implementation manner, referring to fig. 3, the bus protocol library includes a SWD protocol function, when the bus protocol is a SWD protocol, the bus interface is a SW-DP interface, the SW-DP interface includes a SWDIO pin and a SWDCLK pin, and the chip to be tested is connected through a digital channel of the SWDIO pin and the SWDCLK tube heel ATE platform. The chip to be tested also comprises a reset pin nRST, and the reset tube is connected with a digital channel of the ATE platform and is used for controlling the chip to be tested to execute a test.
As one implementation manner, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested is connected through a digital channel of the SDA pin and the SCLK tube heel ATE platform. It should be noted that, when the bus interface of the chip to be tested is an IIC interface, the reset pin is not required to be connected, i.e. only two pins are required to be used for testing the chip to be tested.
Based on the above embodiment, referring to fig. 3, the ATE platform includes a plurality of freely definable digital channels, the digital channels are connected with bus interfaces of the chip to be tested, and the ATE platform may be connected with the chip to be tested having different bus interfaces through the digital channels at the same time. In an embodiment, the chip 1 to be tested is connected with three digital channels of the heel ATE platform of the reset tube by using the SWD protocol, and the chip 2 to be tested is connected with two digital channels of the heel ATE platform of the SCLK tube by using the IIC protocol. The upper computer carries out protocol processing on the test program according to different bus interfaces, converts the test program into a format meeting the transmission requirements of different bus protocols, and then transmits the format to the corresponding chip to be tested through the ATE platform. After receiving the test program subjected to the protocol of the upper computer, the ATE platform analyzes the test program, generates corresponding test waveforms through a digital channel internal circuit of the ATE platform and transmits the corresponding test waveforms to the chip to be tested. The chip to be tested receives the test waveform through the bus interface, so that the chip to be tested can execute various tests according to the test waveform. In this embodiment, assuming that the ATE platform has 192 digital channels, for example, a chip to be tested using the SW-DP interface may be tested at the same time as 64site (station), for example, a chip to be tested using the IIC interface may be tested at the same time as 96 site. The method reduces channel resources required by testing a single chip by the ATE platform, enables the ATE platform to test more chips simultaneously, realizes maximized site parallel test, and greatly reduces test cost.
The embodiment of the application provides a computer storage medium which stores the steps of the chip mass production test method. When the chip mass production test method is executed, the test program is subjected to protocol processing through the bus protocol library, and the protocol processed test program meets the transmission requirement of the bus protocol of the chip to be tested, so that the test program can be transmitted into the chip to be tested through the bus interface, other IO ports of the chip to be tested are not required to be additionally occupied to serve as test mode pins, and precious pin resources of the chip are saved. Furthermore, channel resources required by testing a single chip by the ATE platform are reduced, so that the ATE platform can test more chips at the same time, maximized site parallel testing is realized, and testing cost is greatly reduced. Meanwhile, the test program is subjected to platform formation through the ATE platform vector library, the operation requirements of different ATE platforms can be met by the test program after platform formation, multiplexing and transplanting of test codes are realized among different ATE platforms, the test development difficulty is greatly reduced, and moreover, a proper ATE platform can be selected according to the test cost and the precision requirements, so that the flexibility of chip test and the test development efficiency are improved. In conclusion, the test system is particularly suitable for chip mass production test, and the cost required by chip test is greatly reduced.
Those skilled in the art will appreciate that implementing all or part of the above described embodiment methods may be accomplished by way of a computer program stored in a non-transitory computer readable storage medium, which when executed, may comprise the steps of embodiments of the above described methods. References to memory, storage, databases, or other media used in the various embodiments provided herein may include non-volatile and/or volatile memory. The non-volatile memory may include read-only memory ROM, programmable memory PROM, electrically programmable memory DPROM, electrically erasable programmable memory DDPROM, or flash memory. Volatile memory can include random access memory RAM or external cache memory.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing embodiments are merely representative of several embodiments of the invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application.

Claims (16)

1. The chip mass production testing method is characterized by comprising the following steps of:
step S1, based on a bus protocol and a bus protocol library of a chip to be tested, an upper computer carries out protocol processing on a test program to obtain a protocol-processed test program;
step S2, based on the type of the ATE platform and an ATE platform vector library, the upper computer carries out the platformization of the test program after the protocol is carried out, and the test program after the platformization is obtained;
step S3, the upper computer transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip;
the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, the test program after platform meets the operation requirement of the current ATE platform, and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
2. The method for testing chip mass production according to claim 1, wherein the bus protocol library comprises an SWD protocol function, and when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin.
3. The method for testing chip mass production according to claim 1, wherein the bus protocol library comprises an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface comprises an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
4. The method for testing mass production of chips as defined in claim 2 or 3, wherein said upper computer agrees with said test program to obtain an agreed test program, said method comprising:
the upper computer detects a bus protocol of the chip to be tested, sends a read-write request to the chip to be tested, judges that the chip to be tested uses an SWD protocol if the chip returns a preset level signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol;
if the chip returns a low-level ACK signal, judging that the chip to be tested uses an IIC protocol, and then inserting a frame head and a frame tail into a test program by an upper computer to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol.
5. The method for testing mass production of chips as defined in claim 4, wherein when said chip to be tested uses SWD protocol, said frame header specifically comprises:
resetting the chip to be tested;
controlling the chip to be tested to enter a debugging mode;
writing a test program into a register or a memory of the chip to be tested;
the frame tail specifically comprises:
and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory.
6. The method for testing mass production of chips as defined in claim 4, wherein when the chip to be tested uses IIC protocol, the frame header specifically comprises:
generating an IIC protocol start signal;
designating an address frame of a chip to be tested and an address frame of an accessed register or memory;
writing a test program into a register or a memory of the chip to be tested;
the frame tail specifically comprises:
generating an IIC protocol ending signal;
after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory.
7. The method of claim 1, wherein the ATE platform vector library comprises at least one of 93K ATE platform function, J750 ATE platform function, and 3380D ATE platform function.
8. The method for mass production testing of chips as defined in claim 7, wherein said upper computer performs a platfonn on said protocol-processed test program, and said method for obtaining a platfonn test program comprises:
the upper computer detects the type of the current ATE platform, then calls a 93K ATE platform function or a J750 ATE platform function or a 3380D ATE platform function in an ATE platform vector library according to the type of the current ATE platform, and inserts a specified instruction column, a time column and/or a symbol column before and/or after the code column of the test program to obtain a test program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the current ATE platform.
9. The method for testing mass production of chips as defined in claim 8, wherein said upper computer performs a platfonn on said protocol-processed test program, and said method for obtaining said platfonn test program comprises:
step A1, an upper computer detects the type of a current ATE platform, and when detecting that the type of the current ATE platform is a 93K ATE platform, the method enters step A2;
step A2, the upper computer inserts a time column before a code column of the test program, and then enters step A3;
step A3, the upper computer inserts an instruction column in front of the time column to obtain a testing program after being flattened; the testing program after being subjected to the platform treatment meets the operation requirement of a 93K ATE platform.
10. The method for testing mass production of chips as defined in claim 8, wherein said upper computer performs a platfonn on said protocol-processed test program, and said method for obtaining said platfonn test program comprises:
step B1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a J750 ATE platform, the upper computer enters step B2;
step B2, the upper computer inserts a time column before the code column of the test program, and then enters step B3;
step B3, the upper computer inserts a first symbol row in front of the time row, and then enters step B4;
step B4, the upper computer inserts an instruction column in front of the column of the first symbol column, and then enters step B5;
step B5, the upper computer inserts a second symbol row after the code row to obtain a testing program after the platform is formed; the testing program after being subjected to the platform treatment meets the operation requirement of the J750 ATE platform.
11. The method for testing mass production of chips as defined in claim 8, wherein said upper computer performs a platfonn on said protocol-processed test program, and said method for obtaining said platfonn test program comprises:
step C1, the upper computer detects the type of the current ATE platform, and when detecting that the type of the current ATE platform is a 3380D ATE platform, the upper computer enters step C2;
step C2, the upper computer inserts a first symbol row in front of the code row of the test program, and then enters step C3;
step C3, the upper computer inserts a second symbol row after the row of the code row, and then enters step C4;
step C4, inserting an instruction column into the upper computer after the second symbol column to obtain a testing program after the platform is formed; the test program after being subjected to the platform meets the operation requirement of the 3380D ATE platform.
12. A chip mass production test system is characterized in that the system is used for realizing the chip mass production test method according to any one of claims 1-11, and comprises an upper computer, an ATE platform and a chip to be tested, wherein,
the upper computer comprises a bus protocol library and an ATE platform vector library, wherein the bus protocol library is used for carrying out protocol on a test program, the protocol-carried test program meets the transmission requirement of a bus protocol of a chip to be tested, the ATE platform vector library is used for carrying out platform formation on the test program, and the platform-carried test program meets the running requirement of the current ATE platform;
the ATE platform is connected with the upper computer, receives and processes the testing program after being subjected to the platform treatment, and then sends the testing program to the chip to be tested for chip testing;
the chip to be tested is connected with the ATE platform, and receives the test program processed by the ATE platform through the bus interface so as to test the chip.
13. The chip volume production test system of claim 12, wherein the bus protocol library comprises SWD protocol functions, the bus interface is a SW-DP interface when the bus protocol is a SWD protocol, the SW-DP interface comprises a SWDIO pin and a SWDCLK pin, and the chip under test is connected through a digital channel of the SWDIO pin and the SWDCLK tube heel ATE platform.
14. The chip volume production test system of claim 13, wherein the chip to be tested further comprises a reset pin, the reset pin being connected to a digital channel of the ATE platform for controlling the chip to be tested to perform a test.
15. The chip mass production test system of claim 12, wherein the bus protocol library comprises IIC protocol function, and when the bus protocol is IIC protocol, the bus interface is IIC interface, the IIC interface comprises SDA pin and SCLK pin, and the chip to be tested is connected through digital channels of SDA pin and SCLK tube heel ATE platform.
16. The chip mass production test system of claim 13 or 15, wherein the ATE platform comprises a plurality of freely definable digital channels, the digital channels are connected with bus interfaces of the chip under test, and the ATE platform can be simultaneously connected with the chip under test having different bus interfaces through the digital channels.
CN202211646128.6A 2022-12-21 2022-12-21 Chip mass production testing method and system Pending CN116166486A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117783835A (en) * 2024-02-26 2024-03-29 北京力通通信有限公司 System and method for rapidly testing batch concurrency of radio frequency transceiver chips
CN117783835B (en) * 2024-02-26 2024-05-31 北京力通通信有限公司 System and method for rapidly testing batch concurrency of radio frequency transceiver chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117783835A (en) * 2024-02-26 2024-03-29 北京力通通信有限公司 System and method for rapidly testing batch concurrency of radio frequency transceiver chips
CN117783835B (en) * 2024-02-26 2024-05-31 北京力通通信有限公司 System and method for rapidly testing batch concurrency of radio frequency transceiver chips

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