CN116148629A - Chip testing method, device and system - Google Patents
Chip testing method, device and system Download PDFInfo
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- CN116148629A CN116148629A CN202211646246.7A CN202211646246A CN116148629A CN 116148629 A CN116148629 A CN 116148629A CN 202211646246 A CN202211646246 A CN 202211646246A CN 116148629 A CN116148629 A CN 116148629A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a chip testing method, device and system, wherein the chip testing method carries out protocol processing on a testing program through a bus protocol library, the protocol-processed testing program meets the transmission requirement of the bus protocol of a chip to be tested, so that the testing program can be transmitted into the chip to be tested through a bus interface, other IO ports of the chip to be tested do not need to be additionally occupied to serve as test mode pins, and precious pin resources of the chip are saved. Furthermore, channel resources required by testing a single chip by the ATE platform are reduced, so that the ATE platform can test more chips at the same time, maximized site parallel testing is realized, and testing cost is greatly reduced.
Description
Technical Field
The present disclosure relates to the field of chip testing, and in particular, to a method, an apparatus, and a system for testing a chip.
Background
The cost of a chip influences the competitiveness of the product, and the test cost needs to be reduced as much as possible under the condition of a certain chip area. There are two methods for reducing the cost of chip testing: firstly, the test time of each chip is reduced; and secondly, the number of chips tested simultaneously is increased (the number of chips which can be tested simultaneously is determined by the number of channels of the testing equipment). That is, the greater the number of chips tested, the faster the speed, and the lower the test cost. However, in the current chip test method, when the test mode is designed, the IO ports which occupy too many common functions still need to be used as test mode pins, so that the test equipment cannot save channel resources, the number of chips which can be tested at the same time is reduced, and the occupation of too many IO ports is not friendly to small packaged chips.
Disclosure of Invention
The application provides a chip testing method, device and system, and the specific technical scheme is as follows:
a chip testing method specifically comprises the following steps: based on a bus protocol and a bus protocol library of a chip to be tested, the upper computer carries out protocol processing on the test program to obtain a protocol-processed test program, then converts the protocol-processed test program into a test program which can run on a current ATE platform, and transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
Further, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin.
Further, the method for obtaining the test program after the protocol specifically includes the steps of: the upper computer detects a bus protocol of the chip to be tested, sends a read-write request to the chip to be tested, judges that the chip to be tested uses an SWD protocol if the chip returns a preset level signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol.
Further, the frame header specifically includes: resetting the chip to be tested; controlling the chip to be tested to enter a debugging mode; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory.
Further, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
Further, the method for obtaining the test program after the protocol specifically includes the steps of: the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, judges that the chip to be detected uses an IIC protocol if the chip returns a low-level ACK signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol.
Further, the frame header specifically includes: generating an IIC protocol start signal; designating an address frame of a chip to be tested and an address frame of an accessed register or memory; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: generating an IIC protocol ending signal; after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory.
A chip testing apparatus for implementing the chip testing method, the apparatus comprising: the ATE platform is connected with the chip to be tested and used for transmitting a test program meeting the bus protocol transmission requirement of the chip to be tested to the chip to be tested; and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
Further, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested is connected with a digital channel of an SWDCLK tube heel ATE platform through the SWDIO pin and the SWDCLK pin.
Further, the chip to be tested further comprises a reset pin, and the reset pin is connected with a digital channel of the ATE platform and used for controlling the chip to be tested to execute a test.
Further, the bus protocol library comprises an IIC protocol function, when the bus protocol is the IIC protocol, the bus interface is an IIC interface, the IIC interface comprises an SDA pin and an SCLK pin, and the chip to be tested is connected with a digital channel of an ATE platform through the SDA pin and the SCLK pipe heel.
Furthermore, the ATE platform comprises a plurality of freely definable digital channels, wherein the digital channels are connected with bus interfaces of the chips to be tested, and the ATE platform can be connected with the chips to be tested with different bus interfaces through the digital channels.
The system comprises the chip testing device, and further comprises an upper computer connected with the ATE platform, wherein the upper computer comprises a bus protocol library, the bus protocol library is used for carrying out protocol on a testing program, and the protocol-carried testing program meets the transmission requirement of a bus protocol of a chip to be tested.
According to the chip testing method, the test program is subjected to protocol processing through the bus protocol library, the protocol-processed test program meets the transmission requirement of the bus protocol of the chip to be tested, so that the test program can be transmitted to the chip to be tested through the bus interface, other IO ports of the chip to be tested do not need to be additionally occupied as test mode pins, and precious pin resources of the chip are saved. Furthermore, channel resources required by testing a single chip by the ATE platform are reduced, so that the ATE platform can test more chips at the same time, maximized site parallel testing is realized, and testing cost is greatly reduced.
Drawings
Fig. 1 is a flow chart of a chip testing method according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a chip testing apparatus according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a test device with a bus interface of a chip to be tested being an SW-DP interface according to an embodiment of the present application.
Fig. 4 is a schematic diagram of a chip testing system according to an embodiment of the present application.
Detailed Description
The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention. It should be understood that the following detailed description is merely illustrative of the invention, and is not intended to limit the invention.
In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The cost of a chip influences the competitiveness of the product, and the test cost needs to be reduced as much as possible under the condition of a certain chip area. There are two methods for reducing the cost of chip testing: firstly, the test time of each chip is reduced; and secondly, the number of chips tested simultaneously is increased (the number of chips which can be tested simultaneously is determined by the number of channels of the testing equipment). That is, the greater the number of chips tested, the faster the speed, and the lower the test cost. However, in the current chip test method, when the test mode is designed, the IO ports which occupy too many common functions still need to be used as test mode pins, so that the test equipment cannot save channel resources, the number of chips which can be tested at the same time is reduced, and the occupation of too many IO ports is not friendly to small packaged chips.
In order to solve the above problems, an embodiment of the present application provides a chip testing method, as shown in fig. 1, where the testing method specifically includes:
based on a bus protocol and a bus protocol library of a chip to be tested, the upper computer carries out protocol processing on the test program to obtain a protocol-processed test program, then converts the protocol-processed test program into a test program which can run on a current ATE platform, and transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, and the chip to be tested receives the test program processed by the ATE platform through the bus interface. It should be noted that, the ATE (Automatic Test Equipment) platform refers to an automatic integrated circuit tester in this application, and is a device for detecting the functional integrity of an integrated circuit. The bus protocol library is essentially a library of functions that contains a series of functions that can be extended to convert compiled test programs into a format that meets the transmission requirements of the corresponding bus protocol.
As one implementation mode, the bus protocol library comprises an SWD protocol function, when the bus protocol is an SWD protocol, the bus interface is an SW-DP interface, the SW-DP interface comprises an SWDIO pin and an SWDCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin. The SW-DP interface (Serial Wire Debug Port) is a programming and debugging interface developed by ARM corporation for ARM processors, through which the bus, and thus the registers, peripheral circuits, and memory units of the CPU, are accessible.
Based on the above embodiment, the method for obtaining the test program after the protocol by the upper computer performing the protocol on the test program specifically includes: the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, if the chip returns a preset level signal, such as a 001 three-bit level signal, the chip to be detected is judged to use the SWD protocol, and then the upper computer inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol.
Based on the above embodiment, when the SWD protocol is used by the chip under test, the frame header specifically includes: resetting the chip to be tested; controlling the chip to be tested to enter a debugging mode; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory. Further, a register or a memory of the chip to be tested may also be read to determine whether the written data is correct. And on the rising edge of SWDCLK, the upper computer serially transmits the test program to the chip to be tested through SWDIO.
As one implementation manner, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
Based on the above embodiment, the method for obtaining the test program after the protocol by the upper computer performing the protocol on the test program specifically includes: the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, judges that the chip to be detected uses an IIC protocol if the chip returns a low-level ACK signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; wherein the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol, and the ACK (ACKnowledge Character, acknowledgement character) signal indicates that the data sent by the acknowledgement is accepted without errors in the transmission of data communication.
Based on the above embodiment, when the chip to be tested uses the IIC protocol, the frame header specifically includes: generating an IIC protocol start signal; designating an address frame of a chip to be tested and an address frame of an accessed register or memory; writing a test program into a register or a memory of the chip to be tested; the frame tail specifically comprises: generating an IIC protocol ending signal; after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory. The IIC protocol starting signal is generated by changing the SDA signal from a high level to a low level when the SCLK signal is at a high level. The end signal of the IIC protocol is generated by changing the SDA signal from a low level to a high level when the SCLK signal is at a high level. Waiting for preset time, reserving response time for writing operation, ensuring that after the test program is successfully written, the ATE platform controls the chip to be tested to be electrified again, so that the chip to be tested is reset, and then executing the test program from a register or a memory to realize chip test.
According to the chip testing method, the test program is subjected to protocol processing through the bus protocol library, the protocol-processed test program meets the transmission requirement of the bus protocol of the chip to be tested, so that the test program can be transmitted to the chip to be tested through the bus interface, other IO ports of the chip to be tested do not need to be additionally occupied as test mode pins, and precious pin resources of the chip are saved.
Referring to fig. 2, an embodiment of the present application provides a chip testing apparatus, where the apparatus is configured to implement the above chip testing method, and the apparatus includes: the ATE platform is connected with the chip to be tested and used for transmitting a test program meeting the bus protocol transmission requirement of the chip to be tested to the chip to be tested; and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
As one implementation manner, referring to fig. 3, the bus protocol library includes a SWD protocol function, when the bus protocol is a SWD protocol, the bus interface is a SW-DP interface, the SW-DP interface includes a SWDIO pin and a SWDCLK pin, and the chip to be tested is connected through a digital channel of the SWDIO pin and the SWDCLK tube heel ATE platform. The chip to be tested also comprises a reset pin nRST, and the reset tube is connected with a digital channel of the ATE platform and is used for controlling the chip to be tested to execute a test.
As one implementation manner, the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested is connected through a digital channel of the SDA pin and the SCLK tube heel ATE platform. It should be noted that, when the bus interface of the chip to be tested is an IIC interface, the reset pin is not required to be connected, i.e. only two pins are required to be used for testing the chip to be tested.
Based on the above embodiment, referring to fig. 3, the ATE platform includes a plurality of freely definable digital channels, the digital channels are connected with bus interfaces of the chip to be tested, and the ATE platform may be connected with the chip to be tested having different bus interfaces through the digital channels at the same time. In an embodiment, the chip 1 to be tested is connected with three digital channels of the heel ATE platform of the reset tube by using the SWD protocol, and the chip 2 to be tested is connected with two digital channels of the heel ATE platform of the SCLK tube by using the IIC protocol. The upper computer carries out protocol processing on the test program according to different bus interfaces, converts the test program into a format meeting the transmission requirements of different bus protocols, and then transmits the format to the corresponding chip to be tested through the ATE platform. After receiving the test program subjected to the protocol of the upper computer, the ATE platform analyzes the test program, generates corresponding test waveforms through a digital channel internal circuit of the ATE platform and transmits the corresponding test waveforms to the chip to be tested. The chip to be tested receives the test waveform through the bus interface, so that the chip to be tested can execute various tests according to the test waveform. In this embodiment, assuming that the ATE platform has 192 digital channels, for example, a chip to be tested using the SW-DP interface may be tested at the same time as 64site (station), for example, a chip to be tested using the IIC interface may be tested at the same time as 96 site. The method reduces channel resources required by testing a single chip by the ATE platform, enables the ATE platform to test more chips simultaneously, realizes maximized site parallel test, and greatly reduces test cost.
Referring to fig. 4, an embodiment of the present application provides a chip testing system, where the system includes the foregoing chip testing device, and further includes a host computer connected to an ATE platform, where the host computer includes a bus protocol library, and the bus protocol library is configured to protocol a test program, where the protocol test program meets a transmission requirement of a bus protocol of a chip to be tested.
As one embodiment, the host computer and the ATE platform communicate with each other through a GPIB interface (General-Purpose Interface Bus, universal instrument bus interface) or a USB interface. In one embodiment, the host computer is connected to the ATE platform through a GPIB interface, and further, the host computer detects the type of the ATE platform through the GPIB interface. Each ATE platform contains a unique address associated with its GPIB interface, so that based on that address, the host computer can automatically detect the type of ATE platform to which it is connected.
The embodiment of the application provides a computer storage medium which stores the steps of the chip testing method. When the chip testing method is executed, the testing program is subjected to protocol, and the protocol testing program meets the transmission requirement of the bus protocol of the chip to be tested, so that the testing program can be transmitted into the chip to be tested through the bus interface, other IO ports of the chip to be tested are not required to be additionally occupied as testing mode pins, and precious pin resources of the chip are saved. Furthermore, channel resources required by testing a single chip by the ATE platform are reduced, so that the ATE platform can test more chips at the same time, maximized site parallel testing is realized, and testing cost is greatly reduced.
It is obvious that the above-mentioned embodiments are only some embodiments of the present invention, but not all embodiments, and that the technical solutions of the embodiments may be combined with each other. Furthermore, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are used in the embodiments, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience in describing the present invention and simplifying the description, and does not indicate or imply that the indicated apparatus or element must have a specific orientation or be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. If the terms "first," "second," "third," etc. are used in an embodiment to facilitate distinguishing between related features, they are not to be construed as indicating or implying a relative importance, order, or number of technical features.
In addition, in the description of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents, which are to be considered as merely preferred embodiments of the present invention and not as limitations as these to one skilled in the art will be able to make various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. The chip testing method is characterized by comprising the following steps of:
based on a bus protocol and a bus protocol library of a chip to be tested, the upper computer carries out protocol processing on the test program to obtain a protocol-processed test program, then converts the protocol-processed test program into a test program which can run on a current ATE platform, and transmits the test program processed by the ATE platform to the chip to be tested through the ATE platform so as to test the chip; the test program after protocol meets the transmission requirement of the bus protocol of the chip to be tested, and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
2. The method according to claim 1, wherein the bus protocol library includes SWD protocol function, and when the bus protocol is SWD protocol, the bus interface is SW-DP interface, the SW-DP interface includes SWDIO pin and SWDCLK pin, and the chip to be tested receives the test program processed by the ATE platform through the SWDIO pin and the SWDCLK pin.
3. The method for testing a chip according to claim 2, wherein the method for obtaining the test program after the protocol by the host computer comprises the following steps:
the upper computer detects a bus protocol of the chip to be tested, sends a read-write request to the chip to be tested, judges that the chip to be tested uses an SWD protocol if the chip returns a preset level signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the SWD protocol.
4. A method for testing a chip according to claim 3, wherein the frame header specifically comprises:
resetting the chip to be tested;
controlling the chip to be tested to enter a debugging mode;
writing a test program into a register or a memory of the chip to be tested;
the frame tail specifically comprises:
and setting a program execution pointer, and releasing reset to enable the chip to be tested to execute the test program from the register or the memory.
5. The method according to claim 1, wherein the bus protocol library includes an IIC protocol function, and when the bus protocol is an IIC protocol, the bus interface is an IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested receives a test program processed by the ATE platform through the SDA pin and the SCLK pin.
6. The method for testing a chip according to claim 5, wherein the method for obtaining the test program after the protocol by the host computer comprises the following steps:
the upper computer detects a bus protocol of the chip to be detected, sends a read-write request to the chip to be detected, judges that the chip to be detected uses an IIC protocol if the chip returns a low-level ACK signal, and then inserts a frame head and a frame tail into a test program to obtain a test program after protocol; the frame head and the frame tail enable the test program to meet the transmission requirement of the IIC protocol.
7. The method for testing a chip according to claim 6, wherein the frame header specifically comprises:
generating an IIC protocol start signal;
designating an address frame of a chip to be tested and an address frame of an accessed register or memory;
writing a test program into a register or a memory of the chip to be tested;
the frame tail specifically comprises:
generating an IIC protocol ending signal;
after the preset time, sequentially sending a lower electric signal and an upper electric signal to the chip to be tested, so that the chip to be tested executes a test program from a register or a memory.
8. A chip testing apparatus for implementing the chip testing method of any one of claims 1 to 7, the apparatus comprising:
the ATE platform is connected with the chip to be tested and used for transmitting a test program meeting the bus protocol transmission requirement of the chip to be tested to the chip to be tested;
and the chip to be tested receives the test program processed by the ATE platform through the bus interface.
9. The device according to claim 8, wherein the bus protocol library includes SWD protocol function, and when the bus protocol is SWD protocol, the bus interface is SW-DP interface, the SW-DP interface includes SWDIO pin and SWDCLK pin, and the chip under test is connected through digital channels of SWDIO pin and SWDCLK tube heel ATE platform.
10. The device of claim 9, wherein the chip to be tested further comprises a reset pin, and wherein the reset pin is connected to a digital channel of the ATE platform for controlling the chip to be tested to perform the test.
11. The device according to claim 8, wherein the bus protocol library includes IIC protocol function, and when the bus protocol is IIC protocol, the bus interface is IIC interface, the IIC interface includes an SDA pin and an SCLK pin, and the chip to be tested is connected through a digital channel of the SDA pin and the SCLK tube heel ATE platform.
12. A chip testing apparatus according to claim 9 or 11, wherein the ATE platform comprises a plurality of freely definable digital channels, the digital channels being connected to bus interfaces of the chip under test, the ATE platform being connectable to the chip under test having different bus interfaces simultaneously through the digital channels.
13. A chip testing system, characterized in that the system comprises the chip testing device according to any one of claims 8-12, the system further comprises a host computer connected with the ATE platform, the host computer comprises a bus protocol library, the bus protocol library is used for carrying out protocol processing on a testing program, and the protocol-processed testing program meets the transmission requirement of a bus protocol of a chip to be tested.
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| CN202211646246.7A CN116148629A (en) | 2022-12-21 | 2022-12-21 | Chip testing method, device and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116860536A (en) * | 2023-09-05 | 2023-10-10 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116860536A (en) * | 2023-09-05 | 2023-10-10 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
| CN116860536B (en) * | 2023-09-05 | 2023-11-28 | 武汉凌久微电子有限公司 | Rapid FT test system, test equipment and test method of GPU chip |
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