CN104461805A - CPLD-based system state detecting method, CPLD and server mainboard - Google Patents
CPLD-based system state detecting method, CPLD and server mainboard Download PDFInfo
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- CN104461805A CN104461805A CN201410835657.XA CN201410835657A CN104461805A CN 104461805 A CN104461805 A CN 104461805A CN 201410835657 A CN201410835657 A CN 201410835657A CN 104461805 A CN104461805 A CN 104461805A
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Abstract
The invention provides a CPLD-based system state detecting method, a CPLD and a server mainboard. According to the method, each signal line which can reflect the abnormal state of a system is connected with the complex programmable logic device (CPLD), and a prompt message corresponding to the abnormal state of a signal output by each signal line is set. The method comprises the steps that the CPLD acquires the signals output by the signal lines, the CPLD detects the state of each signal and acquiring the prompt message corresponding to a detected abnormal state, and the CPLD controls a display module to conduct displaying according to the acquired prompt message. By the adoption of the scheme, a user can learn about the abnormal state of the system quickly and determines the state of the system according to the abnormal state, and then accuracy is improved.
Description
Technical field
The present invention relates to Computer Applied Technology field, particularly one is based on system state detection method, CPLD and the server master board of CPLD (CPLD, Complex Programmable Logic Device).
Background technology
Along with the development of computer technology, the exploitation of server becomes increasingly complex, and the fault that server occurs is also more and more various, therefore, how to detect that the reason device of server failure becomes urgent problem.
The mode of the reason device of traditional detection server failure is: when server fail, can determine defective device after utilizing oscillograph and multimeter to carry out repeatedly determination and analysis to the device that in server, each may break down.
Visible, traditional detection mode has the shortcoming long, accuracy rate is low that expends time in.
Summary of the invention
The present embodiment provides a kind of system state detection method based on CPLD, CPLD and server master board, has to solve system detection mode the shortcoming long, accuracy rate is low that expends time in.
Present embodiments provide a kind of system state detection method based on CPLD, can reflect that each signal wire of system exception state is connected with complex programmable logic device (CPLD), the information corresponding to abnormality of the signal that each signal wire exports is set, also comprises:
CPLD obtains the signal that each signal wire described exports;
CPLD detects the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality;
CPLD controls display module according to the information obtained and shows.
Preferably, comprise further:
The normal condition arranging the signal that each signal wire exports is high level, and the abnormality arranging the signal that each signal wire exports is low level; When the signal that CPLD gets described each signal wire output is high level, the state that described CPLD detects described signal is normal condition; When the signal that CPLD gets described each signal wire output is low level, the state that described CPLD detects described signal is abnormality.
Preferably, described display module is charactron, and described CPLD controls display module according to the information obtained and shows, and comprising:
The information of acquisition is compiled as corresponding digital section;
CPLD controls charactron and lights described digital section.
Preferably, before obtaining the information corresponding to abnormality, comprise further:
When CPLD does not get the signal of described each signal wire output within the time period pre-set, perform the information corresponding to described acquisition abnormality.
Preferably, describedly reflect that each signal wire of system exception state comprises:
One or more signal wire in reflection cpu frequency, CPU power supply signal, internal memory power supply signal and south bridge alarm signal.
The present embodiment additionally provides a kind of CPLD, can reflect that each signal wire of system exception state is connected with complex programmable logic device (CPLD), also comprise:
Setting unit, for arrange each signal wire export signal abnormality corresponding to information;
Acquiring unit, for obtaining the signal that each signal wire described exports;
Detecting unit, for detecting the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality from described setting unit;
Control module, the information for obtaining according to described detecting unit controls outside display module and shows.
Preferably, described setting unit is high level for arranging the normal condition of the signal that each signal wire exports, and the abnormality arranging the signal that each signal wire exports is low level;
When the signal that acquiring unit gets described each signal wire output is high level, the state that described detecting unit detects described signal is normal condition; When the signal that acquiring unit gets described each signal wire output is low level, the state that described detecting unit detects described signal is abnormality.
Preferably, described display module is charactron, described control module, for the information of acquisition being compiled as corresponding digital section, controlling charactron and lighting described digital section.
Preferably, describedly reflect that each signal wire of system exception state comprises:
One or more signal wire in reflection cpu frequency, CPU power supply signal, internal memory power supply signal and south bridge alarm signal.
The present embodiment additionally provides a kind of server master board, it is characterized in that, comprises any one CPLD above-mentioned.
Present embodiments provide a kind of system state detection method based on CPLD and CPLD, by reflecting that each signal wire of system exception state is connected with complex programmable logic device (CPLD), the information corresponding to abnormality of the signal that each signal wire exports is set, when state signal being detected is abnormality, determine the information that this abnormality is corresponding, and control display module and show, user is made to know the signal wire of abnormality fast, and know system state according to the signal wire of abnormality, thus improve accuracy rate.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that one embodiment of the invention provides;
Fig. 2 is the method flow diagram that another embodiment of the present invention provides;
Fig. 3 is the server architecture schematic diagram that the embodiment of the present invention provides;
Fig. 4 is the digital section schematic diagram of information 01 correspondence in the embodiment of the present invention;
Fig. 5 is the configuration diagram of the device place equipment that the embodiment of the present invention provides;
Fig. 6 is the apparatus structure schematic diagram that the embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, embodiments provide a kind of system state detection method based on CPLD, can reflect that each signal wire of system exception state is connected with CPLD, arrange the information corresponding to abnormality of the signal that each signal wire exports, the method can comprise the following steps:
Step 101:CPLD obtains the signal that each signal wire described exports.
Step 102:CPLD detects the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality.
Step 103:CPLD controls display module according to the information obtained and shows.
According to such scheme, by reflecting that each signal wire of system exception state is connected with complex programmable logic device (CPLD), the information corresponding to abnormality of the signal that each signal wire exports is set, when state signal being detected is abnormality, determine the information that this abnormality is corresponding, and control display module and show, make user know the signal wire of abnormality fast, and know system state according to the signal wire of abnormality, thus improve accuracy rate.
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.
As shown in Figure 2, embodiments provide a kind of system state detection method based on CPLD, the present embodiment detects with the problem slack-off to server travelling speed, and method can comprise the following steps:
Step 201: can reflect that each signal wire of system exception state is connected with CPLD.
In the present embodiment, these can reflect each signal wire of system exception state can be on CPU, on power supply, south bridge (PCH) etc., switching type power supply (PSU, Power Supply Unit) upper etc., to all in system, CPLD can reflect that each signal wire of system exception state detects.
Step 202: the normal condition and abnormality that can reflect the signal that each signal wire of system exception state exports are set in system, and the information corresponding to abnormality of the signal that each signal wire exports is set.
As shown in Figure 3, the present embodiment is detected as example with power supply chip VR1, PCH and PSU that power supply chip VR0, the CPU1 corresponding to CPU0, CPU1, the CPU0 in server are corresponding and method provided by the invention is described.
In the present embodiment, can utilize high level and low level that the state of the signal that each signal wire exports in server is set, such as, the normal condition arranging the signal that each signal wire exports in server is high level, and the abnormality arranging the signal that each signal wire exports in server is low level.Or the normal condition that can arrange the signal that each signal wire exports in server is 1, the abnormality arranging the signal that each signal wire exports in server is 0.
The device broken down to point out user, arranges the information corresponding to abnormality of the signal that each signal wire exports, and preserves this configuration information.Wherein, this information can be numerical coding, also can be the title of defective device, or arranges according to the warning color of warning lamp.
In the present embodiment, be numerical coding for information, the information corresponding to abnormality of the signal of each signal wire output of setting is as shown in table 1 below:
Table 1:
| Output signal | Information |
| CPU0_PROCHOT# | 01 |
| CPU0_MEM0_HOT# | 02 |
| CPU0_VR0_HOT_N | 03 |
| MEM0_VR0_HOT_N | 04 |
| CPU1_PROCHOT# | 05 |
| CPU1_MEM0_HOT# | 06 |
| CPU1_VR1_HOT_N | 07 |
| MEM1_VR1_HOT_N | 08 |
| SMBALERT# | 09 |
| Other ERROR | ** |
In above-mentioned table 1, PROCHOT#, for stating the output frequency of CPU, under normal circumstances, the output frequency of CPU is positioned at fixing frequency range, if CPU breaks down, this output frequency reduces; CPU0_MEM0, CPU1_MEM0, the internal memory of statement CPU; VR is for stating power supply; SMBALERT is the warning information of PCH, PSU.
Step 203:CPLD obtains the signal of the output of each signal wire.
In the present embodiment, preset preset time period, if CPLD does not get the signal of the output of certain signal wire within the time period preset, then determine that the signal that this signal wire exports is the signal wire of abnormality, so can perform step 205.
Step 204: the state judging the signal that each signal wire obtained exports, if the state that judged result is the signal that each signal wire exports is high level, performs step 203; If judged result is the state of the signal that signal wire exports is low level, perform step 205.
In the present embodiment, if the signal that the signal wire of acquisition exports is high level, the state of the signal of so this signal wire output is normal condition, if the signal that the signal wire obtained exports is low level, the state of the signal of so this signal wire output is abnormality.
Step 205: when being abnormality according to the signal of the output of preserving in advance and the corresponding relation of information, obtains the information corresponding to abnormality.
In the present embodiment, if according to the signal CPU0_PROCHOT# that CPU0 exports, CPLD determines that the signal of this output is low level, thus determine that CPU0 breaks down, determine that the information that the signal of this output is corresponding is according to table 1: 01.
The information of acquisition is compiled as corresponding digital section by step 206:CPLD.
In the present embodiment, if CPLD knows that display module is charactron in advance, therefore, CPLD is compiled as corresponding digital section by 01, the digital section after conversion as shown in Figure 4.
Step 207:CPLD controls charactron and lights digital section.
In the present embodiment, display module can be charactron, also can be other LED light.
In the present embodiment, the numeral number of user according to display module, determines defective device.
According to such scheme, by reflecting that each signal wire of system exception state is connected with complex programmable logic device (CPLD), the information corresponding to abnormality of the signal that each signal wire exports is set, when state signal being detected is abnormality, determine the information that this abnormality is corresponding, and control display module and show, make user know the signal wire of abnormality fast, and know system state according to the signal wire of abnormality, thus improve accuracy rate.
As shown in Figure 5, Figure 6, embodiments provide a kind of CPLD, can reflect that each signal wire of system exception state is connected with complex programmable logic device (CPLD).Device embodiment can pass through software simulating, also can be realized by the mode of hardware or software and hardware combining.Say from hardware view; as shown in Figure 5; for a kind of hardware structure diagram of the CPLD that the embodiment of the present invention provides; except the CPU shown in Fig. 5, internal memory, network interface and nonvolatile memory; in embodiment, CPLD can also comprise other hardware usually, as the forwarding chip etc. of responsible process message.For software simulating, as shown in Figure 6, as the device on a logical meaning, be by the CPU of its place equipment, computer program instructions corresponding in nonvolatile memory is read operation in internal memory to be formed.The CPLD60 that the present embodiment provides comprises:
Setting unit 601, for arrange each signal wire export signal abnormality corresponding to information;
Acquiring unit 602, for obtaining the signal that each signal wire described exports;
Detecting unit 603, for detecting the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality from described setting unit;
Control module 604, the information for obtaining according to described detecting unit controls outside display module and shows.
Further, described setting unit 601 is high level for arranging the normal condition of the signal that each signal wire exports, and the abnormality arranging the signal that each signal wire exports is low level;
When the signal that acquiring unit gets described each signal wire output is high level, the state that described detecting unit detects described signal is normal condition; When the signal that acquiring unit gets described each signal wire output is low level, the state that described detecting unit detects described signal is abnormality.
Further, described display module is charactron, described control module 604, for the information of acquisition being compiled as corresponding digital section, controlling charactron and lighting described digital section.
Further, describedly reflect that each signal wire of system exception state comprises:
One or more signal wire in reflection cpu frequency, CPU power supply signal, internal memory power supply signal and south bridge alarm signal.
The embodiment of the present invention additionally provides a kind of server master board, comprises any one CPLD above-mentioned.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (10)
1. the system state detection method based on CPLD, it is characterized in that, can reflect that each signal wire of system exception state is connected with complex programmable logic device (CPLD), and the information corresponding to abnormality of the signal that each signal wire exports will be set, also comprise:
CPLD obtains the signal that each signal wire described exports;
CPLD detects the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality;
CPLD controls display module according to the information obtained and shows.
2. method according to claim 1, is characterized in that, comprises further:
The normal condition arranging the signal that each signal wire exports is high level, and the abnormality arranging the signal that each signal wire exports is low level; When the signal that CPLD gets described each signal wire output is high level, the state that described CPLD detects described signal is normal condition; When the signal that CPLD gets described each signal wire output is low level, the state that described CPLD detects described signal is abnormality.
3. method according to claim 2, is characterized in that, described display module is charactron, and described CPLD controls display module according to the information obtained and shows, and comprising:
The information of acquisition is compiled as corresponding digital section;
CPLD controls charactron and lights described digital section.
4. method according to claim 1, is characterized in that, before obtaining the information corresponding to abnormality, comprises further:
When CPLD does not get the signal of described each signal wire output within the time period pre-set, perform the information corresponding to described acquisition abnormality.
5. according to described method arbitrary in Claims 1-4, it is characterized in that, describedly reflect that each signal wire of system exception state comprises:
One or more signal wire in reflection cpu frequency, CPU power supply signal, internal memory power supply signal and south bridge alarm signal.
6. a CPLD, is characterized in that, can reflect that each signal wire of system exception state is connected with complex programmable logic device (CPLD), also comprise:
Setting unit, for arrange each signal wire export signal abnormality corresponding to information;
Acquiring unit, for obtaining the signal that each signal wire described exports;
Detecting unit, for detecting the state of described signal, when detecting as abnormality, obtains the information corresponding to abnormality from described setting unit;
Control module, the information for obtaining according to described detecting unit controls outside display module and shows.
7. CPLD according to claim 6, is characterized in that, described setting unit, is high level for arranging the normal condition of the signal that each signal wire exports, and the abnormality arranging the signal that each signal wire exports is low level;
When the signal that acquiring unit gets described each signal wire output is high level, the state that described detecting unit detects described signal is normal condition; When the signal that acquiring unit gets described each signal wire output is low level, the state that described detecting unit detects described signal is abnormality.
8. CPLD according to claim 7, is characterized in that, described display module is charactron, described control module, for the information of acquisition being compiled as corresponding digital section, controlling charactron and lighting described digital section.
9. CPLD according to claim 6, is characterized in that, describedly reflects that each signal wire of system exception state comprises:
One or more signal wire in reflection cpu frequency, CPU power supply signal, internal memory power supply signal and south bridge alarm signal.
10. a server master board, is characterized in that, comprises as the CPLD as described in arbitrary in claim 6 to 9.
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| CN106774015A (en) * | 2017-02-13 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of system status signal localization method, device and control system |
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| CN109581224A (en) * | 2018-12-14 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of monitoring system and smart machine of device power state |
| CN109901057A (en) * | 2019-04-15 | 2019-06-18 | 苏州浪潮智能科技有限公司 | A kind of Fault Locating Method, device, equipment and storage medium |
| CN111078445A (en) * | 2019-11-15 | 2020-04-28 | 苏州浪潮智能科技有限公司 | PSU power failure reason detection method and device |
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| CN112015624A (en) * | 2020-09-03 | 2020-12-01 | 恒为科技（上海）股份有限公司 | Server process monitoring method and system |
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| TWI830623B (en) * | 2023-03-15 | 2024-01-21 | 神雲科技股份有限公司 | A motherboard detection method |
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Application publication date: 20150325 |