CN113961409A - Method for improving serial port data security and OLT equipment thereof - Google Patents
Method for improving serial port data security and OLT equipment thereof Download PDFInfo
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- CN113961409A CN113961409A CN202111243731.5A CN202111243731A CN113961409A CN 113961409 A CN113961409 A CN 113961409A CN 202111243731 A CN202111243731 A CN 202111243731A CN 113961409 A CN113961409 A CN 113961409A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a method for improving serial port data security and OLT equipment thereof, wherein the method comprises the following steps: s1: the OLT equipment is powered on, and the CPLD enters a switch starting state by default; s2: the CPLD sequence detector monitors the instruction data transmitted by the PC to the CPU, and according to a standard serial port protocol, the CPLD stores the received instruction data into the shift register FIFO 1; s3: comparing the instruction data stored in the shift register FIFO1 with a start switch password oolt and a close switch password colt set by a sequence detector respectively; s4: if the command is a starting switch password, the data state sent by the CPU is kept in a disconnected state by the CPLD; if the command is a close switch password, the process proceeds to step S5; if the command is not the starting switch or the closing switch password, returning to S2 to continue detection; s5: closing the switch, starting the encoder by the CPLD, and performing primary encoding processing on the data sent by the CPU; s6: and 8bit data bits are extracted from the data obtained by coding, secondary coding is carried out according to a preset coding truth table, and the data are sent to a PC (personal computer) end through a switch.
Description
Technical Field
The invention relates to the technical field of serial port information security, in particular to a method for improving serial port data security and OLT equipment thereof.
Background
At present, a conventional OLT apparatus communicates with a PC using a serial port (universal asynchronous receiver/transmitter) to display print information of a CPU on a PC screen. The PC sends an instruction to the embedded device through serial port debugging software, thereby performing configuration or function debugging on the embedded device, as disclosed in chinese patent publication No.: CN 104461805 a, published: 2015.03.25, a CPLD-based system state detection method, characterized in that, each signal line capable of reflecting system abnormal state is connected with a complex programmable logic device CPLD, and the prompt information corresponding to the abnormal state of the signal output by each signal line is set, also includes: the CPLD acquires signals output by each signal line; the CPLD detects the state of the signal, and when the signal is detected to be in an abnormal state, prompt information corresponding to the abnormal state is acquired; and the CPLD controls the display module to display according to the acquired prompt information.
In order to prevent the software of the OLT device from being maliciously modified and prevent important print data of the serial port from leaking, it is very important to protect the data security of the serial port. Because original factory research and development personnel often need log information of serial port printing to be used for debugging and problem searching, so the data of serial port is not protected by most equipment manufacturers on the market at present, and great potential safety hazard exists.
Disclosure of Invention
In order to solve the problems of the prior art, the invention provides a method for improving the security of serial port data and OLT equipment thereof.
In order to achieve the purpose of the invention, the technical scheme is as follows:
a method for improving serial port data security comprises the following steps:
s1: the OLT equipment is powered on, and the CPLD enters a switch starting state by default;
s2: the CPLD sequence detector monitors the instruction data transmitted by the PC to the CPU, and according to a standard serial port protocol, the CPLD stores the received instruction data into the shift register FIFO 1;
s3: comparing the instruction data stored in the shift register FIFO1 with a start switch password oolt and a close switch password colt set by a sequence detector respectively;
s4: if the command is a starting switch password, the data state sent by the CPU is kept in a disconnected state by the CPLD; if the command is a close switch password, the process proceeds to step S5; if the command is not the starting switch or the closing switch password, returning to S2 to continue detecting;
s5: closing the switch, starting the encoder by the CPLD, and performing primary encoding processing on the data sent by the CPU;
s6: and 8bit data bits are extracted from the data obtained by coding, secondary coding is carried out according to a preset coding truth table, and the data are sent to a PC (personal computer) end through a switch.
Preferably, after step S6, the log information of the OLT device is acquired by the PC, and decoded log information is obtained by decoding according to the corresponding relationship of the encoding truth table, so that research personnel can analyze and debug the log information.
Further, in step S1, after the OLT device is powered on, the CPLD interrupts the CPU from transmitting data to the PC; meanwhile, the CPLD monitors serial data from the PC, and the CPU normally receives the serial data from the PC.
Further, in step S2, specifically, according to the standard serial port protocol, the CPLD sequentially stores the 8-bit ASCII code of the received command data into the 32-bit shift register FIFO1 of the CPLD.
Further, setting the ASCII code of the starting switch password oolt to 01101111011011110110110001110100; the ASCII code of the closed switch password colt is set to 01100011011011110110110001110100.
An OLT device comprises a CPU and a CPLD; the CPLD module comprises an encoder, a switch, a sequence detector, a shift register FIFO1 and an alignment module;
when the OLT equipment is powered on, the CPLD is in a state of starting a switch by default;
the sequence detector is used for monitoring instruction data transmitted to the CPU by the PC;
the shift register FIFO1 is used for registering the received instruction data according to a standard serial port protocol;
the comparison module is used for comparing the instruction data stored in the shift register FIFO1 with a starting switch password oolt and a closing switch password colt set by the sequence detector respectively;
the switch is used for judging whether to start according to the comparison result so as to realize whether the data sent by the CPU can be transmitted to the PC end;
the encoder is used for carrying out primary encoding processing on the data sent by the CPU and carrying out secondary encoding according to a preset encoding truth table.
Preferably, after the OLT device is powered on, the states of the CPLD are as follows: the switch is closed to interrupt the transmission of the data from the CPU to the PC end; meanwhile, the CPLD monitors serial data from the PC, and the CPU normally receives the serial data from the PC.
Further, the shift register FIFO1 adopts a 32-bit shift register, and stores the 8-bit data bits ASCII code of the received instruction data in sequence according to the standard serial protocol.
Further, the ASCII code of the start switch password oolt is 01101111011011110110110001110100; the ASCII code of the close switch password colt is 01100011011011110110110001110100.
Furthermore, the OLT equipment is also provided with a 232 serial port; and the CPU performs data transmission with the PC terminal through a 232 serial port.
The invention has the following beneficial effects:
the invention makes full use of the CPLD in the OLT equipment, and because the CPLD is more flexible, the encoding and decoding work of serial port data can be more easily realized, the data security is improved, and the printed information of the product is prevented from being easily exposed to competitors. The CPLD not only can encode serial port data, but also can control whether the data can be displayed on a PC (personal computer) end, so that a multiple protection mechanism is formed, and the safety of the serial port data can be greatly improved.
Drawings
FIG. 1 is a flow chart of the steps of the method described in example 1.
Fig. 2 is a schematic frame diagram of the OLT apparatus according to embodiment 2.
Detailed Description
The invention is described in detail below with reference to the drawings and the detailed description.
Example 1
As shown in fig. 1, a method for improving serial port data requires the functions and specific operation steps of a CPLD. The CPU of the OLT is turned off and displayed back, the PC can normally send data to the CPU, and the CPU can receive the data. The data sent by the CPU is encoded by a truth table set in the CPU after passing through the CPLD, but the CPU is controlled by a switch in the CPLD to determine whether the data can finally reach the PC. Only when the PC inputs a specific instruction to the CPU, the instruction is simultaneously recognized by the sequence detector in the CPLD, and the switch is closed, so that the data sent by the CPU can be normally received by the PC. Table 1 shows a serial port frame format of the CPU of the OLT apparatus, in which a data bit is 8 bits, parity is not used, a stop bit is 1bit, and a baud rate is 115200.
TABLE 1
Table 2 shows truth table relationships of the CPLD internal processing data.
TABLE 2
| CPU source data | Encoded data | CPU source data | Encoded data | CPU source data | Number after codingAccording to |
| 0 | A | k | G | G | M |
| 1 | R | m | W | H | b |
| 2 | B | n | H | I | N |
| 3 | S | o | X | J | c |
| 4 | g | p | k | K | o |
| 5 | C | q | I | L | 0 |
| 6 | T | r | Y | M | d |
| 7 | h | s | l | N | p |
| 8 | s | t | v | 0 | 4 |
| 9 | D | u | J | P | P |
| a | U | v | Z | Q | e |
| b | i | w | m | R | q |
| c | t | x | w | S | y |
| d | 0 | y | 2 | T | 5 |
| e | E | z | K | U | Q |
| f | V | A | a | V | f |
| g | j | B | n | W | r |
| h | u | C | x | X | z |
| i | 1 | D | 3 | Y | 6 |
| j | 7 | E | 8 | Z | 9 |
| k | F | F | L |
The specific implementation steps are as follows:
s1: when the equipment is powered on, the CPLD enters a switch starting state by default. The CPLD interrupts data sent by the CPU, and the data are not transmitted to the PC end; meanwhile, the CPLD monitors serial port data from the PC, and the CPU normally receives the serial port data of the PC;
s2: the CPLD sequence detector monitors the instruction data transmitted by the PC to the CPU, and according to the standard serial port protocol, the CPLD sequentially stores the 8-bit data bit ASCII code of the received data into the 32-bit shift register FIFO1 of the CPLD.
S3: the instruction data stored in the shift register FIFO1 are compared with the start switch password oolt and the close switch password colt set by the sequence detector, respectively. Setting the ASCII code of the starting switch password oolt to 01101111011011110110110001110100; the ASCII code of the closed switch password colt is set to 01100011011011110110110001110100.
S4: if the command is a starting switch password, the data state sent by the CPU is kept in a disconnected state by the CPLD; if the command is a close switch password, the process proceeds to step S5; if the command is not the starting switch or the closing switch password, returning to S2 to continue detecting;
s5: if the command is a closed switch password, closing the switch, starting the encoder by the CPLD, and carrying out primary encoding processing on the data sent by the CPU;
s6: referring to table 1, 8-bit data bits are extracted from the CPU data, and the data is secondarily encoded according to a preset encoding truth table (refer to table 2). For example, if the source data is 0(ASCII code 00110000), referring to table 2, the data is replaced with a (ASCII code 01000001), and the start bit and the stop bit are combined and sent to the PC through the switch.
After step S6, the customer may obtain the log information of the OLT device through the PC, and return the log information to the developer of the manufacturer, and the developer reads the log information with the script, and decodes the log information according to the corresponding relationship of the encoding truth table to obtain the decoded log information (for example, the A9wbB is replaced with correct admin), so that the developer may analyze and debug the log information.
This embodiment is through controlling and handling the data that CPU sent to PC direction, can control whether show information on the serial ports in a flexible way, or show the error message who passes through the processing to play the effect of protection serial ports data.
Example 2
Based on the method described in embodiment 1, this embodiment further provides an OLT device, as shown in fig. 2, including a CPU and a CPLD; the CPLD module comprises an encoder, a switch, a sequence detector, a shift register FIFO1 and an alignment module;
when the OLT equipment is powered on, the CPLD is in a state of starting a switch by default;
the sequence detector is used for monitoring instruction data transmitted to the CPU by the PC;
the shift register FIFO1 is used for registering the received instruction data according to a standard serial port protocol;
the comparison module is used for comparing the instruction data stored in the shift register FIFO1 with a starting switch password oolt and a closing switch password colt set by the sequence detector respectively;
the switch is used for judging whether to start according to the comparison result so as to realize whether the data sent by the CPU can be transmitted to the PC end;
the encoder is used for carrying out primary encoding processing on the data sent by the CPU and carrying out secondary encoding according to a preset encoding truth table.
After the OLT device is powered on, the states of the CPLD are as follows: the switch is closed to interrupt the transmission of the data from the CPU to the PC end; meanwhile, the CPLD monitors serial data from the PC, and the CPU normally receives the serial data from the PC.
The shift register FIFO1 adopts a 32-bit shift register, and stores 8-bit data bits ASCII code of the received instruction data in sequence according to a standard serial port protocol.
The ASCII code of the starting switch password oolt is 01101111011011110110110001110100; the ASCII code of the close switch password colt is 01100011011011110110110001110100.
The OLT equipment is also provided with a 232 serial port; and the CPU performs data transmission with the PC terminal through a 232 serial port.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A method for improving the security of serial port data is characterized in that: the method comprises the following steps:
s1: the OLT equipment is powered on, and the CPLD enters a switch starting state by default;
s2: the CPLD sequence detector monitors the instruction data transmitted by the PC to the CPU, and according to a standard serial port protocol, the CPLD stores the received instruction data into the shift register FIFO 1;
s3: comparing the instruction data stored in the shift register FIFO1 with a start switch password oolt and a close switch password colt set by a sequence detector respectively;
s4: if the command is a starting switch password, the data state sent by the CPU is kept in a disconnected state by the CPLD; if the command is a close switch password, the process proceeds to step S5; if the command is not the starting switch or the closing switch password, returning to S2 to continue detecting;
s5: closing the switch, starting the encoder by the CPLD, and performing primary encoding processing on the data sent by the CPU;
s6: and 8bit data bits are extracted from the data obtained by coding, secondary coding is carried out according to a preset coding truth table, and the data are sent to a PC (personal computer) end through a switch.
2. The method for improving the security of the serial port data according to claim 1, wherein: and after the step S6, obtaining the log information of the OLT device through the PC, and decoding according to the corresponding relationship of the coding truth table to obtain the decoded log information for the research and development personnel to analyze and debug.
3. The method for improving the security of the serial port data according to claim 1, wherein: step S1, after the OLT equipment is powered on, the CPLD interrupts the CPU to transmit data to the PC end; meanwhile, the CPLD monitors serial data from the PC, and the CPU normally receives the serial data from the PC.
4. The method for improving the security of the serial port data according to claim 1, wherein: in step S2, specifically, according to the standard serial protocol, the CPLD sequentially stores the 8-bit ASCII code of the received instruction data into the 32-bit shift register FIFO1 of the CPLD.
5. The method for improving the security of the serial port data according to claim 1, wherein: setting the ASCII code of the starting switch password oolt to 01101111011011110110110001110100; the ASCII code of the closed switch password colt is set to 01100011011011110110110001110100.
6. An OLT device, characterized by: comprises a CPU and a CPLD; the CPLD module comprises an encoder, a switch, a sequence detector, a shift register FIFO1 and an alignment module;
when the OLT equipment is powered on, the CPLD is in a state of starting a switch by default;
the sequence detector is used for monitoring instruction data transmitted to the CPU by the PC;
the shift register FIFO1 is used for registering the received instruction data according to a standard serial port protocol;
the comparison module is used for comparing the instruction data stored in the shift register FIFO1 with a starting switch password oolt and a closing switch password colt set by the sequence detector respectively;
the switch is used for judging whether to start according to the comparison result so as to realize whether the data sent by the CPU can be transmitted to the PC end;
the encoder is used for carrying out primary encoding processing on the data sent by the CPU and carrying out secondary encoding according to a preset encoding truth table.
7. The OLT device of claim 5, wherein: after the OLT device is powered on, the states of the CPLD are as follows: the switch is closed to interrupt the transmission of the data from the CPU to the PC end; meanwhile, the CPLD monitors serial data from the PC, and the CPU normally receives the serial data from the PC.
8. The OLT device of claim 5, wherein: the shift register FIFO1 adopts a 32-bit shift register, and stores 8-bit data bits ASCII code of the received instruction data in sequence according to a standard serial port protocol.
9. The OLT device of claim 5, wherein: the ASCII code of the starting switch password oolt is 01101111011011110110110001110100; the ASCII code of the close switch password colt is 01100011011011110110110001110100.
10. The OLT device of claim 5, wherein: the OLT equipment is also provided with a 232 serial port; and the CPU performs data transmission with the PC terminal through a 232 serial port.
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| CN112364397A (en) * | 2020-11-27 | 2021-02-12 | 天津七所精密机电技术有限公司 | Asynchronous serial port secure communication system and method based on FPGA |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100185876A1 (en) * | 2009-01-20 | 2010-07-22 | Kings Information & Network | Keyboard-input information-security apparatus and method |
| CN104461805A (en) * | 2014-12-29 | 2015-03-25 | 浪潮电子信息产业股份有限公司 | CPLD-based system state detecting method, CPLD and server mainboard |
| CN108804952A (en) * | 2018-05-29 | 2018-11-13 | 郑州云海信息技术有限公司 | A kind of server start-up control device and control method |
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