CN102073349A

CN102073349A - Method for saving peripheral circuits of mainboard of server

Info

Publication number: CN102073349A
Application number: CN2011100301611A
Authority: CN
Inventors: 刘强; 梁智豪; 于治楼; 金长新
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2011-01-27
Filing date: 2011-01-27
Publication date: 2011-05-25

Abstract

The invention discloses a method for saving peripheral circuits of a mainboard of a server, which belongs to the technical field of servers. In the method, some peripheral circuits of the mainboard of the server are integrated by a complex programmable logic device (CPLD) chip. The CPLD chip comprises system management bus (SMBUS) switching logic, 80PORT decoding logic, serial port switching logic, central processing unit (CPU) overheat alarm logic, video graphics array (VGA) line-field signal switching logic, power supply detection logic, memory voltage enable logic, and clock frequency-division logic, wherein the SMBUS switching logic is connected with an SMBUS; the 80PORT decoding logic is connected with a low pin count (LPC) bus; the serial port switching logic is connected with a supper input/output (SUPERIO); the CPU overheat alarm logic is connected with a CPU; the VGA line-field signal switching logic is connected with a video card; the power supply detection logic is connected with a power supply; the memory voltage enable logic is connected with a memory; and the clock frequency-division logic is connected with a clock chip. By the method, the peripheral circuits of the mainboard of the server are integrated, the space of the server is reduced, and the cost is saved.

Description

A kind of method of saving the peripheral circuit of server master board

Technical field

The present invention relates to a kind of server technology field, specifically a kind of method of saving the peripheral circuit of server master board.

Background technology

Development along with server technology, the kind of server is more and more, though the chipset that adopts may be similar, but demand according to the industry of not uniting, the very big difference that the periphery design of server still exists, the field that has requires the little function of volume of server complete, requires to integrate some peripheral circuits when so just requiring the design server mainboard and reduces the space and save cost.

Summary of the invention

Technical assignment of the present invention provide a kind of can integrated service device mainboard peripheral circuit, reduce server space and cost-effective a kind of method of saving the peripheral circuit of server master board.

Technical assignment of the present invention is realized in the following manner, comprises server, adopts the piece of CPLD chip to come some peripheral circuits of integrated service device mainboard; The CPLD chip comprises that SMBUS switch switch logic, 80PORT decoding logic, serial ports switch logic, CPU temperature alarm logic, VGA row field signal switch logic, power supply detect logic, memory voltage enable logic, clock division logic; SMBUS switch switch logic connects SMBUS bus, the switch and the switching of the SMBUS bus on the SMBUS switch switch logic control main board and the SMBUS bus of middle plate; The 80PORT decoding logic connects lpc bus, and the POST sign indicating number decoding back the when BIOS that the 80PORT decoding logic is sent server south bridge lpc bus here starts demonstrates concrete numeral on charactron, so that can accurately judge the mainboard running status debugging mainboard time; The serial ports switch logic connects SUPERIO, and the serial ports switch logic is judged by switching signal the rs 232 serial interface signal of SUPERIO is linked to each other with redundant serial ports; CPU temperature alarm logic connects CPU, and CPU temperature alarm logic is with the overheated alarm signal of multiple CPU heat alarm output CPU; VGA row field signal switch logic connects video card, and multichannel VGA shows that the switching by carry out VGA row field signal passage in the CPLD chip realizes; Power supply detects logic and connects power supply, and power supply detects logic detection north and south bridge and whether cpu power output is normal, if normally then the CPLD chip sends signalisation CPU, otherwise produces the signal that reports an error; The memory voltage enable logic connects internal memory, and whether the memory voltage enable logic detects the condition that the control memory voltage produces and satisfy, if satisfy condition then send the enable signal that produces memory voltage and remove to produce the internal memory required voltage, otherwise produces the signal that reports an error; The clock division logic connects clock chip, and the clock division logic is carried out frequency division to input clock, produces low-frequency clock and uses for chip on the server.

SMBUS switch switch logic in the CPLD chip is used for being responsible for opening the SMBUS link that mainboard is communicated by letter with backboard after system start-up is finished, make the external management module to obtain system health information etc. by visit SMBUS bus, but sometimes, need in suitable, close corresponding SMBUS bus in order to prevent that many SMBUS links from visiting the generation of same device simultaneously; The 80PORT decoding logic is judged the running status of mainboard in the vectoring phase with showing by charactron behind the data decoding on the lpc bus when BIOS starts; Because mainboard is connected with backboard redundant interface is arranged, serial ports and VGA signal all join by backboard, and the serial ports switch logic need select signal that rs 232 serial interface signal is switched to respectively on the corresponding mainboard interface according to interface; VGA row field signal switch logic will be selected signal switch line field signal between two interfaces according to interface equally; CPU temperature alarm logic detects CPU and in time sends alarm signal to CPU overheated the time when detecting cpu power is overheated or administration module is sent CPU heat alarm and local management; Power supply detects logic and the memory voltage enable logic then is to be responsible for the duty of north and south bridge and CPU and memory power supply voltage is detected, and as finding abnormity of power supply, timely powered-down also sends the signal that reports an error; The clock division logic then is that the clock that produces 25MHZ uses for local BMC, to reduce external crystal-controlled oscillation quantity.

A kind of method of saving the peripheral circuit of server master board of the present invention is compared with prior art, integrate the peripheral circuit of server master board, the peripheral circuit of saving server master board, minimizing server space, saved cost, thereby, have good value for applications.

Description of drawings

The present invention is further described below in conjunction with accompanying drawing.

Accompanying drawing 1 is a kind of structured flowchart of method of the peripheral circuit of saving server master board.

Embodiment

Explain below with reference to Figure of description and specific embodiment a kind of method of saving the peripheral circuit of server master board of the present invention being done.

Embodiment:

A kind of method of saving the peripheral circuit of server master board of the present invention comprises server, adopts the piece of CPLD chip to come some peripheral circuits of integrated service device mainboard; The CPLD chip comprises that SMBUS switch switch logic, 80PORT decoding logic, serial ports switch logic, CPU temperature alarm logic, VGA row field signal switch logic, power supply detect logic, memory voltage enable logic, clock division logic; SMBUS switch switch logic connects SMBUS bus, the switch and the switching of the SMBUS bus on the SMBUS switch switch logic control main board and the SMBUS bus of middle plate; The 80PORT decoding logic connects lpc bus, and the POST sign indicating number decoding back the when BIOS that the 80PORT decoding logic is sent server south bridge lpc bus here starts demonstrates concrete numeral on charactron, so that can accurately judge the mainboard running status debugging mainboard time; The serial ports switch logic connects SUPERIO, and the serial ports switch logic is judged by switching signal the rs 232 serial interface signal of SUPERIO is linked to each other with redundant serial ports; CPU temperature alarm logic connects CPU, and CPU temperature alarm logic is with the overheated alarm signal of multiple CPU heat alarm output CPU; VGA row field signal switch logic connects video card, and multichannel VGA shows that the switching by carry out VGA row field signal passage in the CPLD chip realizes; Power supply detects logic and connects power supply, and power supply detects logic detection north and south bridge and whether cpu power output is normal, if normally then the CPLD chip sends signalisation CPU, otherwise produces the signal that reports an error; The memory voltage enable logic connects internal memory, and whether the memory voltage enable logic detects the condition that the control memory voltage produces and satisfy, if satisfy condition then send the enable signal that produces memory voltage and remove to produce the internal memory required voltage, otherwise produces the signal that reports an error; The clock division logic connects clock chip, and the clock division logic is carried out frequency division to input clock, produces low-frequency clock and uses for chip on the server.

Except that the described technical characterictic of instructions, be the known technology of those skilled in the art.

Claims

1. a method of saving the peripheral circuit of server master board comprises server, it is characterized in that adopting the piece of CPLD chip to come some peripheral circuits of integrated service device mainboard; The CPLD chip comprises that SMBUS switch switch logic, 80PORT decoding logic, serial ports switch logic, CPU temperature alarm logic, VGA row field signal switch logic, power supply detect logic, memory voltage enable logic, clock division logic; SMBUS switch switch logic connects SMBUS bus, the switch and the switching of the SMBUS bus on the SMBUS switch switch logic control main board and the SMBUS bus of middle plate; The 80PORT decoding logic connects lpc bus, and the POST sign indicating number decoding back the when BIOS that the 80PORT decoding logic is sent server south bridge lpc bus here starts demonstrates concrete numeral on charactron; The serial ports switch logic connects SUPERIO, and the serial ports switch logic links to each other the rs 232 serial interface signal of SUPERIO with redundant serial ports; CPU temperature alarm logic connects CPU, and CPU temperature alarm logic is with the overheated alarm signal of multiple CPU heat alarm output CPU; VGA row field signal switch logic connects video card, and multichannel VGA shows that the switching by carry out VGA row field signal passage in the CPLD chip realizes; Power supply detects logic and connects power supply, and power supply detects logic detection north and south bridge and whether cpu power output is normal, if normally then the CPLD chip sends signalisation CPU, otherwise produces the signal that reports an error; The memory voltage enable logic connects internal memory, and whether the memory voltage enable logic detects the condition that the control memory voltage produces and satisfy, if satisfy condition then send the enable signal that produces memory voltage and remove to produce the internal memory required voltage, otherwise produces the signal that reports an error; The clock division logic connects clock chip, and the clock division logic is carried out frequency division to input clock, produces low-frequency clock and uses for chip on the server.