201227272 六、發明說明： 【發明所屬之技術領域】 一種偵測裝置’特別有關於一種應用於主機板中對於其周邊 元件狀態的偵測裝置。 【先前技術】 請參考「第1圖」所示，其係為習知技術之主機板的架構示 意圖。在習知技術中主機板1〇〇的組成係由基板管理控制單元11〇 連接於南橋晶片組121、切換邏輯單元、序列 埠123或網路連接端124等各項周邊元件。在各項周邊元件中均 具有相應的控制單元(Micro Control Unit，MCU).。在各項周邊元件 會以不同的匯流排進行連接’例如：低腳位計數匯流排(】肅恤 count Bus)、電力管理匯流排(p〇wer Management Bus)或内部智慧 i： f ϊΐ ® ^^Klntelligent Platform Management Interface ^ IPMI) 〇 在習知技術中是由基板管理控制單元n〇偵測主機板1〇〇的 運作並由基板㈣控制單元11Q透過内部整合電路匯流排連接 至’罔路接口。接著’主機板⑽的開發廠商在透過網路接口逐一 的向主機板雇上的各姻邊元件進行麟。開發鋪在根據所 接收到的回應§fl息用以判斷主機板應上的周邊元件是否發生異 常。 、 b白决的礼式方式频可以提供完整_試流程與測試項目。 疋乂上的測。式都兩要透過網路才能實現。因此開發礙商需要另 置獨立的區域肩路，例如：建立動態網域名稱飼服器卿^ 201227272 server)、設定每一個主機板1〇〇的連線參數(例如：網路位址、埠 唬或子網路遮罩等)或不同版本的測試程序之設定。 此外，習知的内部整合電路匯流排的參考設計使用一個7位 元長度的位址空間但保留了 16個位址，所以在一組内部整合電路 匯流排中最多可和112個節點(意即！ 12個周邊元件)通訊。雖然内 «合電路®流排的最大的節點數目是被位址空間所限制住，但 實際上也會被匯流排上的總電容所限制住。 • 基板管理控制單元110上並無設置有電力管理匯流排與其裝 置，所以每—塊主機板⑽在測試時需要由人工另行開啟。就開 4廠商而5 ’ .¾知技術的測試環境的建立就是-項貞擔。再者， 紋在主機板刚上另設置其他的測試治具。這對於開發薇商又 是另一項成本上的負擔。 【發明内容】 雲於以上的問題’本發明在於提供邊元件狀態的偵測 瞻裝置，透過主機板用以偵測主機板所連接的多個周邊元件的使用 狀態。 本發明所揭露之周邊元件狀態的伽裝置祕基板管理控制 單元與可編轉輯元件。基板管财制單元透勒部整合電 路匯流排電性連接於周邊元件；基板管理控制單元用以接收測試 訊號並產生域的轉訊號；_可_邏輯元件透勒部整合 電路匯流排紐連接於基板管理控制單^ ;複雜可編程邏輯元件 t更匕括協4擴展;^組，協議擴展模組用以轉換内部整合電路匯 201227272 流排與序列周邊介面匯流排間所傳遞_試訊號。 在本發陶—輪处雜跑 於稷雜可編程邏輯元件.去诘μ 牙直电〖生連接 ^讀’ η感可編輯輯元件 置，藉以通知 時’複雜可編程賴元件將回應訊息傳送至輸轉…^ 測試人員該主敵的各酬試項目的結果。 本發明所提供帳元件狀不雜由網路接口 =丁相應_1此外，在本發日种的複雜可編轉輯树可驅 動内部整合輸嶋軸_取轉細邊元件的 使用狀態。如此-來’就可以不精的增加職具的開發成 本，就可以對主機板進行測試。 有關本發_財作，紐合圖式作最佳實施例詳細說 明如下。 【實施方式】 本發明係應具有基板控制單元(BasebQanJ麻啊伽 C〇n_er，BMC)駐機板t，耻主機板可以是値器、個人電 腦或筆記型電腦所使用的主機板。請參考「第M圖」所示，其係 為本發明之雜示意圖。周邊元件狀態的制裝置包括基板 管理控制單元210與複雜可編程邏輯元件22〇(c〇mplex201227272 VI. Description of the Invention: [Technical Field of the Invention] A detecting device is particularly concerned with a detecting device applied to a motherboard for the state of its peripheral components. [Prior Art] Please refer to the "Figure 1" for the schematic diagram of the architecture of the motherboard of the prior art. In the prior art, the composition of the motherboard 1 is connected to the peripheral components such as the south bridge chip set 121, the switching logic unit, the serial port 123, or the network connection terminal 124 by the substrate management control unit 11A. There is a corresponding Control Unit (MCU) in each peripheral component. The peripheral components will be connected in different busbars', for example: low-count count bus (countdown), power management bus (p〇wer Management Bus) or internal wisdom i: f ϊΐ ® ^ ^Klntelligent Platform Management Interface ^ IPMI) In the prior art, the substrate management control unit n detects the operation of the motherboard 1 and is connected to the 'circuit interface through the internal integrated circuit bus bar through the substrate (4) control unit 11Q. . Then, the developers of the motherboard (10) are lining up each of the marriage components hired by the motherboard through the network interface. The development shop is based on the response received to determine whether the peripheral components on the motherboard should be abnormal. b, the ceremonial style of the white can provide complete _ test process and test items. The test on the raft. Both can be achieved through the Internet. Therefore, the development of obstruction requires separate independent regional shoulders, for example: establish a dynamic domain name feeder server ^ 201227272 server), set the connection parameters of each motherboard 1 (for example: network address, 埠唬 or subnet masks, etc.) or different versions of the test program settings. In addition, the reference design of the conventional internal integrated circuit bus uses a 7-bit length address space but retains 16 addresses, so there can be up to 112 nodes in a set of internal integrated circuit buss (ie, ! 12 peripheral components) communication. Although the maximum number of nodes in the internal circuit is limited by the address space, it is actually limited by the total capacitance on the bus. • The power management busbar and its device are not provided on the baseboard management control unit 110. Therefore, each motherboard (10) needs to be manually turned on during the test. The establishment of a test environment for 4 manufacturers and 5's knowing technology is the key to the project. Furthermore, the pattern has another test fixture set on the motherboard. This is another cost burden for the development of Wei. SUMMARY OF THE INVENTION The present invention resides in a device for detecting a state of an edge component, which is used to detect a state of use of a plurality of peripheral components to which a motherboard is connected. The gantry device management control unit and the rewritable component of the peripheral component state disclosed in the present invention. The substrate management unit of the substrate management unit is electrically connected to the peripheral components; the substrate management control unit is configured to receive the test signal and generate the domain signal; _ _ _ logic element multiplexer integrated circuit bus line is connected to The substrate management control unit ^; the complex programmable logic device t further includes the extension 4; the group, the protocol expansion module is used to convert the internal integrated circuit sink 201227272 flow row and the serial interface between the serial communication channel to transmit the test signal. In this hair-wheel, the miscellaneous running in the noisy programmable logic component. Go to 诘μ 直直电〖生连接^read' η 感 可 editable component set, by notice when 'complex programmable components will respond to message transmission To the transfer...^ Test the results of the test items of the main enemy. The present invention provides a form of a component that is not miscellaneous by a network interface. In addition, a complex configurable tree in the present day can drive the internal integrated transmission axis to take advantage of the use of the fine-edged component. In this way, the motherboard can be tested without increasing the development cost of the tool. The best embodiment of the present invention is described below in detail. [Embodiment] The present invention should have a baseboard control unit (BasebQanJ 伽 〇 〇 〇 B B B B B B 。 。 , , , , , , , , , , , , , , , , , , , 耻 耻 耻 耻 耻 耻 耻 耻 耻 耻 耻 耻 耻Please refer to the “M” diagram, which is a schematic diagram of the invention. The peripheral device state manufacturing device includes a substrate management control unit 210 and a complex programmable logic device 22 (c〇mplex)
Programmable Logic Device，CPLD)。 基板官理控制單元210透過内部整合電路匯流排(Inter — Integrated Circuit ’ I2C)電性連接於周邊元件23〇。基板管理控制單 元210用以接收測試訊號並產生相應的回應訊號。複雜可編程邏 201227272 輯元件220透過内部整合電路匯流排電性連接於基板管理控制單 兀210。一個基板管理控制單元21〇通常會有幾組内部整合電路匯 流排和外圍的感測器(Sensor)、序列式電子抹除式可複寫唯讀記憶 ^(Serial Electrically-Erasable Programmable Read-Only Memory)>f 通，以讀取系統偵測值及記錄相關數據。另外也可外接一些通用 型之輪入輸出(General Purpose I/O，GPIO)控制器來擴充基板管理 控制早元210的彳貞測功能。 複雜可編程邏輯元件220中更包括協議擴展模組221與資料 緩存器222。協議擴展模組221用以轉換内部整合電路匯流排與序 歹J周邊介面匯流排(Seriai peripherai interface Bus，spj)間所傳遞的 測試訊號。資料緩存器222用以記錄每一周邊元件23〇的回應訊 息。 内部整合電路匯流排係為一種雙線傳輸協議。内部整合電路 匯机排具有資料線(SDATA)腳位與時脈訊號(SCLK)腳位。内部整 σ電路匯流排透過資料線腳位與時脈訊號腳位間所形成的電阻對 電位進行膽。因此’本發明係透翻部整合電路匯流排連接基 板&理控制單7〇 210與複雜可編程邏輯元件22〇。而協議擴展模組 221用以轉換内部整合電路匯流排與序列周邊介面匯流排所傳遞 的測試訊號。 為迠清楚說明本發明的協議轉換處理，還請參考「第2Β圖」 斤下在此-貫施態樣中’協議擴展模组Π更包括内部整合電 路匯*排先進先tH歡(I2C tG FIFQ⑽她如丨、序朋邊介面匯 201227272 流排先進先出模組(8卩11；〇17正〇111〇〇11^)242、讀取式先進先出暫存 器(FIFO register f0r read)243與寫入式先進先出暫存器(Fff〇 register for write)244。内部整合電路匯流排先進先出模組241將内 部整合電路匯流排所收到的訊號發送到寫入式先進先出暫存器 244 ’再透過寫入式先進先出暫存器244舰號逐一的發送到序列 周邊介面匯流排先進先出模組242。 而序列周邊介面匯流排先進先出模組242在接收到序列周邊 介面匯流排所傳送過來的域，則序列周邊介面匯流排先進先出 模組242將訊號傳送至讀取式先進先出暫存器泌讀取式先進先 出暫存器2犯再將訊號轉發至内部整合電路匯流排先進先出模組 24卜内部整合電路匯流排先進先出模組加再透過内部整合電路 匯流排將相應的訊號傳送給對應的裝置。 列周邊介面匯流排可在軟體的控制下構成各種純。例如由一個 主控制單S(maSter MCU)的第一周邊元件231和幾個從屬控継Programmable Logic Device, CPLD). The substrate management control unit 210 is electrically connected to the peripheral elements 23A through an internal integrated circuit bus (Inter- Integrated Circuit 'I2C). The substrate management control unit 210 is configured to receive the test signal and generate a corresponding response signal. Complex Programmable Logic 201227272 component 220 is electrically connected to the baseboard management control unit 210 via an internal integrated circuit bus. A substrate management control unit 21 〇 usually has several sets of internal integrated circuit bus and peripheral sensors (Serial Electrically-Erasable Programmable Read-Only Memory) (Serial Electrically-Erasable Programmable Read-Only Memory) >f pass to read system detection values and record related data. In addition, some general-purpose general purpose I/O (GPIO) controllers can be added to expand the substrate management control function of the early element 210. The complex programmable logic component 220 further includes a protocol extension module 221 and a data buffer 222. The protocol extension module 221 is configured to convert the test signals transmitted between the internal integrated circuit bus and the serial port peripherai interface bus (spj). The data buffer 222 is used to record the response information of each peripheral component 23〇. The internal integrated circuit bus is a two-wire transmission protocol. Internal integrated circuit The bus has a data line (SDATA) pin and a clock signal (SCLK) pin. The internal sigma circuit bus is fused by the resistance formed between the data line pin and the clock signal pin. Thus, the present invention is a versatile integrated circuit busbar connection substrate & control unit 7 〇 210 and a complex programmable logic element 22 。. The protocol expansion module 221 is used to convert the test signals transmitted by the internal integrated circuit bus and the serial interface bus. In order to clearly explain the protocol conversion process of the present invention, please also refer to the "2nd drawing". In this context, the 'protocol expansion module 包括 includes the internal integrated circuit sink * the advanced first tH Huan (I2C tG FIFQ(10) She is like a 丨 丨 边 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 243 and a write-in first-in first-out register (Fff〇register for write) 244. The internal integrated circuit bus FIFO 241 sends the signal received by the internal integrated circuit bus to the write-first-in, first-out The register 244' is further transmitted to the serial peripheral interface bus FIFO module 242 one by one through the write-type FIFO register 244. The serial peripheral interface bus FIFO module 242 is received. The sequence is transmitted from the peripheral interface bus, and the serial peripheral interface bus FIFO 242 transmits the signal to the read-first-in-first-out register, and the read-first-in-first-out register 2 commits again. Signal forwarding to internal integrated circuit bus FIFO Group 24 internal integrated circuit bus FIFO first step and then through the internal integrated circuit bus to transmit the corresponding signal to the corresponding device. The column peripheral interface bus can be composed of various pure under the control of the software. For example, by a master Control the first peripheral component 231 of the single S (maSter MCU) and several slave controls
❹考第3圖」所不’其係為本發明之娜可編程邏輯元 件220對序列周邊介面匯流排之架構示意圖。一般而言，利用序 f几仟之左側係透過序 slave)連接至第—周邊元件 201227272 231，而在「第3圖」中的複雜可編程邏輯元件220之右側則透過 - ㈣整合電路匯流排32〇連接至第二周邊元件攻。換言之，第一 -周邊元件231會透過複雜可編程邏輯元件22〇對第二周邊元件攻 • 進行訊號的轉換。 在本發明的另一實施例包括基板管理控制單元跡複雜 1 呈邏輯元件22G觸咖。輸繼姆複雜可編程邏 輯兀件220。當複雜可編程邏輯元件22〇接收回應訊息時，複雜可 編程賴元件220將回應訊息傳送至輸出裝置，藉以通知測試人 貝該主機板的各·彳試項目的結果。輸出裝置可以是絲、斧八 或是發光二極體。 本發明所提供的周邊元件23〇狀態的偵測農置2〇〇不 網路接口進行相應_試。料，在本發财的娜可編程_ π件22〇可驅動内部整合電路匯流排汹向基板管理控制單元 取得各項周邊元件23〇的使用狀態。如此—來，就可以不用 的增加測試治具的開發成本’就可輯主機板進行測試。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以 定本發明’任何熟習姆技藝者，在顿離本發明之精神和2 内’當可作錢之更動細飾，因此本㈣之專鄉護範圍 本5兒明書所附之申請專利範圍所界定者為準。 、 【圖式簡單說明】 第1圖係為習知技術之主機板的架構示意圖。 第2A圖係為本發明之架構示意圖。 201227272 第2A圖係為本發明之本發明的協議轉換裝置的架構示意圖。 第3圖係為本發明之複雜可編程邏輯元件對序列周邊介面匯 流排之架構不意圖。 【主要元件符號說明】 主機板100 基板管理控制單元110 南橋晶片組121 切換邏輯單元122 序列埠123 網路連接端124 偵測裝置200 基板管理控制單元210 複雜可編程邏輯元件220 協議擴展模組221 資料緩存器222 周邊元件230 第一周邊元件231 第二周邊元件232 内部整合電路匯流排先進先出模組241 序列周邊介面匯流排先進先出模組242 讀取式先進先出暫存器243 寫入式先進先出暫存器244 201227272 序列周邊介面匯流排310 内部整合電路匯流排320Referring to Figure 3, "not" is a schematic diagram of the architecture of the serial programmable interface element 220 of the present invention. In general, the left side of the sequence f is connected to the first peripheral element 201227272 231, and the right side of the complex programmable logic element 220 in the "3rd picture" is transmitted through the - (four) integrated circuit bus. 32〇 is connected to the second peripheral component. In other words, the first peripheral component 231 can perform signal conversion on the second peripheral component through the complex programmable logic component 22 . Another embodiment of the present invention includes a substrate management control unit trace complex 1 in the logic element 22G. The input complex complex logic element 220 is transmitted. When the complex programmable logic component 22 receives the response message, the complex programmable component 220 transmits a response message to the output device to inform the tester of the results of the respective test items of the motherboard. The output device can be a wire, an axe or a light emitting diode. The detection of the status of the peripheral component 23 of the present invention is not determined by the network interface. In this case, the programmable data _ π piece 22〇 can drive the internal integrated circuit busbar to the substrate management control unit to obtain the use status of each peripheral component 23〇. In this way, it is possible to increase the development cost of the test fixture without having to test the motherboard. Although the present invention has been disclosed above in the foregoing preferred embodiments, it is not intended to be used in the context of the present invention, and it may be modified in the spirit and spirit of the present invention. The scope of the patent protection scope of this application is subject to the definition of the patent application scope attached to this book. [Simplified description of the drawings] Fig. 1 is a schematic diagram of the architecture of a motherboard of the prior art. Figure 2A is a schematic diagram of the architecture of the present invention. 201227272 FIG. 2A is a schematic diagram showing the architecture of the protocol conversion apparatus of the present invention. Figure 3 is a schematic diagram of the architecture of the complex programmable logic elements of the present invention for the sequence peripheral interface bus. [Main component symbol description] Motherboard 100 Baseboard management control unit 110 Southbridge chipset 121 Switching logic unit 122 Sequence 埠 123 Network connection terminal 124 Detection device 200 Baseboard management control unit 210 Complex programmable logic element 220 Protocol expansion module 221 Data buffer 222 peripheral component 230 first peripheral component 231 second peripheral component 232 internal integrated circuit bus FIFO module 241 serial peripheral interface bus FIFO 242 read FIFO register 243 write Incoming FIFO register 244 201227272 Serial peripheral interface bus 310 Internal integrated circuit bus 320