TWI518522B - Controlling and switching module capable of being applied in x86 systems for reading data - Google Patents

Description

Control and switching module for signal reading of X86 system

The invention relates to the related field of the electronic switching module, in particular to a control and switching module for signal reading of the X86 system.

SPI (Serial Peripheral Interface) is a signal transmission interface developed by Motorola® to be placed between a microcontroller and a peripheral chip. Please refer to the first figure, which is a sequence of peripheral interface architecture. As shown in the first figure, a microcontroller 11' couples a first peripheral wafer 12' and a second peripheral wafer 13' through its sequence peripheral interface. The serial peripheral interface of the microcontroller 11' includes a main data output pin 111' (MOSI: Master Output, Slave Input), a main data receiving pin 112' (MISO: Master Input, Slave Output), and a main A timing pin 113' (SCLK: Serial Clock), and at least one peripheral chip selection pin (SS: Slave Select).

The first figure shows a first peripheral wafer selection pin 114' and a second peripheral wafer selection pin 115', wherein the microcontroller is corresponding to the microcontroller 11', the first peripheral chip 12' applied to the sequence peripheral interface structure has a first slave data receiving pin 121', a first slave data output pin 122', a first slave timing pin 123', And a first selection signal receiving pin 124'. Moreover, similar to the first peripheral wafer 12', the second peripheral wafer 13' has a second slave data receiving pin 131', a second slave data output pin 132', and a second slave timing pin. 133', and a second selection signal receiving pin 134'. In the transmission architecture of the Sequence Peripheral Interface (SPI), the input and output of all data are synchronized with a clock signal generated by the microcontroller 11'.

Currently, the X86 system implements Ethernet switching (Ethernet). The purpose of the switch is to control the GPIO pin (General Purpose I/O, general-purpose input/output) of the main processor (CPU) through software to simulate the sequence peripheral interface similar to the one shown in the first figure. Data transfer between road switching. Please refer to the second figure, which is the GPIO data transmission architecture diagram of the X86 system. As shown in the second figure, the first GPIO pin GP0', the second GPIO pin GP1', the third GPIO pin GP2', and the fourth GPIO pin of a main processor 21' above the motherboard 20' The bit GP3' is respectively coupled to a timing pin 311' of an Ethernet switching chip 31', a selection pin 312', a slave data receiving pin 313', and a slave data output pin 314'. . In addition, the LAN pin 211' (Local Area Network) of the main processor 21' is coupled to the LAN pin 315' of the Ethernet switching chip 31'; and the Ethernet switching chip 31' Electrically connected to the motherboard 20' Multiple network communications 埠 40’.

In the GPIO data transmission architecture shown in the second figure, the first GPIO pin GP0' and the second GPIO pin GP1' are controlled by the software to respectively output a timing signal and a Netcom selection signal to the Ethernet. Switching the chip 31'; at the same time, the third GPIO pin GP2' and the fourth GPIO pin GP3' are respectively used as the main data output (MOSI: Master Output, Slave Input) and the main data receiving pin (MISO) via the software control. :Master Input, Slave Output). With this arrangement, the main processor 21' of the X86 system can control the network switching of the plurality of network communication ports 40' via the Ethernet switching chip 31' in an SPI-like manner.

The technical architecture shown in the second figure is currently used in X86 systems. However, the inventor of the present invention found in the practice that the GPIO data transmission architecture still has the following major defects:

(1) Refer to the GPIO data transmission signal diagram as shown in the third figure. As shown in the signal diagram (a) of the third figure, when the CPU is in a normal (normal) load, the GPIO data transmission signal will not cause signal delay; however, as shown in the signal diagram of the third figure ( b) As shown in the figure, once the CPU is under heavy load, the GPIO data transmission signal will generate a signal delay, and the signal delay will inevitably affect the correctness of the timing signal.

(2) In accordance with point (1) above, once the timing signal is considered to be correct due to excessive CPU load, the main processor 21' cannot be guaranteed to transmit to the Ethernet. Whether the data is written by one of the network switching chips 31' is correct, and it is necessary to repeatedly read the written data to confirm the correctness.

(3) In addition, the GPIO voltage level selected on different application platforms must also change. For example, the GPIO voltage level of the south bridge chip is 5V, and the GPIO voltage level of the hardware monitor (HWMON) is It is 3.3V.

Therefore, in view of the fact that the conventional SPI-based GPIO data transmission architecture shows many defects in practical operation, the inventor of the present invention tried to research and invent, and finally developed a control of the signal reading applied to the X86 system of the present invention. With switching modules.

The main object of the present invention is to provide a control and switching module for signal reading different from the conventional GPIO control technology, which is applied to an X86 system. The invention is to add a micro control unit between the main processing unit and the switching matrix unit; wherein, since the micro control unit communicates with the main processing unit via the I2C bus, the main processing unit can perform a read control The signal is first stored in the register of the micro control unit through the I2C bus, and then the micro control unit transmits the read control signal to at least one of the plurality of peripheral units through the sequence peripheral interface. In this manner, the main processing unit can read the transmission data from the plurality of peripheral units while ensuring that no data errors have occurred. Furthermore, since the invention is not used Any SPI write interface simulation software, so the control and switching module of the signal reading of the present invention is easy to import into any platform and has high scalability.

Therefore, in order to achieve the main object of the present invention, the inventor of the present invention proposes a control and switching module for signal reading applied to an X86 system, comprising: a main processing unit, which is disposed on a motherboard of an X86 system. a micro control unit is disposed on the motherboard and communicated to the main processing unit by an Inter-Integrated Circuit Bus (I2C bus); and a switching matrix unit (switch The fabric is disposed on the motherboard and electrically connected to a serial peripheral interface (SPI) of the micro control unit; wherein the switch matrix unit is further electrically connected to the plurality of peripheral units Wherein, the main processing unit uses a Field Programmable Gate Array (FPGA) and transmits a data read control signal to the micro control unit through the interactive integrated circuit bus; further, the micro control The unit reads the control signal according to the data and further further the at least one peripheral unit of the plurality of peripheral units through the sequence peripheral interface One reads out specific data transmission, and then transmits the particular data to the main processing unit through the interaction integrated circuit bus.

<present invention>

11‧‧‧Main processing unit

12‧‧‧Micro Control Unit

13‧‧‧Exchange matrix unit

10‧‧‧ Motherboard

120‧‧‧Interactive integrated circuit bus

16‧‧‧ peripheral units

130, 110‧‧‧ LAN feet

121‧‧‧Main timing pin

122‧‧‧ peripheral chip selection pin

123‧‧‧Master data output pin

124‧‧‧Master data receiving pin

131‧‧‧From timing feet

132‧‧‧Select signal receiving pin

133‧‧‧Receipt from data

134‧‧‧From the data output pin

<知知>

11’‧‧‧Microcontroller

12’‧‧‧First peripheral wafer

13’‧‧‧Second peripheral wafer

111’‧‧‧Master data output pin

112’‧‧‧Master data receiving pin

113’‧‧‧Main timing pin

114’‧‧‧First peripheral wafer selection pin

115'‧‧‧Second peripheral wafer selection pin

121’‧‧‧First receiving data from the pin

122’‧‧‧First data output pin

123’‧‧‧First slave timing pin

124’‧‧‧First choice signal receiving pin

131’‧‧‧Second data receiving pin

132’‧‧‧Second data output pin

133’‧‧‧Second slave timing pin

134’‧‧‧Second selection signal receiving position

20’‧‧‧ Motherboard

21’‧‧‧Main processor

GP0’‧‧‧First GPIO pin

GP1’‧‧‧second GPIO pin

GP2’‧‧‧ third GPIO pin

GP3’‧‧‧Fourth GPIO pin

31’‧‧‧Ethernet Switching Chip

311’‧‧‧Timed feet

312’‧‧‧Selected feet

313’‧‧‧ Receiving feet from data

314’‧‧‧From the data output pin

211’‧‧‧LAN feet

315’‧‧‧LAN feet

40’‧‧‧Network Communication埠

The first figure is a sequence peripheral interface architecture diagram; the second diagram is the GPIO data transmission architecture diagram of the X86 system; the third diagram is the GPIO data transmission signal diagram; and the fourth diagram is one of the inventions applied to the X86 system. The architecture diagram of the control and switching module for signal reading.

In order to more clearly describe a control and switching module for signal reading of the X86 system proposed by the present invention, a preferred embodiment of the present invention will be described in detail below with reference to the drawings.

Please refer to the fourth figure, which is an architectural diagram of a control and switching module (hereinafter referred to as a control and switching module for signal reading) applied to the signal reading of the X86 system. The signal reading control and switching module of the present invention can be applied to various X86 systems, such as industrial computers and industrial servers, thereby providing the main processor of the X86 system capable of operating the X86 system under normal (normal) load conditions. A plurality of peripheral modules perform control and switching of data (signal) reading.

As shown in the fourth figure, the control and switching module of the signal reading system mainly includes: a main processing unit 11, a micro control unit 12 and a switch fabric 13; wherein the main processing unit 11 Based on The X86 system is connected to one of the motherboards 10, and the micro control unit 12 is disposed on the motherboard 10 and communicated by an Inter-Integrated Circuit Bus (I2C bus) 120. The main processing unit 11. In addition, the switch fabric 13 is disposed on the motherboard 10 and electrically connected to a Serial Peripheral Interface (SPI) of the micro control unit 12; and, the switch fabric unit ( The switch fabric 13 is further electrically connected to a plurality of peripheral units 16.

In the present invention, the peripheral unit 16 may be a video drive processor, an audio drive processor, a sensor, a memory read/write processor, or a network communication component. And, corresponding to the foregoing various peripheral units 16, the switching matrix unit 13 may be any one of the following: a video switching matrix unit, an audio switching matrix unit, a sensor switching matrix unit, a memory switching matrix unit, or a network switching matrix unit. .

In the control and switching module of the signal transmission shown in FIG. 4, the switching matrix unit 13 is the Ethernet Switch Matrix, so that the LAN pin 130 of the switching matrix unit 13 is coupled. Up to one of the main processing units 11 LAN pin 110. In addition, the sequence peripheral interface of the micro control unit 12 has: a main timing pin 121 (SCLK: Serial Clock), at least one peripheral chip selection pin 122 (SS: Slave Select), and a main data output pin 123. (MOSI: Master Output, Slave Input), and a master data receiving pin 124 (MISO: Master Input, Slave Output).

As described above, the switch matrix unit 13 also has one of the slave terminal pins 131 electrically connected to the master sequence pin 121 and electrically connected to the peripheral chip select pin 122. One of the main data output pins 123 is electrically connected to the data receiving pin 133 and electrically connected to one of the main data receiving pins 124 from the data output pin 134. Thus, by the above-mentioned main processing unit 11, the micro control unit 12 and the switching matrix unit 13 are connected, the main processing unit 11 can use a field editable gate gate array (FPGA) and integrate through the interaction. The circuit bus 120 can store a read control signal in the register of the micro control unit 12 through the I2C bus. Further, the micro control unit 12 transmits the read control signal to the serial control interface through the sequence peripheral interface. At least one of the plurality of peripheral units 16 can, in such a manner, the main processing unit 11 can read the transmission data from the plurality of peripheral units 16 while ensuring that no data errors have occurred.

It should be further noted that the data (signal) reading control is implemented by the following steps: Step (1): The main processing unit 11 sends a read request signal (usually a low) to the micro control unit 12. Positioning voltage signal); step (2): the micro control unit 12 performs a read address setting on the register; step (3): the micro control unit 12 performs a data storage on the register Space setting; step (4): the micro control unit 12 changes its state flag of the register to a read status bit, for example, the read status bit is bit 0; step (5) ): confirm whether the status flag of the register has been changed to the read status bit, if yes, proceed to step (6); if otherwise, repeat the foregoing step (4); and step (6): the micro control The unit 12 sends a completion setting signal (usually a low level voltage signal) to the main processing unit 11.

Thus, the above description has clearly and in detail introduced the control and switching module of the present invention for signal reading of the X86 system; and, as described above, the present invention has the following advantages:

(1) Unlike the prior art, the GPIO pin of the main processor is controlled by the software to realize the control and switching of the signal transmission of the plurality of peripheral chips (modules) by the main processor, and the present invention is applied to the main processing unit 11 and the exchange. A micro control unit 12 is added between the switch fabrics 13; wherein, since the micro control unit 12 communicates with the main processing unit 11 via the I2C bus, the main processing unit 11 can first read a control signal. The I2C bus is stored in the register of the micro control unit 12, and then the micro control unit 12 transmits the read control signal to at least one of the plurality of peripheral units 16 through the sequence peripheral interface. In this manner, the main processing unit 11 can read the transmission data from the plurality of peripheral units 16 while ensuring that no data error has occurred.

(2) In addition, since the control and switching module of the signal reading of the present invention is a full hardware architecture and does not include any SPI write interface simulation software, it is easy to control and switch the signal reading of the present invention. Imported to any platform and highly scalable. For example, it can be configured on the motherboard of the X86 according to different peripheral units 16 (for example, a video driving processor, an audio driving processor, a sensor, a memory read/write processor, or a network communication component). The switching matrix unit 13 (for example, a video switching matrix unit, an audio switching matrix unit, a sensor switching matrix unit, a memory switching matrix unit, or a network switching matrix unit) can be matched with the main processing unit 11 and a micro control Unit 12 performs control and switching of data (signal) readings on any of peripheral units 16.

It is to be understood that the foregoing detailed description of the embodiments of the present invention is not intended to Both should be included in the scope of the patent in this case.

11‧‧‧Main processing unit

12‧‧‧Micro Control Unit

13‧‧‧Exchange matrix unit

10‧‧‧ Motherboard

120‧‧‧Interactive integrated circuit bus

16‧‧‧ peripheral units

130, 110‧‧‧ LAN feet

121‧‧‧Main timing pin

122‧‧‧ peripheral chip selection pin

123‧‧‧Master data output pin

124‧‧‧Master data receiving pin

131‧‧‧From timing feet

132‧‧‧Select signal receiving pin

133‧‧‧Receipt from data

134‧‧‧From the data output pin

Claims (9)

A control and switching module for signal reading of an X86 system includes: a main processing unit, which is disposed on a motherboard of an X86 system; a micro control unit is disposed on the motherboard And communicating with the main processing unit by an Inter-Integrated Circuit Bus (I2C bus); and a switch fabric, which is disposed on the motherboard and electrically Connecting to a serial peripheral interface (SPI) of the micro control unit; wherein the switch fabric is further electrically connected to a plurality of peripheral units; wherein the main processing unit uses one edit a Field Programmable Gate Array (FPGA) and transmit a data read control signal to the micro control unit through the interactive integrated circuit bus; further, the micro control unit reads the control signal according to the data The sequence peripheral interface further reads out a specific data transmitted by at least one of the plurality of peripheral units, and further transmits the interaction Coincidence circuit transmits the bus-specific data to the main processing unit. Signal reading for X86 system as described in item 1 of the patent application scope The control and switching module is configured, wherein the serial peripheral interface of the micro control unit has: a main timing pin (SCLK: Serial Clock), at least one peripheral chip selection pin (SS: Slave Select), and a main Data output pin (MOSI: Master Output, Slave Input), and a master data receiving pin (MISO: Master Input, Slave Output). The control and switching module applied to the signal reading of the X86 system, as described in claim 1, wherein the switching matrix unit may be any one of the following: a video switching matrix unit, an audio switching matrix unit, and a sensing Switch fabric unit, memory switch matrix unit, or network switch matrix unit. The control and switching module for signal reading of the X86 system, as described in claim 1, wherein the data reading control is implemented by the following steps: (1) the main processing unit is to the micro The control unit sends a read request signal; (2) the micro control unit performs a read address setting on a register in the micro control unit; (3) the micro control unit performs a read address on the register Data storage space setting; (4) the micro control unit changes its state flag of the register Further reading the status bit; (5) confirming whether the status flag of the register has been changed to the read status bit, and if yes, proceeding to step (6); otherwise, repeating the foregoing step (4) And (6) the micro control unit sends a completion setting signal to the main processing unit. The control and switching module applied to the signal reading of the X86 system, as described in claim 2, wherein the switching matrix unit further has: a slave timing pin, electrically connected to the master timing pin a selection signal receiving pin is electrically connected to the peripheral chip selection pin; a data receiving pin is electrically connected to the main data output pin; and a data output pin is electrically connected. Connect to the main data receiving pin. The control and switching module for signal reading of the X86 system, as described in claim 3, wherein the peripheral unit can be any of the following: a video driving processor, an audio driving processor, and a sensor. , memory read/write processor, or network communication component. Signal reading applied to X86 system as described in item 4 of the patent application scope The control and switching module is selected, wherein the read request signal is a low level voltage signal. The control and switching module for signal reading of the X86 system, as described in claim 4, wherein the read status bit is bit 0. The control and switching module for signal reading of the X86 system, as described in claim 4, wherein the completion setting signal is a low level voltage signal.