TWI712892B - Complex programmable logic device and operation method thereof - Google Patents

Abstract

A complex programmable logic device includes a SGPIO analyzing circuit, a I2C analyzing circuit and a first multiplexer. The SGPIO analyzing circuit has a plurality of port analyzing circuits, a detecting circuit and a processing circuit. Each port analyzing circuit receives an input signal and outputs a first data. The detecting circuit detects the input signal of the first port analyzing circuit to output a test signal. The processing circuit captures port data included in the first data outputted by at least one of the port analyzing circuits as a first control signal according to the test signal. The I2C analyzing circuit analyzes a data flow in order to output a second control signal according to an address command related to an address message, a control command and an input data. The first multiplexer selects the first control signal or the second control to be outputted according to a detection signal.

Description

Complex programmable logic device and its operating method

The present invention relates to a complex programmable logic device, especially a complex programmable logic device using I2C and SGPIO analysis modules.

At present, the complex programmable logic device (CPLD) of the hard disk backplane mainly performs hard disk lighting, hard disk power-on control, NVME timing control, and hard disk status reading. However, the I2C and SGPIO parsing modules used by the complex programmable logic device are quite complex and not compact enough, resulting in insufficient use of the resources of the complex programmable logic device. If the hard disk backplane needs to support different types of interfaces (such as SATA and NVME) at the same time, a higher-end complex programmable logic device must be used. However, this will inevitably lead to an increase in the use cost.

Furthermore, different types of hard disk backplanes usually require different types of complex programmable logic devices. This will result in a large number of required complex programmable logic devices and their firmware versions, resulting in high maintenance costs. Therefore, there is a need for a complex programmable logic device that can integrate different types of hard disk backplanes while meeting the functional requirements of different types of backplanes.

The present invention provides a complex programmable logic device, mainly through specific I2C and SGPIO analysis methods, so that the complex programmable logic device can realize all the functions of different types of hard disk backplanes at the same time, so as to achieve the function integration of the complex programmable logic device and reduce Consume a lot of resources and reduce costs.

An embodiment of the present invention discloses a complex programmable logic device including a serial universal input/output analysis circuit, an integrated circuit bus analysis circuit and a first multiplexer. The serial universal input and output analysis circuit includes multiple port analysis circuits, detection circuits and processing circuits. Each The port analysis circuit has an input terminal and an output terminal, the input terminal is used for receiving the first input signal, and the output terminal is used for outputting the first data. The detection circuit is electrically connected to the input end of the first port analysis circuit of the port analysis circuits, and detects the input signal of the first port analysis circuit to output the detection signal. The processing circuit is electrically connected to the output terminals of the port analysis circuits and the detection circuit, and the processing circuit captures the first data output from at least a part of the output terminals of the port analysis circuits according to the detection signal The port data is used as the first control signal. The integrated circuit bus analysis circuit is used to analyze the data stream to generate address information, control commands and input data, and output a second control signal according to the address commands, control commands and input data associated with the address information. The first multiplexer is used for selectively outputting the first control signal or the second control signal according to the detection signal.

Another embodiment of the present invention discloses an operation method of a complex programmable logic device, which includes the following steps: a plurality of port analysis circuits are used to respectively receive first input signals and correspondingly output first data; and a detection circuit detects the connections The first input signal of the first port analysis circuit of the port analysis circuit is used to output the detection signal; the processing circuit captures the output of at least a part of the port analysis circuits according to the detection signal The port data of the first data is used as the first control signal; the integrated circuit bus circuit parses the data stream to generate address information, control commands and input data, and according to the address commands, control commands and input data associated with the address information Output the second control signal; the first multiplexer selects the output of the first control signal or the second control signal according to the detection signal.

In summary, in the complex programmable logic device and its operating method proposed by the present invention, the detection circuit in the serial universal input and output analysis circuit is mainly used to detect the input signal of the first port analysis circuit. What kind of signal (for example, four-port or eight-port signal), and the processing circuit selectively captures at least part of the port data output by the port analysis circuit according to the signal type of the input signal to output the first control signal. On the other hand, the multi-address response characteristic of the circuit is analyzed through the integrated circuit bus to output the second control signal. With the above-mentioned SGPIO and I2C analysis functions, complex programmable logic devices can be configured in a streamlined module It can realize all the functions of different types of hard disk backplanes at the same time, and achieve the function integration of complex programmable logic devices, thereby reducing resource consumption and reducing costs.

The above description of the content of the disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the patent application scope of the present invention.

1: Complex programmable logic device

10: Serial universal input and output analysis circuit

101~103: Port analysis circuit

104: detection circuit

105: processing circuit

1051: first subcircuit

1052: second subcircuit

1053: second multiplexer

11: Integrated circuit bus analysis circuit

110, 111: Multi-address response circuit

12: The first multiplexer

IN1: Input terminal

ON1: output

S1~S3: the first input signal

D1~D3: first data

CN1: The first control signal

CN2: Second control signal

C1, C2: data flow

DS: Detection signal

FIG. 1 is a functional block diagram of a complex programmable logic device according to an embodiment of the present invention.

2 is a detailed functional block diagram of the complex programmable logic device depicted in the embodiment of FIG. 1 according to the present invention.

FIG. 3 is a method flowchart of the operation method of a complex programmable logic device according to an embodiment of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments, and the content is sufficient to enable anyone familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of patent application and the drawings Anyone who is familiar with the relevant art can easily understand the related purpose and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention by any viewpoint.

Please refer to FIG. 1. FIG. 1 is a functional block diagram of a complex programmable logic device according to an embodiment of the present invention. As shown in FIG. 1, the complex programmable logic device 1 includes a serial universal input/output analysis circuit 10, an integrated circuit bus analysis circuit 11 and a first multiplexer 12. The serial universal input/output analysis circuit 10 includes a plurality of port analysis circuits 101 to 103, a detection circuit 104, and a processing circuit 105. Each port analysis circuit has an input terminal and an output terminal, wherein the input terminal is used for receiving the first input signal, and the output terminal is used for outputting the first data. In practice, the complex programmable logic device 1 can be installed on the backplane (not shown in the figure), and it is provided according to the interface types supported by the backplane. Provides different signal analysis functions to perform different hard disk LFD lighting.

Taking the embodiment of FIG. 1 as an example, the port analysis circuit 101 has an input terminal IN1 and an output terminal ON1. The input terminal IN1 receives the first input signal S1 and the output terminal ON1 outputs the first data D1. The port analysis circuit 102 has an input terminal IN2 and an output terminal ON2. The input terminal IN2 receives the first input signal S2 and the output terminal ON2 outputs the first data D2. The port analysis circuit 103 has an input terminal IN3 and an output terminal ON3. The input terminal IN3 receives the first input signal S3 and the output terminal ON3 outputs the first data D3. In practice, the port resolution circuits 101~103 can be connected to the platform path controller (PCH) or the host bus adapter (HBA), and the first input signal S1~S3 can be from the platform path controller (PCH). ) Or the serial general-purpose input output (SGPIO) signal of the host bus adapter (HBA), where the platform path controller (PCH) corresponds to the 8 port signal, and the host bus adapter ( HBA) corresponds to the 4 port signal.

The detection circuit 104 is electrically connected to the input terminal IN1 of the first port analysis circuit (ie, the port analysis circuit 101) of the port analysis circuits 101 to 103, and the detection circuit 104 detects the first input of the port analysis circuit 101 The signal S1 is used to output the detection signal TS. In detail, the detection circuit 104 is used to determine the number of ports of the first input signal S1 to generate a detection result, and output the detection signal TS according to the detection result. In other words, in one embodiment, the detection signal TS can indicate what kind of signal the first input signal S1 belongs to (or how many ports it has), such as a four-port signal or an eight-port signal.

The processing circuit 105 is electrically connected to the output terminals ON1 to ON3 of the port analysis circuits 101 to 103 and the detection circuit 104. The processing circuit 105 extracts the port data of the first data output by the output ends of at least a part of the port analysis circuits 101 to 103 according to the detection signal TS as the first control signal CN1. More specifically, the processing circuit 105 selects the port data of a part of the first data output by the port analysis circuit or selects to capture according to the type (number of ports) of the first input signal S1 indicated by the detection signal TS The port data of the first data output by all the port analysis circuits is used as the first control signal CN1.

For example, if the detection signal TS indicates that the input signal S1 is an 8-port signal, it means that the SATA interface is connected to the PCH. At this time, the processing circuit 105 captures a part of the port analysis circuit (such as the port analysis circuit). The port data of the first data (such as the first data D1, D2) output by the output terminals (such as the output terminals ON1 and ON2) of 101 and 102) are used as the first control signal CN1. If the detection signal TS indicates that the input signal S1 is a 4-port signal, it means that the SATA interface is connected to the HBA. At this time, the processing circuit 105 captures the output of all port analysis circuits (such as port analysis circuits 101~103) The port data of the first data (such as the first data D1 to D3) output by the terminals (such as the output terminals ON1 to ON3) is used as the first control signal CN1.

The integrated circuit bus analysis circuit 11 is used to parse the data streams C1 and C2 to generate respective address information, control commands and input data, and output the first according to the respective address commands, control commands and input data associated with the address information 2. Control signal CN2. In practice, the integrated circuit bus analysis circuit 11 is connected to one or more processors, and receives data streams (for example, data streams C1 and C2) from the one or more processors. In the embodiment of FIG. 1, the integrated circuit bus analysis circuit 11 obtains individual address information, control commands and input data by analyzing the data streams C1 and C2, and according to individual address commands, control commands and input data related to address information Output the second control signal CN2.

The first multiplexer 12 is used for selectively outputting the first control signal CN1 or the second control signal CN2 according to the detection signal DS. The detection signal DS can indicate whether the current backplane supports SATA or NVME to determine whether to output the first control signal CN1 or the second control signal CN2, where the first control signal CN1 and the second control signal CN2 They are used for LED lighting for SATA and NVME respectively. For example, the signal level corresponding to SATA is 1, and the signal level corresponding to NVME is 0. When the detection signal DS indicates the signal level is 1, the first multiplexer 12 turns on the path from the serial universal input/output analysis circuit 10 to the output end of the first multiplexer 12 to output the first control signal CN1. Conversely, when the detection signal DS indicates the signal level is 0, the first multiplexer 12 turns on the path from the integrated circuit bus analysis circuit 11 to the output end of the first multiplexer 12 to output the second control signal CN2.

Through the structure of the complex programmable logic device 1 proposed in the present invention to perform hard disk LED lighting, the number of independent analysis circuits under the traditional architecture can be greatly reduced, and the purpose of saving resources can be achieved with a simplified circuit configuration.

Please refer to FIG. 2. FIG. 2 is a detailed functional block diagram of the complex programmable logic device depicted in the embodiment of FIG. 1 of the present invention. Figure 1 and Figure 2 have roughly the same architecture, but the difference is that the processing circuit 105 of Figure 2 includes a first sub-circuit 1051, a second sub-circuit 1052, and a second multiplexer 1053, and the integrated circuit bus analysis circuit 11 includes multiple Address response circuits 110, 111. The first sub-circuit 1051 has an input terminal P1 and an output terminal Q1, and the input terminal P1 of the first sub-circuit 1051 is electrically connected to the output terminals ON1 to ON3. The first sub-circuit 1051 is used to capture the port data of the first data output by a part of the port analysis circuits 101 to 103.

The second sub-circuit 1052 has an input terminal P2 and an output terminal Q2, and the input terminal P2 of the second sub-circuit 1052 is electrically connected to the output terminals ON1 to ON3. The second sub-circuit 1052 is used to capture the port data of the first data output by each port analysis circuit.

The second multiplexer 1053 is electrically connected to the output terminal Q1 of the first sub-circuit 1501, the output terminal Q2 of the second sub-circuit 1502 and the first multiplexer 12. The second multiplexer 1053 conducts the path from the output terminal Q1 of the first sub-circuit 1051 or the output terminal Q2 of the second sub-circuit 1052 to the first multiplexer 12 according to the detection signal TS.

In practice, in a situation, when the detection signal TS indicates that the input signal S1 is an 8-port signal, the first sub-circuit 1051 will capture the first data output by the port analysis circuits 101~102 The port data of D1 and D2 are used as the first control signal CN1. In another situation, when the detection signal TS indicates that the input signal S1 is a 4-port signal, the second sub-circuit 1052 will capture the port data of the first data D1~D3 output by the port analysis circuits 101~103 As the first control signal CN1.

On the other hand, the multiple address response circuits 110 and 111 respectively parse the data streams C1 and C2 to obtain corresponding address information (address), input data (value) and control commands (command) individually. Among them, multiple preset addresses are preset in the multiple address response circuits 110 and 111 respectively. The multi-address response circuits 110 and 111 respectively determine which of these preset addresses their address information responds to (or corresponds to), and records the response preset addresses and outputs them as address commands. The multiple address response circuits 110 and 111 respectively use address commands and control commands to select based on input data to individually output corresponding data, and the individually output data can be used as the second control signal CN2. Through the feature of multi-address response, the number of IC slave modules (I2C slaves) used under the traditional architecture can be reduced, thereby greatly reducing the resource occupation of complex programmable logic devices.

In one embodiment, the detection signal TS indicates that the first input signal S1 of the first port analysis circuit 101 is an eight-port signal, and the first sub-circuit 1051 extracts the data from the first port analysis circuit 101 according to the detection signal TS. All port values in the port data of the output first data D1, and some port values in the port data of the first data output by another port analysis circuit are retrieved. In detail, when it is determined that the input signal of the first port analysis circuit 101 is an eight-port signal, the first sub-circuit 1051 will capture all the port data in the first data D1 output by the port analysis circuit 101 Port value, such as 8 port data. On the other hand, the first sub-circuit 1051 also captures the port values of four of the eight ports in the port data of the first data D1 output by the port analysis circuit 102.

In this case, the second sub-circuit 1052 does not capture the port data of the first data output by any port analysis circuit, and the first sub-circuit 1051 outputs the port value captured above, and the second sub-circuit The multiplexer 1053 can output the port values as the first control signal CN1 according to the path from the detection signal TS conducting the first sub-circuit 1051 to the output terminal of the second multiplexer 1053.

In another embodiment, the detection signal TS indicates that the first input signal S1 of the first port analysis circuit 101 is a four-port signal, and the second sub-circuit 1052 captures all the output of the port analysis circuit according to the detection signal TS Part of the port value in the port data of the first data. In detail, when it is determined that the input signal of the first port analysis circuit 101 is a four-port signal, the first sub-circuit 1051 will capture the first data D1~D3 output by all the port analysis circuits 101~103 Part of the port value in the port data. For example, the port values of four of the eight ports in the port data of the first data D1 to D3 of each port analysis circuit 101 to 103 are captured. That is to analyze the power at each port The port data (eight-port signal) of the first data output by each channel takes the port value of four ports.

In this case, the first sub-circuit 1051 will not capture the port data of the first data output by any port analysis circuit, and the second sub-circuit 1052 will output the port value captured above, and the second The multiplexer 1053 can output the port values as the first control signal CN1 according to the path from the detection signal TS on the first sub-circuit 1051 to the output terminal of the second multiplexer 1053.

Please refer to FIG. 3. FIG. 3 is a method flowchart of a complex programmable logic device operation method according to an embodiment of the present invention, which is applicable to the complex programmable logic device 1 of FIGS. 1 and 2. As shown in the figure, in step S11, a plurality of port analysis circuits 101 to 103 respectively receive the first input signals S1 to S3 and correspondingly output the first data D1 to D3. In step S12, the detection circuit 104 detects the first input signal S1 of the first port analysis circuit 101 of the port analysis circuits 101 to 103, and outputs the detection signal TS accordingly. In step S13, the processing circuit 105 retrieves the port data of the first data output by at least a part of the port analysis circuits 101 to 103 according to the detection signal TS as the first control signal CN1. In step S14, the integrated circuit bus circuit 11 parses the data stream to generate address information, control commands and input data, and outputs the second control signal CN2 according to the address commands, control commands and input data associated with the address information . In step S15, the first multiplexer 12 selects and outputs the first control signal CN1 or the second control signal CN2 according to the detection signal DS.

In one embodiment, when the detection signal TS indicates that the input signal of the first port analysis circuit 101 is an eight-port signal, the processing circuit 105 extracts at least a part of the connections of the port analysis circuits according to the detection signal TS. The step of using the port data of the first data output by the port analysis circuit as the first control signal CN1 includes: using the first sub-circuit 1051 in the processing circuit 105 to extract the data from the first port analysis circuit 101 according to the detection signal TS All port values in the port data of the output first data D1, and capture the port data of the first data (for example, the first data D2) output by another port analysis circuit (for example, the port analysis circuit 102) Part of the port value.

In one embodiment, when the detection signal TS indicates that the input signal S1 of the first port analysis circuit 101 is a four-port signal, the processing circuit 105 extracts at least a part of the port analysis circuits according to the detection signal TS. The step of using the port data of the first data output by the port analysis circuit as the first control signal CN1 includes: extracting all the port analysis by the second sub-circuit 1052 in the processing circuit 105 according to the detection signal TS Some port values in the port data of the first data D1 to D3 output by the circuits 101 to 103.

In summary, in the complex programmable logic device and its operating method proposed by the present invention, the detection circuit in the serial universal input and output analysis circuit is mainly used to detect the input signal of the first port analysis circuit. What kind of signal (for example, four-port or eight-port signal), and the processing circuit selectively captures at least part of the port data output by the port analysis circuit according to the signal type of the input signal to output the first control signal. On the other hand, the multi-address response characteristic of the circuit is analyzed through the integrated circuit bus to output the second control signal. With the above-mentioned SGPIO and 12C analysis functions, the complex programmable logic device can realize all the functions of different types of hard disk backplanes at the same time under the simplified module configuration, and achieve the functional integration of the complex programmable logic device. Reduce resource consumption and reduce costs.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. All changes and modifications made without departing from the spirit and scope of the present invention fall within the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the attached patent scope.

1: Complex programmable logic device

10: Serial universal input and output analysis circuit

101~103: Port analysis circuit

104: detection circuit

105: processing circuit

11: Integrated circuit bus analysis circuit

12: The first multiplexer

IN1: Input terminal

ON1: output

S1~S3: the first input signal

D1~D3: first data

CN1: The first control signal

CN2: Second control signal

C1, C2: data flow

DS: Detection signal

Claims (8)

A complex programmable logic device includes: a serial universal input and output analysis circuit, including: a plurality of port analysis circuits, each of the port analysis circuit has an input terminal and an output terminal, the input terminal is used to receive a A first input signal, and the output terminal is used to output a first data; a detection circuit electrically connected to the input terminal of the first port analysis circuit of the port analysis circuits, and detects the first connection The first input signal of the port analysis circuit to output a detection signal; and a processing circuit electrically connected to the output ends of the port analysis circuits and the detection circuit, and the processing circuit captures the detection signals according to the detection signal Port data of the first data output by at least a part of the output terminals in the port analysis circuit is used as a first control signal; an integrated circuit bus analysis circuit for analyzing a data stream to generate address information , A control command and an input data, and output a second control signal according to an address command, the control command and the input data associated with the address information; and a first multiplexer for outputting a second control signal according to a detection signal Select to output the first control signal or the second control signal. The complex programmable logic device according to claim 1, wherein the processing circuit includes: a first sub-circuit having an input terminal and an output terminal, and the input terminal of the first sub-circuit is electrically connected to the connection ports The output terminals of the analysis circuit, the first sub-circuit is used to capture the port data of the first data output by a part of the port analysis circuits; a second sub-circuit has an input terminal and a Output terminal, the input terminal of the second sub-circuit is electrically connected to the output terminals of the port analysis circuits, and the second sub-circuit is used to capture the first data output by each port analysis circuit Port data; and a second multiplexer electrically connected to the output end of the first sub-circuit, the output end of the second sub-circuit and the first multiplexer, the second multiplexer according to the The detection signal conducts the path from the output terminal of the first sub-circuit or the output terminal of the second sub-circuit to the first multiplexer. The complex programmable logic device according to claim 2, wherein the detection signal indicates that the first input signal of the first port analysis circuit is a four-port signal or an eight-port signal. The complex programmable logic device according to claim 2, wherein the detection signal indicates that the first input signal of the first port analysis circuit is an eight-port signal, and the first sub-circuit extracts according to the detection signal All port values in the port data of the first data output by the first port analysis circuit, and part of the port values in the port data of the first data output by another port analysis circuit are captured. The complex programmable logic device according to claim 2, wherein the detection signal indicates that the first input signal of the first port analysis circuit is a four-port signal, and the second sub-circuit captures according to the detection signal All the port analysis circuits output partial port values in the port data of the first data. A method for operating a complex programmable logic device includes: using a plurality of port analysis circuits to respectively receive a first input signal and correspondingly outputting a first data; using a detection circuit to detect the first of the port analysis circuits According to the first input signal of the port analysis circuit, a detection signal is output; and a processing circuit is used to extract the first data output by at least a part of the port analysis circuits in the port analysis circuits according to the detection signal The port data is used as a first control signal; an integrated circuit bus circuit parses a data stream to generate an address information, a control command and an input data, and according to an address command, the address command associated with the address information A second control signal is output by the control command and the input data; and a first multiplexer is used to selectively output the first control signal or the second control signal according to a detection signal. The method for operating a complex programmable logic device according to claim 6, wherein when the detection signal indicates that the first input signal of the first port analysis circuit is an eight-port signal, the processing circuit is based on the The detection signal captures the port data of the first data output by at least a part of the port analysis circuits in the port analysis circuits as the first control signal including: using a first sub-circuit in the processing circuit according to the The detection signal captures all port values in the port data of the first data output by the first port analysis circuit, and captures part of the port data of the first data output by another port analysis circuit Port value. The method for operating a complex programmable logic device according to claim 6, wherein when the detection signal indicates that the first input signal of the first port analysis circuit is a four-port signal, the processing circuit is based on the The detection signal captures the port data of the first data output by at least a part of the port analysis circuits in the port analysis circuits as the first control signal including: using a second sub-circuit in the processing circuit according to the The detection signal captures all partial port values in the port data of the first data output by the port analysis circuits.

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