JP2004271282A - High-speed serial controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To debug a circuit section which does not depend on a PHY circuit, without newly preparing an expensive measuring instrument, in a high-speed serial controller incorporating the PHY circuit. <P>SOLUTION: A test circuit 2 is connected to each interface section of the PHY circuits 3, 8 that are provided at a physical layer and convert an analog signal flowing to wiring into a digital signal, and LINC circuits 4, 7 that are provided at a data link layer, adjacent to the physical layer for converting data converted to a digital signal by the PHY circuits 3, 8 into data in a prescribed format. Then, parallel data, flowing to the interface sections, are observed directly by means of a serial test interface 25. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a high-speed serial controller, and more particularly, to a high-speed serial controller with a built-in test circuit for debugging a built-in digital signal processing unit.
[0002]
[Prior art]
One of data transfer methods in a computer system or the like is a serial transfer method. Examples of the serial bus include Ethernet® (IEEE802.3), USB (Universal Serial Bus), and IEEE1394. The high-speed serial interface is one of the core technologies for realizing an interface in a new digital consumer device that integrates a computer system and an AV (audio / visual) device. Standardization of high-speed technology including high-speed serial interface has been activated.
[0003]
Normally, a high-speed serial controller converts an analog signal flowing between wirings into a digital signal in a physical layer IC (hereinafter, referred to as a PHY-IC) and transfers the digital signal to a data link layer IC (LINC-IC). Then, the data is transmitted and received by converting the data into a prescribed format. Conventionally, the PHY-IC has been manufactured as an analog IC chip composed of an analog circuit. The LINC-IC is manufactured as a digital IC chip composed of a digital circuit. Therefore, the conventional high-speed serial controller has a two-chip configuration including an analog IC chip and a digital IC chip.
[0004]
In recent years, with the shortening of electronic devices and cost reduction, it has been promoted to combine a PHY-IC and a LINC-IC on the same chip to form a single chip. In addition, many of the new standard interface standards currently proposed are of the high-speed serial transfer system. Therefore, in the future, a circuit in which a physical layer circuit (hereinafter, referred to as a PHY circuit) and a data link layer circuit (hereinafter, referred to as a LINC circuit) are mounted on the same chip, and all interfaces are constituted by high-speed serial interfaces The development of becomes active.
[0005]
However, since the PHY circuit converts the parallel data sent from the LINC circuit into high-speed serial data and outputs it to the wiring, the difficulty of the measurement of the PHY circuit increases as the speed increases. Therefore, in order to evaluate a high-speed serial controller, a very expensive measuring instrument is required.
[0006]
Meanwhile, a high-speed serial bus controller device having a function of generating an arbitrary error packet has been proposed (see Patent Document 1). Further, in a semiconductor integrated circuit device provided with a serial bus control circuit, a configuration has been proposed in which an analog circuit section and a digital circuit section are completely separated from each other for testing (see Patent Document 2).
[0007]
[Patent Document 1]
JP 2000-174850 A [Patent Document 2]
JP-A-6-94805
[Problems to be solved by the invention]
As described above, an expensive measuring instrument is required to evaluate a circuit incorporating a high-speed serial interface and a PHY circuit. For this reason, there is a problem that the existing environment for evaluation cannot be used, that is, the evaluation cannot be performed unless the environment includes expensive measuring instruments.
[0009]
The present invention has been made to solve the above problems, and provides a high-speed serial controller capable of debugging a circuit portion independent of a PHY circuit without preparing a new expensive measuring instrument. The purpose is to:
[0010]
[Means for Solving the Problems]
In order to solve the above-mentioned problems and achieve the object, a high-speed serial controller according to the present invention is provided in a physical layer, and includes a first control unit for converting an analog signal flowing through a wiring into a digital signal. A second control unit provided in a data link layer adjacent to the physical layer and configured to convert data converted into a digital signal by the first control unit into data of a prescribed format; and the first control unit. And a test unit connected to an interface between the control unit and the second control unit, and an output unit for outputting parallel data flowing through the interface unit.
[0011]
According to the first aspect of the present invention, the parallel data flowing through the interface between the first control means and the second control means is output from the output means.
[0012]
Further, in the high-speed serial controller according to the invention described in claim 2, in the invention described in claim 1, the test means outputs an output to the output means during the evaluation by the first control means and the first control means. A switching unit for switching from an output of the interface unit in the first combination with the second control unit to an output of the interface unit in the second combination of the first control unit and the second control unit; It is characterized by the following.
[0013]
According to the second aspect of the present invention, the output to the output unit is evaluated by the switching unit during the evaluation from the output of the interface unit of the first combination of the first control unit and the second control unit. Is switched to the output of the interface unit of the second combination of the first control means and the second control means.
[0014]
According to a third aspect of the present invention, in the high-speed serial controller according to the first or second aspect, the test unit is generated by a data generation unit that generates parallel data and the data generation unit. The data is transferred to an interface unit of a first combination of the first control unit and the second control unit and an interface unit of a second combination of the first control unit and the second control unit. Data transfer means for transferring.
[0015]
According to the third aspect of the present invention, the parallel data generated by the data generating means is provided with an interface unit of a first combination of the first control means and the second control means, and the first control means. And the second control means is transferred to the interface unit of the second combination.
[0016]
The high-speed serial controller according to a fourth aspect of the present invention is the high-speed serial controller according to any one of the first to third aspects, wherein the test means has a mode in which the first control means is evaluated. A test pin used when the output means executes a mode in which the first control means is evaluated also serves as a test pin used when executing another mode.
[0017]
According to the fourth aspect of the present invention, the test pin used at the time of evaluation of the first control means is also used at the time of executing another mode.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of a high-speed serial controller according to the present invention will be described in detail with reference to the accompanying drawings. In the following description, the number of serial bus interfaces is assumed to be 2, but the present invention is not limited to this.
[0019]
FIG. 1 is a block diagram showing an example of a configuration of a high-speed serial controller according to the present invention. As shown in FIG. 1, the high-speed serial controller 1 has a built-in test circuit 2 functioning as a test unit. Further, the high-speed serial controller 1 includes a first PHY circuit 3 functioning as a first control means, a first LINC circuit 4 functioning as a second control means, an arbiter circuit 5, a DMA (direct memory access) circuit 6 , A second LINC circuit 7 functioning as a second control means, and a second PHY circuit 8 functioning as a first control means.
[0020]
The first PHY circuit 3 is connected via a first serial bus interface 9 to a wiring (not shown). The first PHY circuit 3 and the first LINC circuit 4 are connected via a first internal bus 11. The first LINC circuit 4 and the arbiter circuit 5 are connected via a second internal bus 12.
[0021]
The arbiter circuit 5 and the DMA circuit 6 are connected via a third internal bus 13. The DMA circuit 6 and the second LINC circuit 7 are connected via a fourth internal bus 14. The second LINC circuit 7 and the second PHY circuit 8 are connected via a fifth internal bus 15. The second PHY circuit 8 is connected to a wiring (not shown) via the second serial bus interface 10.
[0022]
The test circuit 2 is connected to an external bus (not shown) via a serial test interface 25 functioning as an output unit. Inside the high-speed serial controller 1, the test circuit 2 is connected to the interface between the first PHY circuit 3 and the first LINC circuit 4, that is, the first internal bus 11 via the sixth internal bus 26. are doing. Further, the test circuit 2 is connected to an interface between the second PHY circuit 8 and the second LINC circuit 7, that is, to the fifth internal bus 15 via the seventh internal bus 27.
[0023]
Further, the test circuit 2 supplies a mode switching signal to the first PHY circuit 3 and the first LINC circuit 4 via the first signal line 28. The same applies to the second PHY circuit 8 and the second LINC circuit 7, and the test circuit 2 supplies a mode switching signal via the second signal line 29.
[0024]
The test circuit 2 includes an interface selection circuit 20, a data generation circuit 21 functioning as data generation means, a data transfer circuit 22 functioning as data transfer means, a monitor circuit 23, and a test pin selection circuit 24 functioning as a test pin selection circuit. Have. The interface selection circuit 20 includes an interface section (first internal bus 11) between the first PHY circuit 3 and the first LINC circuit 4, and an interface section between the second PHY circuit 8 and the second LINC circuit 7. (Fifth internal bus 15) is selected to be evaluated. The data generation circuit 21 automatically generates parallel data according to the test mode.
[0025]
The data transfer circuit 22 transfers the parallel data generated by the data generation circuit 21 to the LINC circuits 4 and 7 selected by the interface selection circuit 20. The monitor circuit 23 is a circuit for monitoring data. The test pin selection circuit 24 is a circuit that selects a test pin of the serial test interface 25 according to which bit data of which parallel data is monitored.
[0026]
Next, the operation of the high-speed serial controller 1 and the flow of data will be described. At the time of data transmission, the DMA circuit 6 is activated, and the second LINC circuit 7 requests required data to the arbiter circuit 5 via the DMA circuit 6. The arbiter circuit 5 performs arbitration and requests data from the first LINC circuit 4.
[0027]
As a result, data is read from an external storage device (not shown) via the first PHY circuit 3, the first serial bus interface 9, and a wiring (not shown) connected to the first serial bus interface 9. The read data is transferred to the first PHY circuit 3 via a wiring (not shown) and the first serial bus interface 9.
[0028]
In the first PHY circuit 3, an analog signal is converted into a digital signal. The data converted into the digital signal is transferred to the arbiter circuit 5 via the first LINC circuit 4. The arbiter circuit 5 transfers the received data to the DMA circuit 6, and the DMA circuit 6 transfers the data to the second LINC circuit 7.
[0029]
The second LINC circuit 7 converts the received data into a prescribed format by adding information data necessary for packet transfer, and sends the data to the second PHY circuit 8. The second PHY circuit 8 converts the received data into an analog signal, and outputs the analog signal to a wiring (not shown) via the second serial bus interface 10.
[0030]
When receiving data, the second PHY circuit 8 receives an analog signal from a wiring (not shown) via the second serial bus interface 10, converts the analog signal into a digital signal, and outputs the digital signal to the second LINC circuit 7. . The second LINC circuit 7 receives the packet data from the second PHY circuit 8, and checks the additional information data of the packet. Then, the second LINC circuit 7 requests the DMA circuit 6 to output data obtained by removing the additional information data from the packet data.
[0031]
The DMA circuit 6 requests the arbiter circuit 5 to output data, and outputs data to the arbiter circuit 5 when the arbiter circuit 5 arbitrates and permits the arbitration. The arbiter circuit 5 receives the data and requests the first LINC circuit 4 to output data.
[0032]
Thereby, the data is transferred to the first PHY circuit 3. Then, data is written to an external storage device (not shown) via the first PHY circuit 3, the first serial bus interface 9, and a wiring (not shown) connected to the first serial bus interface 9.
[0033]
At this time, the test mode is determined in the test circuit 2 by the setting from the serial test interface 25. The determined mode is notified to the first PHY circuit 3, the first LINC circuit 4, the second LINC circuit 7, and the second PHY circuit 8 by a mode switching signal.
[0034]
Next, a mode in which only the monitor operation is performed will be described. In this mode, an interface section (first internal bus 11) between the first PHY circuit 3 and the first LINC circuit 4 and a second PHY circuit 8 and a second LINC circuit 7 are controlled by the interface selection circuit 20. It is determined which interface unit (fifth internal bus 15) to select.
[0035]
When the target interface section is determined by this selection, the parallel data flowing through the interface section between the selected LINC circuits 4 and 7 and the PHY circuits 3 and 8 can be monitored by the test pins of the serial test interface 25. Become. As a result, the exchange of data during high-speed serial transfer can be observed at the data rate at the interface between the LINC circuits 4, 7 and the PHY circuits 3, 8.
[0036]
There is also a mode in which data transfer is performed between the first LINC circuit 4 and the second LINC circuit 7 without performing high-speed serial transfer. In this mode, the data transfer circuit 22 transfers the parallel data automatically generated by the data generation circuit 21 to the LINC circuits 4 and 7 selected by the interface selection circuit 20.
[0037]
The outputs of the LINC circuits 4 and 7 not selected at this time are output to the serial bus interfaces 9 and 10 via the corresponding PHY circuits 3 and 8. The data flowing from the unselected LINC circuits 4, 7 to the corresponding PHY circuits 3, 8 can be monitored by the test pins of the serial test interface 25.
[0038]
In addition, there is a mode in which both the first LINC circuit 4 and the second LINC circuit 7 are monitored. In this mode, by switching the test pins of the serial test interface 25 according to the register setting of the test pin selection circuit 24, the parallel data of the first LINC circuit 4 and the parallel data of the second LINC circuit 7 are simultaneously observed. Becomes possible. In general, the occurrence of a defect also occurs during a single operation, but often occurs during a combination operation. In this mode, analysis and debugging of a problem that can occur only during the combination operation can be efficiently performed.
[0039]
In addition, there is a mode of a function in which the data transfer circuit 22 simultaneously transfers the same data when there are a plurality of serial bus interfaces 9 and 10 to be DMA-transferred. In this mode, data is simultaneously transferred to the LINC circuits 4 and 7 to which data is transferred by the same DMA circuit 6, and the parallel data of the first LINC circuit 4 via the arbiter circuit 5 is monitored. In this mode, a more complicated combination state can be easily reproduced, which is useful for analyzing a complicated combination operation, and the verification efficiency at the time of circuit design is improved.
[0040]
In addition, there is a mode for performing a test unique to the PHY circuits 3 and 8. In the serial test interface 25 of the present embodiment, the test pins used in this mode are shared with the test pins used in each mode described above. Generally, since the PHY circuits 3 and 8 are analog circuits, a test mode different from the above-described normal test and a test pin are required.
[0041]
If there is no problem in terms of cost, test pins used for tests specific to the PHY circuits 3 and 8 may be provided exclusively. However, in a situation where the PHY circuits 3 and 8 and the LINC circuits 4 and 7 are incorporated in one chip to reduce the cost, an increase in cost due to the addition of test pins becomes a problem. In such a case, sharing the test pins is effective because the number of test pins that are not required for the actual system can be reduced as much as possible.
[0042]
According to the above-described embodiment, since parallel data flowing through the interface between the PHY circuits 3 and 8 and the LINC circuits 4 and 7 can be directly observed by the serial test interface 25, a new expensive measuring instrument is prepared. Even without doing so, it is possible to debug a circuit portion that does not depend on the PHY circuits 3 and 8 in the existing environment. In addition, it is possible to identify a defect with the PHY circuits 3 and 8.
[0043]
In the above, the present invention is not limited to the above-described embodiment, but can be variously modified. For example, the number of serial bus interfaces may be three or more.
[0044]
【The invention's effect】
As described above, according to the first aspect of the present invention, since the parallel data flowing through the interface between the first control means and the second control means is output from the output means, a new expensive measurement is performed. Even if a device is not prepared, it is possible to obtain a high-speed serial controller capable of debugging a circuit portion which does not depend on the first control means constituted by an analog circuit without changing the existing environment. In addition, an effect is obtained that a fault with the first control means can be isolated.
[0045]
According to the second aspect of the present invention, in the first aspect of the present invention, the data flowing through the respective interface units is transmitted to a plurality of combinations of the first control means and the second control means. Since the observation can be performed at the same time, there is an effect that it is useful for analysis debugging when there is a problem that can occur only during the combination operation.
[0046]
According to the invention described in claim 3, in the invention described in claim 1 or 2, the test data is provided for each of a plurality of combinations of the first control means and the second control means. By being transferred to the interface unit, a more complicated combination state can be easily reproduced, which is useful for analyzing a complicated combination operation, and has an effect of improving the verification efficiency at the time of circuit design.
[0047]
According to the invention described in claim 4, in the invention described in any one of claims 1 to 3, the test pin used at the time of evaluation of the first control means is used when the other mode is executed. Is also used, the number of test pins that are not required for the actual system can be reduced as much as possible, so that the effect of suppressing an increase in cost can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of a configuration of a high-speed serial controller according to the present invention.
[Explanation of symbols]
1 High-speed serial controller 2 Test means (test circuit)
3,8 First control means (PHY circuit)
4,7 Second control means (LINC circuit)
21 Data generation means (data generation circuit)
22 Data transfer means (data transfer circuit)
24 Switching means (test pin selection circuit)
25 Output means (serial test interface)

Claims (4)

First control means provided in the physical layer and converting an analog signal flowing through the wiring into a digital signal;
A second control unit provided in a data link layer adjacent to the physical layer and configured to convert data converted into a digital signal by the first control unit into data of a prescribed format;
Test means connected to an interface between the first control means and the second control means;
Output means for outputting parallel data flowing through the interface unit,
A high-speed serial controller comprising: The test means, during evaluation, outputs an output to the output means from an output of an interface unit of a first combination of the first control means and the second control means, 2. The high-speed serial controller according to claim 1, further comprising a switching unit configured to switch to an output of an interface unit in a second combination with the second control unit. 3. The test means includes: data generation means for generating parallel data;
The data generated by the data generation unit is transmitted to an interface unit of a first combination of the first control unit and the second control unit, and the first control unit and the second control unit. Data transfer means for transferring to the interface unit of the second combination;
The high-speed serial controller according to claim 1, further comprising: The test means has a mode in which the first control means is evaluated, and a test pin of the output means used when executing the mode in which the first control means is evaluated includes a mode in another mode. 4. The high-speed serial controller according to claim 1, wherein the high-speed serial controller also serves as a test pin used at the time of execution.

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