JP4736135B2 - Internal bus analysis system for inter-card communication, method and program - Google Patents

Description

  The present invention relates to an analysis system for buses between boards in a computer system or in a board, and more particularly to a bus analysis system capable of analyzing a plurality of serial buses or parallel buses.

  In recent years, the performance required for information processing apparatuses has increased dramatically. For example, in a computer system, as the CPU performance grows rapidly, there is a fact that the amount of computation to be processed has increased dramatically.

  As an example of a computer system, there is one in which one or a plurality of CPU cards and I / O (Input / Output) cards are mounted in a housing called a shelf for cooperative processing.

  The CPU card and I / O card are connected via an internal parallel bus mounted on the housing.

  Conventionally, PCI, which is a shared bus, has been widely used as an internal parallel bus, but the bandwidth of the internal parallel bus has become insufficient with rapid growth of CPU performance, and now PCI-Express, which is a high-speed bus, has become widespread. It's getting on.

  PCI-Express is a serial interface standard established with the aim of speeding up the PCI bus, which is a parallel bus conventionally used in personal computers and the like.

  Specifically, it is a large-capacity and high-speed bus standard that realizes a maximum transmission bandwidth of 160 Gbps by bundling up to 2.5 GHz per lane and a maximum of 64 lanes. Such a parallel bus (PCI-Express is a serial bus, but it is a multi-lane, so it becomes a substantially parallel signal. Therefore, in the following, in the case of simply a parallel bus, a bus that becomes a substantially parallel signal such as PCI-Express) Bus analyzers and exercisers are widely used as tools for verifying the operation of

  Here, the configuration of a conventional verification method for data flowing through the internal parallel bus will be described in detail with reference to FIGS. 1, 2, and 3. FIG.

  FIG. 1 is a schematic diagram showing how the bus analyzer device 13 performs an internal parallel bus analysis between a CPU card 11 and an I / O card 12 in a computer system as an example.

  The CPU card 11 and the I / O card 12 are electrically connected via a backplane (not shown), and transmit / receive data on the internal parallel bus.

  When measuring the bus using the bus analyzer device 13, the probe 14 is applied exclusively to the internal parallel bus, the electric signal is branched, the data is taken into the bus analyzer device 13 side, and the bus data is analyzed.

  Such an analysis is a widely used technique for measuring whether a bus is operating normally between cards.

  However, when the configuration shown in FIG. 1 is adopted, it is necessary to insert the probe on the data line to be analyzed as described above to branch the electric signal. However, if the intrusion current flows to the probe side, the internal parallel bus May cause deterioration of the data waveform, affecting the observed data line. Therefore, a strict design is required to prevent intrusion current so that the data waveform does not deteriorate.

  FIG. 2 is a schematic diagram showing how the exerciser 21 performs bus data analysis of the CPU card 11 and the I / O card 12.

  The exerciser 21 has a built-in function for terminating the bus and connects the CPU card 11 or the I / O card 12 and the exerciser 21 on a one-to-one basis.

  Then, arbitrary test data is transmitted from the exerciser 21 to the CPU card 11 or the I / O card 12, and the response is analyzed.

  Such an analysis is a widely used technique for measuring whether the internal parallel bus of a single card is operating normally.

  However, when the configuration shown in FIG. 2 is adopted, a one-to-one connection between the CPU card and the exerciser or the I / O card and the exerciser is required, and the actual operation is performed (for example, the CPU card and the I / O card are connected). Individual responses to any test data cannot be measured when connected to the shelf via the backplane.

  As a method for solving the above problem, there is a method of converting an internal parallel bus (PCI bus) into an IEEE 1394 signal and connecting it to an external measuring instrument (see, for example, Patent Document 1).

  According to Patent Document 1, a measuring instrument is connected to an internal parallel bus via a signal of the IEEE 1394 standard without directly applying a probe to the internal parallel bus and maintaining a connection between the CPU card and the I / O card. It is possible.

  On the other hand, FIG. 3 is a schematic diagram showing a state in which data flowing through the internal parallel bus is measured by the bus analyzer device 13 placed remotely.

  First, the configuration will be described. The CPU card 11 and one or a plurality of I / O cards 12 are mounted on a shelf 31 and are connected by an internal parallel bus 32 via a backplane (not shown).

  The CPU card 11 generally includes a CPU and internal storage memory (FIG. 3, memory), a north bridge (FIG. 3, north bridge) that bridges a high-speed bus between the CPU and internal storage memory, and a low speed between the CPU and I / O. A south bridge (FIG. 3, south bridge) that bridges the bus and an I / O interface (FIG. 3, I / O section) are provided.

  Next, the operation of the remote measurement of the internal parallel bus will be described. First, the data of the internal parallel bus is taken into the internal storage memory at a predetermined timing.

  Here, the data fetching timing is generally determined by a method in which a CPU is set by determining a time to be measured in advance, or a method in which a CPU interrupt is triggered when an error occurs.

  Next, the data stored in the internal storage memory is transmitted to the remote bus analyzer 13 via the I / O interface and further via the external communication path 33 such as Ethernet (Ethernet (registered trademark)), where the data is analyzed. (For example, refer to Patent Document 2).

The bus analyzer 13 and exerciser 21 shown in FIGS. 1 to 3 generally include a specific internal parallel bus analysis engine such as PCI-Express and specialize in the bus analysis.
JP 2004-110389 A JP 59-174927 A

  In the above bus analysis system required for debugging during system development, the internal parallel bus (PCI bus) is converted into an IEEE1394 signal in order to measure data between a plurality of CPU cards and I / O cards. The conventional technology that is configured to connect to an external measuring instrument has the following problems.

  First, the first problem is that it is difficult to realize with a simple circuit configuration.

  The reason is that the internal parallel bus is a parallel signal of 32 bits or 64 bits, for example, and a switch or selector for switching the measurement target CPU card and I / O card must be installed for each parallel signal line. This is because the scale of switches and selectors increases dramatically according to the number.

  The second problem is that the internal parallel bus to be measured cannot support a high-speed bus standard such as PCI-Express.

  This is because the IEEE 1394 standard defines a maximum transmission band of 1.6 Gbps and cannot support the PCI-Express band of 2.5 Gbps.

  In addition, there are some problems even when the configuration shown in FIG.

  First, the internal parallel bus cannot be measured remotely at an arbitrary timing. This is because in the case of remote observation, the data of the internal parallel bus is temporarily stored in a memory in the CPU card or the like on the measurement target side, and external communication such as Ethernet is used via the I / O portion on the CPU card. Send to measuring instrument.

  The memory is stored in such a manner that the time to be measured is determined in advance and the writing time to the memory is set by the CPU, or the memory is written when some error occurs. In other words, the measurement can be performed only at a predetermined timing.

  The next problem is that the internal parallel bus cannot be measured from a certain distance. The reason is IEEE 1394. This is because the maximum distance that can be transmitted even when optical transmission is used in the b standard is 500 m, and transmission exceeding that distance is impossible.

  A further problem is that in a bus analysis system required for debugging at the time of system development, when analyzing an internal parallel bus from a remote location, a response to arbitrary test data cannot be analyzed. This is because the exerciser cannot be connected via external communication such as Ethernet.

  Therefore, the present invention is a bus analysis system required for debugging at the time of system development, etc., while preventing electrical troubles associated with probing at the time of measurement, at the same time, the bus analyzer function and exerciser function can be compatible at low cost. An object of the present invention is to provide a possible internal bus analysis system for inter-card communication, its method and its program.

  According to the present invention, there is provided a bus analysis system for analyzing an internal bus for inter-card communication, comprising a computer on which one or a plurality of cards are mounted and a bus analysis device connected to the computer. The bus analyzer converts a data transmitted from the card to the internal bus into an Ethernet protocol, a means for copying the data converted by the first protocol converter, A bus analyzing means for analyzing an internal bus based on the replicated data; a second protocol converting means for converting the data converted by the first protocol converting means into a protocol corresponding to the bus; Connection state holding means for holding a bus connection between the cards using the data converted by the second protocol conversion means; Bus analysis system, characterized in that it comprises is provided.

  In the above bus analysis system, the bus analysis system comprises a computer on which one or more cards are mounted and a bus analysis device connected to the computer, and analyzes an internal bus for inter-card communication. The card again converts the data transmitted from the card to the internal bus into an Ethernet protocol, and converts the data converted by the first protocol conversion unit into a protocol corresponding to the bus again. Second protocol conversion means for performing conversion, wherein the bus analysis device replicates the data converted by the first protocol conversion means, and analyzes the internal bus based on the replicated data Between the cards using the data converted by the bus analyzing means and the second protocol converting means A connection state holding means for holding the scan connection may be a bus analysis system, characterized in that it comprises a.

  In a bus analysis system required for debugging at the time of system development, even when there are a plurality of measurement targets, a switch or selector for switching between the measurement target CPU card and the I / O card is not required.

[Embodiment 1]
Next, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is a block diagram showing the bus analysis system of the present invention.

  The bus analysis system according to the present invention includes one or a plurality of CPU cards 11, one or a plurality of I / O cards 12, a bus analyzer unit 43, a CPU card 11 or an I / O card 12, and a backplane connector (see FIG. (Not shown), and an internal parallel bus unit 44 is provided.

  Further, the bus analyzer unit 43 includes one or more external I / F units 45 (here, an electrical interface used in the internal parallel bus, such as LVDS (Low Voltage), which are connected to the CPU card 11 and the I / O card 12. One or a plurality of bridge units 46 connected to the external I / F unit 45, such as differential signaling and CML (Common Mode Logic). An Ethernet switch unit 47 connected to the bridge unit 46, an Ethernet transmission line unit 48, and an analyzer unit 49 connected to the Ethernet switch unit 47.

  Here, the analyzer unit 49 can rewrite the bus analyzer function in accordance with the internal parallel bus to be analyzed by mounting the bus analyzer function as a macro on a device such as software or field programmable gate array (FPGA). Is possible.

  Next, the structure of the bridge part 46 is demonstrated with reference to drawings. FIG. 5 is a diagram illustrating components of the bridge unit 46.

  The bridge unit 46 is connected to the external I / F unit 45 to perform an internal parallel bus physical format process, and is connected to the internal parallel bus I / F unit 51 to process the internal parallel bus data. An internal parallel bus termination unit 52, a protocol conversion unit 53 that is connected to the internal parallel bus termination unit 52 and converts to an Ethernet protocol, and an Ethernet I / F unit 54 that is connected to the protocol conversion unit 53 and generates a physical layer packet of the Ethernet protocol And an address management table 55 for converting a transfer address in the internal parallel bus to a transfer address in the Ethernet protocol.

  Here, the bridge unit 46 can be rewritten in accordance with the internal parallel bus to be analyzed by configuring it with a rewritable device such as an FPGA.

  Next, the packet format of the Ethernet protocol will be described with reference to the drawings. FIG. 6 shows the packet format of the Ethernet protocol.

  The packet is written with a pattern (preamble) for synchronization at the head, followed by header information in which the destination address / source address, packet type / length, etc. are written. Further, data of the internal parallel bus is included in the data area next to the header information.

  An error check packet (FCS (Frame Check Sequence)) is added to the end of the packet to check whether the packet is garbled during transfer.

  As the standard used for the internal parallel bus described above, for example, PCI, PCI-Express, and the like can be considered. However, the present invention is not limited to the exemplified standard, and any standard can be selected.

  Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.

  The data of the internal parallel bus output from the CPU card 11 is input to the external I / F unit 45 of the bus analyzer device unit 43 through the internal parallel bus unit 44, and electrical termination processing is performed.

  Next, in the bus analyzer unit 43, the input internal parallel bus data is transferred from the external I / F unit 45 to the bridge unit 46, and is internally transmitted by the internal parallel bus I / F unit 51 in the bridge unit 46. After the physical formatting of the parallel bus, the internal parallel bus termination unit 52 performs termination processing of the internal parallel bus data.

  The data subjected to termination processing is transferred to the protocol conversion unit 53 and converted to the Ethernet protocol.

  Next, protocol conversion work will be described in detail.

  The data of the internal parallel bus transferred to the protocol conversion unit 53 is subjected to header analysis including the destination / source address of the internal parallel bus.

  By referring to the address management table unit 55 in which the correspondence between the address of the internal parallel bus and the address of the Ethernet protocol is held, the destination / source address information of the Ethernet protocol is acquired.

  Next, the data of the internal parallel bus is stored in the data area of the Ethernet protocol, and is transferred to the Ethernet I / F unit 54 with the preamble, header information (destination, source address, etc.) and FCS described above. .

  The Ethernet I / F unit 54 generates a physical layer packet of the Ethernet protocol and outputs it from the bridge unit 46.

  An Ethernet protocol packet output from the bridge unit 46 is transferred to the Ethernet switch unit 47 via the Ethernet transmission path unit 48.

  Next, the header information is referred to and transferred to the bridge unit 46 on the side to which the desired I / O card 12 is connected.

  The packet of the Ethernet protocol is converted from the Ethernet protocol into the internal parallel bus data in the reverse operation in the bridge unit 46, and desired based on the header information via the external I / F unit 45 and the internal parallel bus unit 44. To the I / O card 12.

  As described above, tunneling by Ethernet is performed in the middle, but the connection between the CPU card 11 and the I / O card 12 is maintained by the connection through the internal parallel bus.

  Next, a packet analysis method between the CPU card 11 and the I / O card 12 will be described.

  As described in the description of the protocol conversion work, the data on the internal parallel bus between the CPU card 11 and the I / O card 12 is converted into the Ethernet protocol and input to the Ethernet switch unit 47.

  Here, the packet to be measured is electrically copied by the Ethernet switch unit 47 and transferred to the bridge unit 46 and the analyzer unit 49. The analyzer unit 49 performs data analysis after termination of the Ethernet protocol and the internal parallel bus.

  By using this configuration, while maintaining the connection on the internal parallel bus between the CPU card 11 and the I / O card 12, the data of the internal parallel bus to be measured is stored in the Ethernet protocol data area. The switch unit 47 can branch to the analyzer unit 49 side.

  Therefore, it is not necessary to perform a strict current non-intrusive design as compared with the electric branching by the conventional probe.

  Furthermore, it is possible to prevent waveform deterioration of data flowing through the bus due to current intrusion into the bus analyzer side in a measurement method using a conventional bus analyzer. In addition, a plurality of internal parallel bus units 44 can be selectively measured by simply switching the switching path of the Ethernet switch unit 47.

  In addition, an additional switch and selector for selecting the internal parallel bus unit 44, which are essential in the configuration of the prior art, are not required. Furthermore, by rewriting the bridge unit 46 and the analyzer unit 49, path analysis for any internal parallel bus becomes possible.

  From the above, it is possible to perform a plurality of bus analyzes with one bus analyzer.

[Embodiment 2]
Next, the configuration of the embodiment of the present invention will be described in detail with reference to the drawings. FIG. 7 is a block diagram showing the second embodiment.

  The basic configuration of the second embodiment is the same as that of the first embodiment, but only the configuration of the bus analyzer device unit 43 is different from that of the first embodiment.

  Therefore, only the bus analyzer unit 43 which is a difference will be described.

  As in the first embodiment, the bus analyzer unit 43 is connected to the CPU card 11 and one or a plurality of external I / F units 45 and external I / F units 45 connected to the I / O card 12. It is the same as the first embodiment in that it includes one or a plurality of bridge units 46, an Ethernet switch unit 47 connected to the bridge unit 46, an Ethernet transmission path unit 48, and an analyzer unit 49 connected to the Ethernet switch unit 47. is there.

  The second embodiment further includes an emulation unit 71 that generates test data corresponding to the internal parallel bus, converts the test data into an Ethernet protocol, and transfers the test data to the Ethernet switch unit 47.

  The emulation unit 71 includes a test data generation unit 81, a protocol conversion unit 53, a second Ethernet I / F unit 82, and an address management table 55.

  Next, the operation of the second exemplary embodiment of the present invention will be described in detail with reference to FIGS. Since the connection with the internal parallel bus between the CPU card 11 and the I / O card 12 is the same as in the first embodiment, it is omitted in this description, and only the operation of the emulation unit 71 that is different from the first embodiment is described. explain.

  FIG. 8 is a configuration diagram showing the emulation unit 71.

  First, the test data generation unit 81 attaches an address in the internal parallel bus of the CPU card 11 or the I / O card 12 and the bus analyzer device unit 43 to which the test data is to be transmitted, and provides the test data (internal parallel bus format). It is generated and transferred to the protocol converter 53.

  Here, protocol conversion is the same as that in the first embodiment, and is therefore omitted. The packet converted into the Ethernet protocol is configured into a physical layer packet of the Ethernet protocol by the second Ethernet I / F unit 82.

  Thereafter, the data is transferred to the Ethernet switch unit 47 and transferred to the bridge unit 46 on the side to which the desired CPU card 11 or I / O card 12 is connected based on the header information.

  Next, the packet of the Ethernet protocol is converted from the Ethernet protocol to the data of the internal parallel bus unit 44 in the bridge unit 46, and the desired CPU card 11 or I / F is transmitted via the external I / F unit 45 and the internal parallel bus bus unit 44. It is transferred to the O card 12.

  Since the operation of the emulation unit 71 is performed in a state in which the connection between the CPU card 11 and the I / O card 12 is maintained, the normal data transfer between the CPU card 11 and the I / O card 12 is interrupted.

  However, a configuration in which packets are stored in a buffer (not shown) of the Ethernet switch unit 47 during data transmission between the CPU card 11 and the I / O card 12 allows the CPU card 11 and the I / O card 12 to communicate with each other. Data transmission can be prevented from being hindered.

  Next, the CPU card 11 or the I / O card 12 that has received the test data transmits a response to the test data to the internal parallel bus unit 44.

  Thus, the response can be analyzed by the analyzer unit 49 of the bus analyzer device unit 43 by the same operation as that of the first embodiment.

  By using the second configuration shown above, the CPU card 11 and the I / O card 12 can be tested for arbitrary test data while maintaining the connection on the internal parallel bus between the CPU card 11 and the I / O card 12. Is possible.

[Embodiment 3]
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. FIG. 9 is a block diagram showing the third embodiment.

  The multibus analysis system according to the present invention includes one or a plurality of CPU cards 11, one or a plurality of I / O cards 123 PU card 11 and a bridge unit 46 mounted on the I / O card 12, the CPU card 11 or I The Ethernet transmission path unit 48, the Ethernet switch unit 47, the Ethernet work unit 91, and the bus analyzer device unit 43 that are drawn out from the / O card 12 through a backplane connector (not shown).

  The bus analyzer unit 43 includes a CPU card 11, one or a plurality of external I / F units 45 connected to the I / O card 12, and an analyzer unit 49 connected to the external I / F unit 45.

  Next, the operation of the third exemplary embodiment of the present invention will be described in detail with reference to FIG.

  The internal parallel bus in the CPU card 11 or the I / O card 12 is immediately converted into the Ethernet protocol by the bridge unit 46 similarly mounted in the CPU card 11 or the I / O card 12.

  Here, the protocol conversion operation is the same as that in the first embodiment, and is therefore omitted.

  Next, the converted packet is transferred to the Ethernet switch unit 47 via the Ethernet transmission path unit 48, and transferred to the desired I / O card 12 with reference to the header information.

  The packet of the Ethernet protocol transferred to the I / O card 12 is converted from the Ethernet protocol to the protocol of the internal parallel bus unit in the bridge unit 46.

  As in the above-described embodiments, tunneling by Ethernet is performed on the way, but the connection between the CPU card 11 and the I / O card 12 is maintained by the internal parallel bus.

  Next, a remote data analysis method between the CPU card 11 and the I / O card 12 will be described. Data on the internal parallel bus between the CPU card 11 and the I / O card 12 is converted into an Ethernet protocol and input to the Ethernet switch unit 47.

  Here, the data to be measured is electrically copied by the Ethernet switch unit 93 and transferred to the remote bus analyzer device unit 43 via the Ethernet work unit 91.

  Next, the Ethernet protocol packet is transferred to the analyzer unit 49 via the external I / F unit 45 in the bus analyzer unit 43, and then data analysis is performed.

  Here, since the operation of the analyzer unit 49 is the same as that of the first embodiment, the description thereof is omitted.

  By using the third configuration shown above, it is possible to remotely measure the internal parallel bus while maintaining the connection on the internal parallel bus between the CPU card 11 and the I / O card 12.

  Furthermore, it is possible to measure the internal parallel bus between any CPU card 11 and I / O card 12 at any timing by simply switching the Ethernet switch unit 47.

[Embodiment 4]
Next, the structure of the 4th Embodiment of this invention is demonstrated in detail with reference to drawings. FIG. 10 is a block diagram showing the fourth embodiment.

  In the fourth embodiment, since only the configuration of the bus analyzer device unit 43 is different from that of the third embodiment, only the bus analyzer device unit 43 will be described. As in the third embodiment, the bus analyzer unit 43 is connected to the CPU card 11 and one or a plurality of external I / F units 45 connected to the I / O card 12, and the second connected to the external I / F unit 45. An Ethernet switch unit 100, an analyzer unit 49 connected to the second switch unit 100, and an emulation unit 71 that generates test data of the internal parallel bus, converts it to a serial protocol, and transfers it to the second switch unit 100 Prepare.

  Here, the configuration of the emulation unit 71 has a configuration as shown in FIG. 8 as in the second embodiment.

  Next, the operation of the fourth exemplary embodiment of the present invention will be described in detail with reference to FIG. Since the connection using the internal parallel bus between the CPU card 11 and the I / O card 12 is the same as that in the third embodiment, it is omitted in this description, and only the operation of the emulation unit 71 that is different from the third embodiment is described. To do.

  As in the second embodiment, the internal parallel bus test data converted to the Ethernet protocol in the emulation unit 71 is transferred to the second Ethernet switch unit 100, and based on the header information, the desired CPU card 11 or I / O The data is transferred to the external I / F unit 45 on the side to which the O card 12 is connected.

  The test data output from the bus analyzer unit 43 is transferred to the Ethernet switch unit 47 via the Ethernet work unit 91 and transferred to the desired CPU card 11 or I / O card 12 based on the header information.

  The CPU card 11 or the I / O card 12 that has received the test data performs processing by converting the Ethernet protocol into the protocol of the internal parallel bus unit 44 in the bridge unit 46.

  Next, the CPU card 11 or the I / O card 12 generates the response, converts it to the Ethernet protocol via the internal parallel bus unit 44, converts it to the Ethernet protocol, and then sends it to the Ethernet work unit 91 via the switch unit 47. Send.

  Further, the bus analyzer device unit 43 receives the response packet transferred via the Ethernet work unit 91 and analyzes it in the same manner as described in the third embodiment.

  By using this configuration described above, it is possible to analyze the response to the test data from the remote to the CPU card 11 or the I / O card 12 at an arbitrary timing.

[Embodiment 5]
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 11 is a block diagram showing a PCI-Express bus analysis system of the present invention.

  The PCI-Express bus analysis system according to the present invention is backed up from one or more CPU cards 11, one or more I / O cards 12, PCI-Express analyzer system 113, CPU card 11 or I / O card 12. A PCI-Express bus unit 112 is provided to extract data to the outside through a plain connector (not shown).

  The PCI-Express analyzer system 111 includes a CPU card 11, one or more external I / F units 45 connected to the I / O card 12, and one or more bridges connected to the external I / F unit 45. Unit (hereinafter referred to as PEB (PCI-Express Ethernet Bridge)) 113, Ethernet switch unit 47 connected to PEB unit 113, Ethernet transmission path unit 48, and PCI-Express analyzer unit 114 connected to Ethernet switch unit 47. .

  The PCI-Express protocol is configured with a serial bus configuration of 2.5 GHz per lane and a maximum of 64 lanes, and the electrical signal is LVDS (Low Voltage Differential Signaling) which is a low voltage differential signal suitable for high-speed transmission. Used.

  Next, the configuration of the PEB unit 113 will be described with reference to the drawings. FIG. 12 is a configuration diagram showing components of the PEB unit 113.

  The PEB unit 113 is connected to the external I / F unit 45 and is connected to the PCI-Express I / F unit 121 that terminates the physical layer packet of the PCI-Express bus unit 112, and the PCI-Express I / F unit 121. The physical layer packet of the Ethernet protocol connected to the PCI-Express protocol termination unit 122 that terminates the link layer of the Express protocol, the protocol conversion unit 123 that is connected to the PCI-Express protocol termination unit 122 and converts to the Ethernet protocol, and the protocol conversion unit 123 And an address management table unit 125 for converting a transfer address in the PCI-Express protocol into a transfer address in Ethernet.

  Next, PCI-Express protocol and Ethernet protocol packet formats will be described with reference to the drawings. FIG. 13 is a diagram showing a packet format of the PCI-Express protocol of the present invention.

  The PCI-Express protocol includes a physical layer that defines the standard of electric signals to be transmitted, a link layer that guarantees transmission between links, and a transaction layer that receives read / write requests from the software layer and transmits them to the link layer.

  Here, FIG. 13 shows the data format of the data link layer and transaction layer particularly related to the present invention. The transaction layer packet includes a header information part and data in which address information of a transfer destination is written.

  In the data link layer packet, a sequence number for guaranteeing the arrival order in link transmission and a CRC (Cyclic Redundancy Check) for error check are added to the transaction layer packet as components.

  FIG. 14 shows the Ethernet packet format of the present invention. The packet is preceded by a pattern (preamble) for synchronization, followed by header information in which the destination address / source address, packet type / length, etc. are written.

  Further, a PCI-Express transaction layer packet is included in the data area next to the header information. An error check packet FCS (Frame Check Sequence) or the like for checking whether the packet is garbled during transfer is added to the end of the packet.

  In the present embodiment, a configuration in which the internal parallel bus is a PCI-Express protocol is shown.

  In this regard, in the first to fourth embodiments, it is also possible to adopt a configuration in which the internal parallel bus is a PCI-Express protocol.

  Next, the operation of the fifth embodiment of the present invention will be described with reference to FIG. 11, FIG. 12, FIG. 13 and FIG.

  The PCI-Express protocol packet output from the CPU card 11 is input to the external I / F unit 45 of the PCI-Express analyzer unit 111 via the PCI-Express bus unit 112.

  In the PCI-Express analyzer unit 111, the input PCI-Express protocol packet is transferred from the external I / F 45 to the PEB unit 113.

  After that, the PCI-Express physical layer is terminated in the PCI-Express I / F unit 121 in the PEB unit 113, and then the termination process of the PCI-Express protocol link layer is performed in the PCI-Express protocol termination unit 122. .

  Here, the transaction layer packet subjected to the termination process is transferred to the protocol conversion unit 123 and converted into the Ethernet protocol.

  Next, protocol conversion work will be described in detail.

  The transaction layer packet of the PCI-Express protocol transferred to the protocol conversion unit 123 is analyzed for a header including the destination and source address of the PCI-Express protocol.

  By referring to the address management table section 125 in which the correspondence relationship between the address described in the transaction layer of the PCI-Express protocol and the address of the Ethernet protocol is held, the destination / source address information of the Ethernet protocol is acquired.

  Next, the transaction layer packet of the PCI-Express protocol is stored in the data area of the Ethernet protocol, and is transferred to the Ethernet I / F unit 124 with a preamble, header information (destination, source address, etc.) and FCS.

  The Ethernet I / F unit 124 generates a physical layer packet of the Ethernet protocol and outputs it to the outside of the PEB unit 113.

  The packet of the Ethernet protocol output from the PEB unit 113 is transferred to the Ethernet switch unit 47 via the Ethernet transmission path 48, and the PEB unit 113 on the side to which the desired I / O card 12 is connected with reference to the header information. Forwarded to

  In the PEB unit 113, the Ethernet protocol packet is converted from the Ethernet protocol to the PCI-Express protocol in the reverse operation to the above, and the desired I / O is transmitted via the external I / F unit 45 and the PCI-Express bus unit 112. It is transferred to the card 12.

  As in the above-described embodiments, tunneling is performed in the middle of the Ethernet protocol, but the connection between the CPU card 11 and the I / O card 12 is maintained using the PCI-Express protocol.

Next, a bus data analysis method between the CPU card 11 and the I / O card will be described.
PCI-Express protocol data between the CPU card 11 and the I / O card 12 is converted into an Ethernet protocol and input to the Ethernet switch unit 47.

  Here, the data to be measured is electrically copied by the Ethernet switch unit 114 and transferred to the PCI-Express analyzer unit 114.

  Finally, the PCI-Express analyzer unit 114 analyzes data after terminating the Ethernet protocol and the PCI-Express protocol.

  By using the fifth configuration shown above, the PCI-Express protocol data that is to be measured while maintaining the connection with the PCI-Express protocol between the CPU card 11 and the I / O card 12 is the data area of the Ethernet protocol. Can be branched to the PCI-Express analyzer unit 114 side by the Ethernet switch unit 47.

  Therefore, it is not necessary to have a strict current non-intrusive design as compared with the electric branching by the conventional probe.

  At the same time, it is possible to prevent waveform deterioration of data flowing through the bus due to current intrusion into the bus analyzer side in a measurement system using a conventional bus analyzer.

  Furthermore, without using a PCI-Express dedicated bus analyzer, the PEB unit 113, the Ethernet switch unit 47, and the software-based PCI-Express analyzer unit 114 are incorporated into the Ethernet packet generator, so that the PCI-Express can be realized at a low cost. Protocol analysis is possible.

  In addition, if the PEB unit 113 is mounted on the CPU card 11 and I / O card 12 side, a general-purpose Ethernet switch and a software-based Ethernet packet generator incorporating the PCI-Express analyzer unit 114 can be used to further reduce the cost. PCI-Express analysis is possible.

[Effect of the embodiment]
The first effect is that the Ethernet installed between the measurement objects (for example, the CPU card or the I / O card) even in the case where there are a plurality of measurement objects in the bus analysis system required for debugging at the time of system development. Since the internal parallel bus converted into the Ethernet protocol can be switched by the switch, a switch or selector for switching the CPU card or I / O card to be measured is unnecessary.

  The second effect is that, in a bus analysis system required for debugging during system development, the internal parallel bus is converted to an Ethernet protocol with a transmission bandwidth of up to 10 Gbps and connected to a measuring instrument. It is possible to cope with a high-speed bus such as PCI-Express.

  The third effect is that in a bus analysis system required for debugging during system development, a function as a bridge is mounted on the measurement target side (for example, a CPU card or an I / O card), so that the Ethernet work Since the data of the internal parallel bus can be extracted as an Ethernet protocol capable of remote communication, the internal parallel bus can be measured at an arbitrary timing from a remote location.

  The fourth effect is that, in a bus analysis system required for debugging during system development, the internal parallel bus is converted into an Ethernet protocol that can be transmitted remotely via Ethernet work and connected to a measuring instrument. Therefore, it is possible to perform remote observation without considering the transmission distance.

  The fifth effect is that the internal parallel bus converted to the Ethernet protocol that can be transmitted remotely by installing a function as a bridge on the measurement target side in the bus analysis system required for debugging etc. when developing the device. Since the test data can be inserted and the response can be branched via the Ethernet switch, it is possible to respond to any test data from a remote location.

It is a block diagram which shows the conventional Embodiment 1. It is a block diagram which shows the conventional Embodiment 2. It is a block diagram which shows the conventional Embodiment 3. It is a block diagram which shows the 1st Embodiment of this invention. It is a block diagram of the bridge part which shows the 1st Embodiment of this invention. It is a figure showing the packet format of the serial protocol used in the 1st Embodiment of this invention. It is a block diagram which shows the 2nd Embodiment of this invention. It is a block diagram of the emulation part used in the 2nd Embodiment of this invention. It is a block diagram which shows the 3rd Embodiment of this invention. It is a block diagram which shows the 4th Embodiment of invention. It is a block diagram which shows the 5th Embodiment of this invention. It is a block diagram of the bridge part (PEB) which shows the 5th Embodiment of this invention. It is a figure showing the packet format of the PCI-Express protocol used in the 5th Embodiment of this invention. It is a figure showing the packet format of the Ethernet protocol used in the 5th Embodiment of this invention.

Explanation of symbols

11 CPU card 12 I / O card 13 Bus analyzer device 14 Probe 21 Exerciser 31 Shelf 32 Internal parallel bus 33 External communication path 43 Bus analyzer device portion 44 Internal parallel bus portion 45 External I / F portion 46 of bus analyzer Bridge portion 47 Ethernet Switch unit 48 Ethernet transmission path unit 49 Analyzer unit 51 of bus analyzer device Internal parallel bus I / F unit 52 Internal parallel bus termination unit 53 Protocol conversion unit 54 Ethernet I / F unit 55 Address management table unit 71 Emulation unit 81 Emulation unit Test data generation unit 82 Second Ethernet I / F unit 91 in emulation unit Ethernet work unit 100 Second Ethernet switch unit 111 PCI-Express analyzer Bridge section of The System 112 PCI-Express bus unit 113 PCI-Express analyzer unit (PEB)
114 PCI-Express Analyzer Unit 121 PCI-Express I / F Unit 122 EB PCI-Express I / F Unit 122 PEB PCI-Express Protocol Termination Unit 123 PEB Protocol Conversion Unit 124 PEB Ethernet I / F Unit 125 PEB Address Management table section

Claims (15)

A computer with one or more cards,
A bus analyzer connected to the computer;
A bus analysis system for analyzing an internal bus for inter-card communication,
The bus analyzer is
First protocol conversion means for converting data transmitted from the card to the internal bus into data conforming to the Ethernet (registered trademark) protocol;
Means for replicating the data converted by the first protocol conversion means;
Bus analysis means for analyzing an internal bus based on the replicated data;
Second protocol conversion means for converting the data converted by the first protocol conversion means again into data conforming to the protocol corresponding to the bus;
Connection state holding means for holding a bus connection between the cards using the data converted by the second protocol conversion means;
A bus analysis system comprising: A computer with one or more cards,
A bus analyzer connected to the computer;
A bus analysis system for analyzing an internal bus for inter-card communication,
The card
First protocol conversion means for converting data transmitted from the card to the internal bus into data conforming to the Ethernet protocol;
Second protocol conversion means for converting the data converted by the first protocol conversion means again into data conforming to the protocol corresponding to the bus;
With
The bus analyzer is
Means for replicating the data converted by the first protocol conversion means;
Bus analysis means for analyzing an internal bus based on the replicated data;
Connection state holding means for holding a bus connection between cards using the data converted by the second protocol conversion means;
A bus analysis system comprising: The bus analysis system according to claim 1 or 2,
The bus analyzer is
Means for generating test patterns for bus analysis;
Means for converting the test pattern into an Ethernet protocol-compliant one;
Means for transmitting the converted test pattern to the card;
Further comprising
The bus analysis system performs the bus analysis based on response information from the card to the test pattern. A computer with one or more cards,
A first bus analyzer connected to the computer;
A second bus analysis device network-connected to the first bus analysis device;
A bus analysis system for analyzing an internal bus for inter-card communication,
The card
First protocol conversion means for converting data transmitted from the card to the internal bus into data conforming to the Ethernet protocol;
Second protocol conversion means for converting the data converted by the first protocol conversion means again into data conforming to the protocol corresponding to the bus;
With
The first bus analyzer is
Means for replicating the data converted by the first protocol conversion means;
Connection state holding means for holding a bus connection between cards using the data converted by the second protocol conversion means;
With
The second bus analyzer is
A bus analysis system comprising bus analysis means for analyzing an internal bus based on the replicated data. The bus analysis system according to claim 4,
The second bus analyzer is
Means for generating test patterns for bus analysis;
Means for converting the test pattern into an Ethernet protocol-compliant one;
Means for transmitting the converted test pattern to the card;
Further comprising
The bus analysis system performs the bus analysis based on response information from the card to the test pattern. The bus analysis system according to any one of claims 1 to 5,
A bus analysis system, wherein a bus which is a target of the first protocol conversion means can be selected from any bus. The bus analysis system according to any one of claims 1 to 6,
The bus analysis system characterized in that the bus to be analyzed conforms to the PCI-Express standard. A computer with one or more cards,
A bus analyzer connected to the computer;
A bus analysis method for analyzing an internal bus for inter-card communication,
The bus analyzer is
A first protocol conversion step of converting data transmitted from the card to the internal bus into data conforming to the Ethernet protocol;
Replicating the data converted by the first protocol conversion step;
A bus analysis step for analyzing an internal bus based on the replicated data;
A second protocol conversion step of converting the data converted by the first protocol conversion step again into data conforming to a protocol corresponding to the bus;
A connection state holding step for holding a bus connection between the cards using the data converted in the second protocol conversion step;
A bus analysis method comprising: A computer with one or more cards,
A bus analyzer connected to the computer;
A bus analysis method for analyzing an internal bus for inter-card communication,
The card
A first protocol conversion step for converting data transmitted from the card to the internal bus into data conforming to the Ethernet protocol;
A second protocol conversion step of converting the data converted by the first protocol conversion step again into data conforming to a protocol corresponding to the bus;
With
The bus analyzer is
Replicating the data converted by the first protocol conversion step;
A bus analysis step for analyzing an internal bus based on the replicated data;
A connection state holding step of holding a bus connection between the cards using the converted data in the second protocol conversion step;
A bus analysis method comprising: The bus analysis method according to claim 8 or 9, wherein
The bus analyzer is
Generating a test pattern for bus analysis;
Converting the test pattern into an Ethernet protocol-compliant one;
Transmitting the converted test pattern to a card;
Further comprising
The bus analysis method is characterized in that the bus analysis step is performed based on response information from a card to the test pattern. A computer with one or more cards,
A first bus analyzer connected to the computer;
A second bus analysis device network-connected to the first bus analysis device;
A bus analysis method for analyzing an internal bus for inter-card communication,
The card
A first protocol conversion step for converting data transmitted from the card to the internal bus into data conforming to the Ethernet protocol;
A second protocol conversion step of converting the data converted by the first protocol conversion step again into data conforming to a protocol corresponding to the bus;
With
The first bus analyzer is
Replicating the data converted by the first protocol conversion step;
A connection state holding step of holding a bus connection between the cards using the converted data in the second protocol conversion step;
With
The second bus analyzer is
A bus analysis method comprising a bus analysis step of analyzing an internal bus based on the replicated data. The bus analysis method according to claim 11,
The second bus analyzer is
Generating a test pattern for bus analysis;
Converting the test pattern into an Ethernet protocol-compliant one;
Transmitting the converted test pattern to a card;
Further comprising
The bus analysis method is characterized in that the bus analysis step is performed based on response information from a card to the test pattern. The bus analysis method according to any one of claims 8 to 12,
A bus analysis method, wherein a bus that is a target of the first protocol conversion step can be selected from any bus. The bus analysis method according to any one of claims 8 to 13,
The bus analysis method characterized in that the bus to be analyzed conforms to the PCI-Express standard.   A program for causing a computer to execute the bus analysis method according to any one of claims 8 to 14.

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