CN100359864C - Method and apparatus of CPU fault detection for signal processing unit - Google Patents
Method and apparatus of CPU fault detection for signal processing unit Download PDFInfo
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- CN100359864C CN100359864C CNB200610007949XA CN200610007949A CN100359864C CN 100359864 C CN100359864 C CN 100359864C CN B200610007949X A CNB200610007949X A CN B200610007949XA CN 200610007949 A CN200610007949 A CN 200610007949A CN 100359864 C CN100359864 C CN 100359864C
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Abstract
The present invention relates to a detecting method and a detecting device for the failure of a CPU in a signal processing unit. By utilizing the detecting method and the detecting device of the present invention, the CPU in the signal processing unit is detected according to a specified period, and thereby, the failure detecting rate of the CPU is enhanced, failure detecting information can be effectively transferred to the signal processing unit of a downstream communication site, and the downstream communication site can correctly recognize and carry out a correct action.
Description
Technical field
The present invention relates to the fault detect of communication equipment, relate to the detection method and the device of cpu fault in the signal processing unit particularly.
Background technology
In service at communication network, all signal routing schedulings all are that the webmaster by communication network carries out control operation, the interior CPU of signal processing unit is on the one hand by receiving the various command of webmaster in each communication site, finish the correct configuration of this signal processing unit all working chip, operating state and warning information with this signal processing unit in time is reported to webmaster on the other hand, webmaster is had at fingertips to the operating state of each website in the communication network, be convenient to the staff operating communication network is safeguarded.CPU is the core of each signal processing unit in the signal processing unit, if the CPU control unit breaks down, signal processing unit by its control will be out of hand, can't get in touch with other website in the communication network, this moment, signal processing unit can not receive the order of webmaster, can't report the operating state of the unit that breaks down again to webmaster.If if this fault can not in time be sent to next stage signal receiving unit or signal protection control unit, the signal of out of order signal unit just can't in time be protected so, communication will be interrupted, and communication equipment can not in time obtain safeguarding.Therefore the survey of the fault self-checking of communication equipment is very important, the fault detect of each signal processing unit is comprehensive more good more, and the result of fault detect also must be able to effectively export, make the downstream receiving element can correctly judge the upstream fault and can make correct operation, thereby make the work that communication equipment still can be reliable and stable when having local fault to take place, the communication network operation is not interrupted, and communication equipment also can in time obtain the fault message that has taken place and can accurately locate and in time obtain safeguarding simultaneously.Therefore, the fault that effectively detects CPU in the signal processing unit in the communication site is extremely important, require to accomplish can right judgement CPU fault, can export this fault message again and give other unit associated therewith.
In a kind of signal processing circuit unit design of prior art, utilize the house dog device of cpu chip periphery to run well with the program of keeping CPU.But as if this kind detection mode house dog occurs sometimes in operate as normal in application, but CPU but can not carry out normal running to the chip of being controlled, whole signal processing unit is in false normal operating conditions.The detection of cpu fault in the signal processing unit of another kind of prior art is to utilize interior field programmable gate array (FPGA) device of signal processing unit that CPU is detected.But when using this kind method, often energising back CPU only operates control FPGA device once, be the method be merely able to the detection signal processing unit power up initialization during CPU whether normal, the cpu fault that occurs for the working stage after the initialization can not correctly detect and export fault message.Because the CPU working state abnormal, then signal processing unit is just unavailable, need carry out the protection of signalling channel.In fact, the signal processing unit of above-mentioned prior art all exists CPU to break down and situation about not being detected, and this operation to the communication site brings hidden danger.In case this fault takes place, bring immeasurable loss will for Virtual network operator and user.
Summary of the invention
Purpose of the present invention just provides the detection method and the device of cpu fault in a kind of signal processing unit, to overcome the problem of above-mentioned existing in prior technology to the cpu fault omission.
The cpu fault checkout gear comprises FPGA device and clock in the signal processing unit of the present invention, CPU is after powering in the wherein said signal processing unit, carry out the program that is loaded, periodically refresh the register A in the FPGA device, described checkout gear is characterised in that in the FPGA device and comprises:
The detection signal generation module, constitute by counter, and receive the clock signal of self-clock and control signal from the interface module of communicating by letter with CPU, and to CPU operating state detection module periodicity output detection signal, the cycle of institute's output detection signal is many times that CPU refreshes the register A cycle;
CPU operating state detection module, constitute by register A and detection module, register A is connected with CPU and connection detection module by data wire and address wire, detection module receive detection signal from the detection signal generation module read register A deposit data and with reading of data last time relatively, output represent the code word of CPU operating state to the testing result output module then;
The testing result output module, form by verification and coding two parts, check part is carried out verification to the code word from the representative operating state of CPU operating state detection module, give coded portion with the verification result transmission, coded portion is encoded to the fault detect sign to the code word through verification, and outputs to fault detect sign output line;
The interface module of communicating by letter with CPU is connected with CPU with address wire by data wire, periodically produces control signal according to CPU institute assigned detection cycle Configuration Values, and control signal is passed to the detection signal generation module.
Cpu fault detection method in the signal processing unit of the present invention comprises step:
Carry out the program that is loaded after CPU powers on, periodically refresh the register A in the FPGA device; CPU carries out institute's loading procedure, by data wire and address wire cooperate in the FPGA device with cpu i/f module assignment sense cycle Configuration Values;
With the sense cycle Configuration Values of CPU communication interface modules basis, produce the counter that control signal is exported to the detection signal generation module from CPU;
The counter of detection signal generation module periodically produces detection signal and output detection signal and gives CPU operating state detection module interior detection module according to control signal and clock signal;
Detection module in the CPU operating state detection module is the storing value of detected register A periodically, and with storing value last time relatively, storing value changes then output and represents the normal code word of CPU as working state signal, otherwise then output represents that the code word of cpu fault is as working state signal;
Checking circuit in the testing result output module is to carrying out verification from the code word of CPU operating state detection module, continuous several times is received expression CPU code word working properly, judge that then this code word represents normal and export to wherein coding circuit, continuous several times is received the code word of expression cpu fault, judge that then this code word represents fault and export to wherein coding circuit that coding circuit is the output of fault detect marking signal with institute's receiving code word code.
According to cpu fault detection method in the above-mentioned signal processing unit of the present invention, it is characterized in that:
The interval that CPU refreshes the register A in the FPGA device is a random number about 5 milliseconds according to the CPU executive program;
CPU carries out institute's loading procedure, cooperates being 500 milliseconds with cpu i/f module assignment sense cycle Configuration Values in the FPGA device by data wire and address wire;
The concrete steps that CPU refreshes the register A in the FPGA device are that CPU reads original code of depositing from register A, with the code negate of being read, the code after the negate is write among the register A again;
The described checking procedure of the checking circuit in the testing result output module is: receive identical working state signal continuous three times from CPU operating state detection module, then judgment task state detection module signal is reliable, effective, by coding circuit the working state signal coding is become the output of fault detect sign, if the working state signal of continuous three receptions is inequality, then checking circuit judges that detected working state signal is unreliable, and coding circuit is still exported the fault detect encoding flag of exporting last time.
The parameter setting of detection method of the present invention is finished by the CPU institute's loading procedure that powers on.This CPU loading procedure makes CPU carry out surface function down: with about 5 milliseconds gap periods visit FPGA device; All the code negate in the register A in the FPGA device is refreshed again after each visit; CPU power up working properly after, the FPGA cell configuration is detected the sense cycle of CPU operating state by CPU.
Because the checkout gear that is used for cpu fault that in the circuit design of signal processing unit, increased of the present invention, this device detects CPU in the signal processing unit according to designated period, thereby improve the cpu fault verification and measurement ratio, and make fault detect information can be sent to downstream communication website signal processing unit effectively, make the correct identification of downstream communication website energy and carry out correct operation.The practical application test on the SDH communication equipment of checkout gear of the present invention and implementation method, result of the test proves, this method and apparatus not only can in time detect the fault of CPU in the signal processing unit, can also detect the correct configuration whether this signal processing unit obtains webmaster.
Description of drawings
Fig. 1 represents the general construction schematic diagram of signal processing unit of the present invention;
Fig. 2 is expressed as in the inventive method by the performed failure detection steps of CPU in the signal processing unit;
Fig. 3 represents to be arranged in the signal processing unit of the present invention detection signal generation module in the FPGA;
Fig. 4 represents to be arranged in the signal processing unit of the present invention the detection module of CPU operating state in the FPGA;
Fig. 5 is expressed as and is arranged at testing result output module in the FPGA in the signal processing unit of the present invention;
Fig. 6 is expressed as and is arranged at the interface module of communicating by letter with CPU in the FPGA in the signal processing unit of the present invention.
Embodiment
Fig. 1 is the signal processing unit general structure according to the present invention, and Fig. 2 is for relating to the execution in step of fault detect in the CPU executive program.As shown in Figure 1, CPU is connected with FPGA with data wire by address wire, and FPGA receives external timing signal and exports the fault detect marking signal.As shown in Figure 2, CPU powers on after the operate as normal, is handling the routine work step simultaneously, and fault detect workflow that also must execution graph 2 increases the software processes flow process that is used for detecting the CPU operating state.In one embodiment of the invention, CPU is programmed, be provided with its every the set time 5ms left and right sides time promptly according to presumptive address to FPGA in the register A operation that conducts interviews, the time interval of this accessing operation changes about 5ms owing to be subjected to the influence of the performed operate as normal program of CPU.This 5ms cycle also can be adjusted flexibly according to the CPU operating frequency.The value that CPU initially writes this register A in the FPGA can be arbitrarily, but but is convenient checking also certain predetermined value value.Because CPU need carry out the program run of operate as normal,, CPU can be slightly larger than or be slightly less than the 5ms visit refresh cycle that sets in advance usually so visiting the time cycle of this register A.CPU the refresh cycle then, the numerical value of storing among the register A is read, to institute's reading numerical values negate, the numerical value with negate writes among the register A again then.In this embodiment, the cycle of CPU operating state detection module detected register A is set to 100 times of CPU register A time, i.e. 500ms among the FPGA.Select 100 times and generally belong to the shortest sense cycle, and this sense cycle also can be selected according to concrete applicable cases by those skilled in the art, for example also can select sense cycle is second or the number of minutes magnitude.The 500ms sense cycle of selecting in the present embodiment by CPU by data wire and address wire with the mode of Configuration Values be transferred in the FPGA device with the CPU communication interface modules, passing to counter as the detection signal generation module by with the CPU communication interface modules Configuration Values being converted to control signal, counter produces detection signal according to this cycle and carries out detection to register A numerical value with Controlled CPU operating state detection module.The sense cycle default value that is provided with in institute's loading procedure when powering on is 500ms, and promptly the shortest sense cycle can be revised this sense cycle by the webmaster control panel under the operating state.In sense cycle, when detecting singlechip CPU refreshes register A in the FPGA by the time cycle property that is provided with value, then programmable device FPGA is just by the coded system output expression CPU code word of appointing working properly, do not refresh the value of register A when detect singlechip CPU in detection time by the time that is provided with, programmable device FPGA is just represented CPU abnormal code word of working by the coded system output of appointing.The used time ratio of detection time and CPU register A is big more, detects reliable more.
Explain the concrete implementation that detects step below in conjunction with Fig. 3 to 6.As shown in Figure 3, in embodiments of the present invention, the clock that counter receive clock generator produces sends detection signal every 500ms to CPU operating state detection module under control signal control.As shown in Figure 4, every interval 500ms is by the numerical value in the detection module detected register A, each is all different with the numerical value that detected last time if judge this numerical value, register A is by normal refresh in this expression, then the normal code word of detection module output expression CPU as working state signal to the testing result output module; If judge that numerical value and the last time of register A relatively are not that each all changes, then detection module output represent the normal code word of CPU as working state signal to the testing result output module.Normal or the abnormal code word of above-mentioned expression CPU is certain code word of prior agreement.In order to guarantee the reliability of testing result, the checking circuit that working state signal is transferred in the testing result output module carries out verification, if the operating state of three checks is identical in three continuous 500ms sense cycle, then checking circuit judges that just testing result is reliable, effectively, and testing result exported to coding circuit, there is coding circuit to be about to testing result and is encoded to the output of fault detect sign, if the operating state that continuous detecting is three times is inequality, think that then the detected operating state of CPU operating state detection module is unreliable, this moment, coding circuit was still exported the coding fault detect sign of last time.In a word, the testing result output module just refreshes the fault detect encoding flag value of once representing the CPU operating state every three 500ms sense cycle.
Utilized apparatus and method of the present invention in synchronous digital hierarchy (SDH) equipment, to carry out tentative application, this equipment utilization 8 position datawires of CPU, 8 address wires, and in FPGA, design and realized detecting the operating state device of CPU according to failure detector of the present invention.In the test, utilize the artificial CPU abnormal state of making, the reliability of check apparatus of the present invention, the result measures the fault detect encoding flag by oscilloscope and can accurately export on the fault detect marking signal outlet line of FPGA.In addition; insert whole SDH communication system will testing SDH equipment; when manual simulation's cpu fault, downstream communication website signal processing unit can correctly receive the alarm that upstream communication website signal processing unit produces owing to cpu fault, the execution signal protection switching action that the SDH system can be correct.Test shows, the detection method of cpu fault and device can either improve the verification and measurement ratio of fault in the signal processing unit of the present invention, and the maintenance efficiency of communication system has been improved in accurate position that again can fault location.
Claims (3)
1. cpu fault checkout gear in the signal processing unit, this device comprises FPGA device and clock, CPU is after powering in the wherein said signal processing unit, carry out the program that is loaded, periodically refresh the register A in the FPGA device, described checkout gear is characterised in that in the FPGA device and comprises:
The detection signal generation module, constitute by counter, and receive the clock signal of self-clock and control signal from the interface module of communicating by letter with CPU, and to CPU operating state detection module periodicity output detection signal, the cycle of institute's output detection signal is many times that CPU refreshes the register A cycle;
CPU operating state detection module, constitute by register A and detection module, register A is connected with CPU and connection detection module by data wire and address wire, detection module receive detection signal from the detection signal generation module read register A deposit data and with reading of data last time relatively, output represent the code word of CPU operating state to the testing result output module then;
The testing result output module, form by verification and coding two parts, check part is carried out verification to the code word from the representative operating state of CPU operating state detection module, give coded portion with the verification result transmission, coded portion is encoded to the fault detect sign to the code word through verification, and outputs to fault detect sign output line;
The interface module of communicating by letter with CPU is connected with CPU with address wire by data wire, periodically produces control signal according to CPU institute assigned detection cycle Configuration Values, and control signal is passed to the detection signal generation module.
2. cpu fault detection method in the signal processing unit comprises step:
Carry out the program that is loaded after CPU powers on, periodically refresh the register A in the FPGA device; CPU carries out institute's loading procedure, by data wire and address wire cooperate in the FPGA device with cpu i/f module assignment sense cycle Configuration Values;
With the sense cycle Configuration Values of CPU communication interface modules basis, produce the counter that control signal is exported to the detection signal generation module from CPU;
The counter of detection signal generation module periodically produces detection signal and output detection signal and gives CPU operating state detection module interior detection module according to control signal and clock signal;
Detection module in the CPU operating state detection module is the storing value of detected register A periodically, and with storing value last time relatively, storing value changes then output and represents the normal code word of CPU as working state signal, otherwise then output represents that the code word of cpu fault is as working state signal;
Checking circuit in the testing result output module is to carrying out verification from the code word of CPU operating state detection module, continuous several times is received expression CPU code word working properly, judge that then this code word represents normal and export to wherein coding circuit, continuous several times is received the code word of expression cpu fault, judge that then this code word represents fault and export to wherein coding circuit that coding circuit is the output of fault detect marking signal with institute's receiving code word code.
3. cpu fault detection method in the signal processing unit according to claim 2 is characterized in that:
The interval that CPU refreshes the register A in the FPGA device is a random number about 5 milliseconds according to the CPU executive program;
CPU carries out institute's loading procedure, cooperates being 500 milliseconds with cpu i/f module assignment sense cycle Configuration Values in the FPGA device by data wire and address wire;
The concrete steps that CPU refreshes the register A in the FPGA device are that CPU reads original code of depositing from register A, with the code negate of being read, the code after the negate is write among the register A again;
The described checking procedure of the checking circuit in the testing result output module is: receive identical working state signal continuous three times from CPU operating state detection module, then judgment task state detection module signal is reliable, effective, by coding circuit the working state signal coding is become the output of fault detect sign, if the working state signal of continuous three receptions is inequality, then checking circuit judges that detected working state signal is unreliable, and coding circuit is still exported the fault detect encoding flag of exporting last time.
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| CN101241463B (en) * | 2007-02-08 | 2010-09-01 | 北京天融信网络安全技术有限公司 | Method for accomplishing FPGA control and restoration |
| CN101252528B (en) * | 2008-04-14 | 2011-04-13 | 华为技术有限公司 | Method and apparatus for detecting malfunction |
| CN102546215B (en) * | 2010-12-30 | 2014-12-31 | 深圳市恒扬科技有限公司 | Method and device for protecting data link, and equipment with device |
| CN103425117B (en) * | 2012-05-22 | 2015-11-18 | 上海黄浦船用仪器有限公司 | For 092 torpedo directoor industrial computer Detection of Stability system |
| CN102929755B (en) * | 2012-09-27 | 2015-03-04 | 许继集团有限公司 | Fault detection method of CPU (Central Processing Unit) module address and data bus |
| JP6560489B2 (en) * | 2014-11-25 | 2019-08-14 | 株式会社日立製作所 | Control controller and control method thereof |
| CN104571091B (en) * | 2014-12-31 | 2017-09-29 | 重庆川仪自动化股份有限公司 | The controller failure detecting system of intelligent transducer |
| US9929858B2 (en) * | 2015-09-21 | 2018-03-27 | Nxp B.V. | Method and system for detecting fault attacks |
| JP7010268B2 (en) * | 2019-04-19 | 2022-01-26 | オムロン株式会社 | Communication monitoring system and communication monitoring method |
| CN113608914B (en) * | 2021-08-10 | 2024-04-26 | 安谋科技（中国）有限公司 | Chip, functional safety detection method of chip, medium and electronic equipment |
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| JP2000311987A (en) * | 1999-04-27 | 2000-11-07 | Hitachi Ltd | Semiconductor integrated circuit with testing function |
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| JP2000311987A (en) * | 1999-04-27 | 2000-11-07 | Hitachi Ltd | Semiconductor integrated circuit with testing function |
| CN1725189A (en) * | 2004-07-20 | 2006-01-25 | 华为技术有限公司 | Detection method for failure of chip |
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| 数字系统中CPU板故障诊断研究. 吴芝路；江志峰；任广辉；林茂六.电子测量技术，第3期. 1999 * |
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