CN1725189A - Detection method for failure of chip - Google Patents
Detection method for failure of chip Download PDFInfo
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- CN1725189A CN1725189A CN 200410070821 CN200410070821A CN1725189A CN 1725189 A CN1725189 A CN 1725189A CN 200410070821 CN200410070821 CN 200410070821 CN 200410070821 A CN200410070821 A CN 200410070821A CN 1725189 A CN1725189 A CN 1725189A
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Abstract
This invention discloses a test method for the fault of chips including: setting up image data of registers in all chips in the system memory separately, designing a first test period, when the first test period begins, registers needed to be tested in each chip are determined randomly judging if a fault happens to said chip in terms of the data in the registers to be tested and said image data, which can reduce occupation of CPU resource.
Description
Technical field
The present invention relates to the measuring technology of the electronics or the communications field, be specifically related to a kind of detection method of failure of chip.
Background technology
Development along with chip fabrication techniques, embedded microprocessor technology and software engineering, in the design of electronics and communication products, increasing ASIC (special IC)/VISI (ultra-large integrated circuit) is employed, raising along with chip integration, the function of single chip is more and more stronger, even develops into ASIC and other auxiliary circuits that have only to finish major function in the whole integrated circuit board.Therefore, in order to guarantee the normal operation of product, extremely important to the fault detection and diagnosis of this class chip.
In the reality, find by checking and statistics that reasons such as burning out appears in threshold value, chip if chip power supply power-fail or power supply voltage are lower than, short circuit cause chip functions to lose efficacy, the register value in the chip can change.For this class fault, adopt the method for " register is patrolled and examined " that chip is detected usually, promptly judge by regularly detecting whether the register of chip changes the quality of coming detection chip.
Concrete operations are: the data such as control, configuration that when system start-up, needs are written to register in the ASIC/VISI write earlier keep in the system a as mirror image, the signal of chip data mirror back-up as shown in Figure 1, and then be written among the ASIC/VISI, whether normal for the work of judging chip in normal operational process, regularly read the data in the related register in the chip, and with internal memory in the mirror image data that keeps compare, think chip failure if both are inconsistent.Then by the pre-designed diagnosis of start-up system, recover, restart supervisor, system recovery is normally moved.
Usually, for a baroque chip, when its inner register quantity is big, in order to guarantee the coverage rate of fault detect, all to patrol and examine at every turn, will take more cpu resource like this all registers, and when register quantity is big, whenever patrol and examine and once can consume the long time, the real time business that can influence system is handled.In order to reduce the influence that system's regular traffic is handled, when design, also can adopt the mode of only component register being patrolled and examined or prolonging polling period.
The mode that component register is patrolled and examined is meant: according to the function difference that each register is finished, choose some important registers and carry out timing as representative and patrol and examine.And entanglement of chip failure late register or the possibility that is modified are uncertain, might be that a register is modified, also might be to be modified in a large number, therefore, this selected part register as the detection method of representative can only detection chip partial failure, the coverage rate of detection is lower.
Can reduce relatively the taking of cpu resource though prolong the mode of polling period, the oversize sensitivity that will influence fault detect of polling period needs the long time just can detect after causing fault to take place.In addition, though prolonged polling period, but in a polling period, the time that all registers are patrolled and examined is fixed, if need in time to handle other business in the period at this section, then the processing capability in real time of system business can be had a strong impact on, and may cause patrolling and examining the unusual of result.
Summary of the invention
The detection method that the purpose of this invention is to provide a kind of failure of chip detects coverage rate and the low shortcoming of sensitivity when overcoming the fault detect of prior art chips.
The objective of the invention is to be achieved through the following technical solutions:
A kind of detection method of failure of chip comprises:
A, set up the mirror image data of register in all chips;
B, setting first sense cycle;
C, when described first sense cycle begins, determine the register that described chip need detect at random;
D, judge that data in the described register that need to detect are with described mirror image data and determine whether the described pairing chip of register of detection that needs breaks down.
Described C step specifically comprises:
C1, for register ordering and set its sequence number;
C2, the register that definite at random needs detect from register series.
Described C step specifically comprises:
C1, for register ordering and set its sequence number;
The register of selecting the important register in each chip to detect in C2 ', the register from the C1 step as needs.
Described step C2 specifically comprises:
First random number in C21, the described register series scope of generation;
C22, determine the register that needs detect according to described first random number.
Described step C22 is specially:
With sequence number is the register that described first random number detects as needs to the whole registers in the register series maximum range that needs to detect; Perhaps
With sequence number is the register that described first random number detects as needs to the whole registers in the register series minimum value scope that needs to detect.
Described step C22 is specially:
The register that sequence number is described first random number predetermined number destination register detects as needs to the register series maximum range that needs to detect; Perhaps
The register that sequence number is described first random number predetermined number destination register detects as needs to the register series minimum value scope that needs to detect.
Described step C22 is specially:
Produce second random number in the described register series scope that needs to detect;
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the ascending order mode selected number that circulates; Perhaps
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the descending mode selected number that circulates.
Described step C22 is specially:
Produce second random number in the described register series scope to be checked;
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the ascending order mode selected number that circulates; Perhaps
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the descending mode selected number that circulates.
Described step D comprises:
D1, set up register mirror image data concordance list;
D2, read the data in the described register that need to detect;
D3, obtain in the internal memory mirror image data of the register that detects corresponding to described needs according to described register mirror image data concordance list;
Data in D4, the more described register that reads and the mirror image data in the described register that obtains judge according to comparative result whether the chip at described register place breaks down.
Described register mirror image data concordance list comprises: address, register mirror image data start address, the register mirror image data length of register in chip.
Described method also comprises:
E, register in all chips is divided into the registers group of predetermined number;
F, setting second sense cycle;
G, successively when begin each described second round, obtain the data in the described registers group respectively;
H, judge according to data in the described registers group and described mirror image data whether described chip breaks down.
By above technical scheme provided by the invention as can be seen, the inventive method is carried out failure of chip by the register that needs to detect and is detected in each each chip of sense cycle picked at random, detect whole registers with respect to traversal, shortened sense cycle, reduced taking to system resource, detect by important register in each chip of picked at random, can further improve the sensitivity of fault detect, detect the major failure of chip in time, apace; Component register has improved the coverage rate of fault detect as the mode that representative detects in the chip with respect to fixedly choosing.The inventive method also by being attached to the detection task that detects whole registers in the some cycles by employing batch task traversal, has further improved the coverage rate of fault detect.
Description of drawings
Fig. 1 is a chip data mirror back-up synoptic diagram;
Fig. 2 is the process flow diagram of first embodiment of the invention;
Fig. 3 regularly travels through in batches that sense cycle concerns synoptic diagram in the detection task;
Fig. 4 is the process flow diagram that regularly in batches travels through the detection task in the inventive method;
Fig. 5 is the process flow diagram of second embodiment of the invention.
Embodiment
Core of the present invention is on the prior art basis, divide register to detect to change the picked at random chip internal into and divide register to detect fixedly choosing chip internal in the prior art, that is to say that foundation determines the chip that breaks down with the machine testing task; Setting the number of the register that each sense cycle will detect, can be fixed number, also can be random number; For the coverage rate that further guarantees to detect, set up the cycle detection task, promptly carry out simultaneously in some cycles, traveling through the detection task that detects whole registers in batches, determine the chip that all break down according to detection to whole registers.
In order to make those skilled in the art person understand the present invention program better, the present invention is described in further detail below in conjunction with drawings and embodiments.
With reference to Fig. 2, Fig. 2 is the process flow diagram of first embodiment of the invention:
At first, in step 201:, comprise following content with the machine testing task initialization:
(1) in Installed System Memory, set up the mirror image data of register in all chips respectively, and set up register mirror image data concordance list, can be referring to Fig. 1.
In a system, such as an integrated circuit board system, may have a plurality of chips, and may have the register of a plurality of storage difference in functionality data in each chip, sometimes the fault of certain register can not cause the inefficacy of chip all functions, equally, certain register can not guarantee that normally the chip all functions are effective, therefore sets up the mirror image data of register in all chips in Installed System Memory respectively.Which register is the detection task need detect in actual motion, chooses mirror image data that should register compared from internal memory to get final product.
Register mirror image data concordance list comprises: address, register mirror image data start address, the register mirror image data length of register in chip.As shown in table 1:
Table 1:
| The address of register in chip | Register mirror image data start address |
| ?1F20H | ?F120H |
| ?1F30H | ?F1?30H |
| ?2F20H | ?F2?50H |
| ?2F30H | ?F2?60H |
| ?… | ?… |
Wherein, the register position is represented in the address of register in chip; The start address that register mirror image data start address is represented to deposit in the internal memory to mirror image data that should register;
(2) be provided with machine testing task timer.The timing of this timer (first sense cycle) can wait to determine according to the quantity and the systemic-function of register in the system.
After finishing with the machine testing task initialization, start, after the timing of this timer arrives, enter step 202: start with the machine testing task with machine testing task timer.
Enter step 203: the register to be checked in selected each chip.Can be according to the difference of quantity, size and the function of register in each chip, register is classified and analyzed, losing efficacy or changed the back for register will be placed on important position to what system produced catastrophic failure.So just can register be divided into several classes, choose the base register that the most important register conduct of influence is selected at random, and then in these base registers, select a part at random as each register with machine testing according to importance.Certainly, also can select whole registers in the chip as register to be checked.
Step 204: for register to be checked ordering and set its sequence number.Selected register to be checked may be whole registers, also may be component register, for the realization of simplifying the detection task and the continuity that keeps these register number to be detected, these selected registers to be checked be sorted, and set its sequence number.
In order to find the chip at this register place according to sequence number, so that judge is to judge that a chip breaks down, also need to set up the corresponding relation of the address of register in chip in register series number and the register mirror image data concordance list, multiple mode can be arranged, such as: set up a sequence number conversion table, this table comprises the sequence number and register the address in chip corresponding with it of all registers to be checked, retrieves this conversion table according to the sequence number of register and can find the register that needs are patrolled and examined easily; The sequence number of register to be checked can also be added in the above-mentioned register mirror image data concordance list, on the correspondence position of not choosing as register to be checked, fill invalid bit, such as " NN ", when searching the chip at register place, number get final product as index with register series.As shown in table 2:
Table 2:
| The address of register in chip | Register mirror image data start address | Register series to be checked number |
| 1F20H | ?F120H | ?NN |
| 1F30H | ?F130H | ?1 |
| 2F20H | ?F250H | ?10 |
| 2F30H | ?F260H | ?7 |
| … | ?… | ?… |
Then, enter step 205: register that from register series to be checked, need to determine detection at random.So just can guarantee each chip is all regularly detected, and each detection is register important, representational, at random.
Behind the register of determining at random to need to detect, enter step 206: read the data in the register that needs to detect successively.Because it is a plurality of to need the register of detection to have, need detect one by one.
Step 207: the mirror image data that obtains the register that detects corresponding to needs in the internal memory according to register mirror image data concordance list.
Behind the register of in above-mentioned steps 205, having determined to need to detect, also just known the sequence number of this register, mention in front, can there be multiple mode to set up the corresponding relation of the address of register in chip in register series number and the register mirror image data concordance list, number can know the address of register in chip according to register series, know this register mirror image data start address and length according to register mirror image data concordance list again, from internal memory, obtain mirror image data corresponding to this register according to these information.
Then, enter step 208: judge whether the data in the register are identical with mirror image data in the internal memory.
If identical, show that then register place chip is normal, enter step 209: wait for next sense cycle.After that is to say that wait arrives timing once more with machine testing task timer, restart, carry out failure of chip according to said process and detect with the machine testing task.
If inequality, show that then register place chip breaks down, and enters step 210: carry out fault handling.
Pointed out need to determine at random from register series to be checked the register of detection in above-mentioned steps 205, its process is as follows:
At first, produce the interior random number (first random number) of register series scope to be checked.The present technique field personnel know, random number has multiple producing method, can choose suitable manner according to system's actual conditions, is not described in detail at this.
Then, from register series to be checked, select the register that needs detect according to this random number.The quantity of the register that each detection task is selected can identical, also can be different.
Suppose that register to be checked has 1000, can register be sorted that sequence number is 1～1000 according to the address size of register.
(1) supposes to patrol and examine 100 at every turn, random integers N between producing one 1～1000 by program when at every turn needing to detect, the register that sequence number is identical with these random integers is as first register that detects, patrol and examine 100 registers of its back, promptly sequence number is the register of N to N+100 at every turn; Perhaps patrol and examine the register of 100 register N-100 to N of its front at every turn.
When if the value of N+100 exceeds the maximum sequence number 1000 of register, then can only detect sequence number backward from sequence number N is 1000 register; Also can from register series to be checked, do ascending order circulation and select, that is to say detect 1000 after, again since 1, select 100 registers altogether as detected object.
Equally, if the value of N-100 less than the minmal sequence of register number 1 o'clock, then can only detect sequence number forward from sequence number N is 1 register; Also can from register series to be checked, do descending circulation and select, that is to say detect 1 after, again since 1000, select 100 registers altogether as detected object.
(2) suppose the register quantity difference of at every turn patrolling and examining, better simply mode is: the random integers N between producing 1～1000 by program when at every turn needing to detect, the register that sequence number is identical with these random integers is patrolled and examined the register that sequence number is N～1000 as first register that detects at every turn; Perhaps patrol and examine the register that sequence number is 0～N at every turn.According to register series number ascending or descending sequence detection.
(3) if the register quantity of patrolling and examining not simultaneously, after producing first random integers N, can also produce the second random number M in the register series scope to be checked, as the quantity of patrolling and examining register at every turn at every turn.
The register that sequence number is identical with the first random integers N is as first register that detects, M the register of at every turn patrolling and examining its back, and promptly sequence number is the register of N to N+M; Perhaps patrol and examine the register of M register N-M to N of its front at every turn.
Equally, if the value of N+M exceeds the maximum sequence number 1000 of register, perhaps the value of N-100 selects the register of N～1000 or 1～N to detect less than the minmal sequence of register number 1 o'clock; Also can do circulation and select, select M register and detect register to be checked.
Certainly, also have much other selection modes at random, its selection course is similar to the above, is not described in detail at this.
In order to reduce, select most important in each chip, representational register to detect as far as possible to the taking of system resource;
In order to improve the sensitivity of fault detect, can in the scope that system allows, shorten polling period as far as possible, the timing that just is provided with machine testing task timer is less value.
If all patrol and examine the cpu resource that takies 10ms, the register of so each sampling Detection 10% then only needs the cpu resource of 1ms.Same on whole resources occupation rate, as adopting the timing patrol task of 100ms, if select the resources occupation rate of whole register patrol tasks to reach 10%; If each sampling Detection 10%, then the resources occupation rate of patrol task has only 1%.
In order to ensure the coverage rate of fault detect better, on above-mentioned basis with the machine testing task, additional timing travels through the detection task in batches.Its basic thought is the registers group that register in all chips is divided into predetermined number (S), patrol and examine each data block successively by timed task then, the cycle of supposing this timed task is t, just can finish patrolling and examining all chip registers so in S timed task cycle t.Patrol and examine all registers take time and be T=S*t.
Fig. 3 shows the relation between them:
Begin in each sense cycle (0, t, 2t ...) after, select a registers group, successively each register in this registers group is detected all registers in having detected this registers group.Only take the very little a section of a sense cycle t detection time of each registers group.After next sense cycle begins, select next registers group to detect.Reduce the taking of cpu resource with this, improve failure checking cover ratio.
With reference to Fig. 4, Fig. 4 illustrates the flow process that above-mentioned timing travels through the detection task in batches:
Step 401: regularly traversal detects task initialization in batches, comprises that traversal is set detects timer, and the timing of this timer (second sense cycle) can wait to determine according to the quantity and the systemic-function of register in the system; And initialization register group X, begin to detect from first registers group usually, i.e. X=0.Certainly, also can choose a registers group arbitrarily begins.
Step 402: start the detection task that regularly in batches travels through.
Step 403: register in all chips is divided into S registers group.Each registers group can comprise the register of equal number, also can comprise the register of varying number.Suppose registers group from 0 open numbering, 0～S-1 registers group then arranged.
Step 404: start traversal and detect timer.
Step 405: obtain X registers group.
Step 406: read the data in the register that needs to detect successively.
Step 407: judge whether mirror image data corresponding in data and the internal memory in the register is identical.
If mirror image data corresponding in the data in the register and the internal memory is different, then enter step 411: carry out fault handling.
If identical, then enter step 408: the value of X is added 1, that is to say and choose next registers group.
Then, enter step 409: whether the value of judging X equals S, that is to say to detect last registers group whether.
If X equals S, then enter step 410: the value of X is reset to 0, promptly select first registers group to detect.If X is since 0, then show that timesharing has detected intrasystem whole registers one time this moment.
Then, return step 404: start traversal and detect timer, carry out the detection of next cycle.
If X is not equal to S, then directly turn back to step 404, wait for the detection of next cycle.
Above-mentioned timing travel through in batches the detection task can be in system independent operating, its advantage is that to take cpu resource less, the traversal that can finish all registers detects, and makes failure checking cover ratio reach maximum; Shortcoming is that the fault detection sensitivity is lower, can not detect the fault of total system chips in time.
For sensitivity and the coverage rate that ensures detection, in the methods of the invention, above-mentioned timing is traveled through the detection task in batches to combine with the machine testing task with foregoing, give full play to advantage separately, two are detected the task independent operating, finish detection separately, any one detection task detects the abnormal conditions that failure of chip is all thought system.
With reference to Fig. 5, Fig. 5 is the process flow diagram of second embodiment of the invention:
In this embodiment, detection is separately finished in two separate operations of detection task.
At first, in step 51: system initialization comprises following content:
(1) in Installed System Memory, sets up the mirror image data of register in all chips respectively, and set up register mirror image data concordance list.For the existing explanation in register mirror image data concordance list front, do not repeat them here.
(2) register in all chips is divided into the registers group of predetermined number, and sets up the registers group sequence table.According to size and system's actual needs of register, each registers group comprises the register of same number or the register of a plurality of different numbers.A preferable packet mode is the component register that all includes each chip in every group, like this, just makes the component register that can detect each chip in the sense cycle, helps improving the detection coverage rate.
The registers group sequence table comprises registers group sequence number, the register address in chip, and is as shown in table 3 below.
Table 3:
| The registers group sequence number | The address of register in chip |
| ?1 | ?1F20H |
| ?1 | ?2F30H |
| ?2 | ?2F20H |
| ?3 | ?1F30H |
| ?3 | ?3F20H |
| ?… | ?… |
For the processing of simplifying procedures, also can not set up the registers group sequence table separately, but the registers group sequence number is added in the above-mentioned register mirror image data concordance list, be about to the register mirror image data rope table shown in the previous table 2 and change table 4 into:
Table 4:
| The address of register in chip | Register mirror image data start address | Register series to be checked number | The registers group sequence number |
| 1F20H | ?1F20H | ?NN | ?1 |
| 1F30H | ?1F30H | ?1 | ?3 |
| 2F20H | ?2F50H | ?10 | ?2 |
| 2F30H | ?2F60H | ?7 | ?1 |
| … | ?… | ?… |
(3) be provided with machine testing task timer and traversal and detect timer, wherein, with the timing (first sense cycle) of machine testing task timer for carrying out the time interval with the machine testing task; Traversal detects the timing (second sense cycle) of timer for carry out the time interval that travels through the detection task in batches.
After system initialization is finished, enter step 52: start with machine testing task timer and traversal and detect timer.
After the timing with machine testing task timer arrives,
Enter step 511: start with the machine testing task.
Then, enter step 512: determine the register that each chip need detect in the system at random.The detailed process of determining the register that each chip need detect in the system at random can be with reference to the description of front.
Enter step 513: obtain the mirror image data in the internal memory of the register correspondence that needs detect according to register mirror image data concordance list.
Step 514: the mirror image data in the internal memory of data in the register of Jian Ceing and correspondence judges whether chip breaks down as required.
Detect the timing arrival of timer when traversal after,
Enter step 521: start the detection task that regularly in batches travels through.
Then, enter step 522: from the registers group sequence table, choose a registers group.Can also can choose a registers group wantonly and begin from first registers group.
Step 523: the data of obtaining different registers in the registers group respectively.
Then, enter step 524: obtain the mirror image data in the internal memory of register correspondence according to register mirror image data concordance list.
Step 525: judge according to the mirror image data in the internal memory of data in the register and correspondence whether chip breaks down.
After the next one begins with the machine testing duty cycle, proceed according to above-mentioned detection mode with the machine testing task.
When the next one after regularly traversal detects duty cycle and begins in batches, proceed according to the above-mentioned detection mode that travels through the detection task in batches.It should be noted that in each sense cycle at this, only all over registers group of strict detection.For the coverage rate that guarantees to detect, need detect one by one according to the registers group sequence table, so that in the fixed cycle, all detect all registers in each chip.
In the practical application of the foregoing description, the complexity when realizing in order to reduce software can only detect fixing, important register with changing into the machine testing task.Like this, can reduce the complexity of software, ensure the sensitivity that detects by detection again, guarantee the coverage rate of fault detect by travel through the detection task in batches simultaneously fixing, important register.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, wish that appended claim comprises these distortion and variation and do not break away from spirit of the present invention.
Claims (10)
1, a kind of detection method of failure of chip is characterized in that, comprising:
A, set up the mirror image data of register in all chips;
B, setting first sense cycle;
C, when described first sense cycle begins, determine the register that described chip need detect at random;
D, judge that data in the described register that need to detect are with described mirror image data and determine whether the described pairing chip of register of detection that needs breaks down.
2, method according to claim 1 is characterized in that, described C step specifically comprises:
C1, for register ordering and set its sequence number;
C2, the register that definite at random needs detect from register series.
3, method according to claim 2 is characterized in that, described C step specifically comprises:
C1, for register ordering and set its sequence number;
The register of selecting the important register in each chip to detect in C2 ', the register from the C1 step as needs.
4, method according to claim 2 is characterized in that, described step C2 specifically comprises:
First random number in C21, the described register series scope of generation;
C22, determine the register that needs detect according to described first random number.
5, method according to claim 4 is characterized in that, described step C22 is specially:
With sequence number is the register that described first random number detects as needs to the whole registers in the register series maximum range that needs to detect; Perhaps
With sequence number is the register that described first random number detects as needs to the whole registers in the register series minimum value scope that needs to detect.
6, method according to claim 4 is characterized in that, described step C22 is specially:
The register that sequence number is described first random number predetermined number destination register detects as needs to the register series maximum range that needs to detect; Perhaps
The register that sequence number is described first random number predetermined number destination register detects as needs to the register series minimum value scope that needs to detect.
7, method according to claim 4 is characterized in that, described step C22 is specially:
Produce second random number in the described register series scope that needs to detect;
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the ascending order mode selected number that circulates; Perhaps
With sequence number is that the register of described first random number is a reference position, is described second register that detect as needs of several registers at random according to the descending mode selected number that circulates.
8, method according to claim 2 is characterized in that, described step D specifically comprises:
D1, set up register mirror image data concordance list;
D2, read the data in the described register that need to detect;
D3, obtain in the internal memory mirror image data of the register that detects corresponding to described needs according to described register mirror image data concordance list;
Data in D4, the more described register that reads and the mirror image data in the described register that obtains judge according to comparative result whether the chip at described register place breaks down.
9, method according to claim 1 is characterized in that, described register mirror image data concordance list comprises: address, register mirror image data start address, the register mirror image data length of register in chip.
10, method according to claim 1 and 2 is characterized in that, described method also comprises:
E, register in all chips is divided into the registers group of predetermined number;
F, setting second sense cycle;
G, successively when begin each described second round, obtain the data in the described registers group respectively;
H, judge according to data in the described registers group and described mirror image data whether described chip breaks down.
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Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1145972C (en) * | 2000-03-30 | 2004-04-14 | 华为技术有限公司 | Automatic test method and circuit for RAM |
| CN1230830C (en) * | 2001-12-20 | 2005-12-07 | 华为技术有限公司 | RAM high speed test control circuit and its testing method |
| JP3785388B2 (en) * | 2002-09-17 | 2006-06-14 | 松下電器産業株式会社 | Failure detection method |
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2004
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100359864C (en) * | 2006-02-23 | 2008-01-02 | 烽火通信科技股份有限公司 | Method and apparatus of CPU fault detection for signal processing unit |
| CN102360325A (en) * | 2011-09-26 | 2012-02-22 | 青岛海信信芯科技有限公司 | Debugging method and device of register |
| CN102360325B (en) * | 2011-09-26 | 2017-06-23 | 青岛海信电器股份有限公司 | Register adjustment method and device |
| CN105320583A (en) * | 2014-07-31 | 2016-02-10 | 上海华虹集成电路有限责任公司 | UVM (universal verification methodology) based write-only register verification test platform and verification method |
| CN105373458A (en) * | 2014-09-01 | 2016-03-02 | 上海华虹集成电路有限责任公司 | Internal signal detection method for UVM verification platform and application |
| CN105446844A (en) * | 2014-09-01 | 2016-03-30 | 上海华虹集成电路有限责任公司 | Read-only register verification test platform and verification method based on UVM (Universal Verification Methodology Manual) |
| CN108875415A (en) * | 2018-06-28 | 2018-11-23 | 福建超瑞创原信息技术有限公司 | A kind of safety method and device of random detection |
| CN110793639A (en) * | 2019-11-18 | 2020-02-14 | 北京和普威视科技股份有限公司 | Method and system for judging health state of infrared thermal imaging machine core |
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