CN107678909B - Circuit and method for monitoring chip configuration state in server - Google Patents
Circuit and method for monitoring chip configuration state in server Download PDFInfo
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- CN107678909B CN107678909B CN201710635684.6A CN201710635684A CN107678909B CN 107678909 B CN107678909 B CN 107678909B CN 201710635684 A CN201710635684 A CN 201710635684A CN 107678909 B CN107678909 B CN 107678909B
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 7
- 230000000630 rising effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
- G06F11/3093—Configuration details thereof, e.g. installation, enabling, spatial arrangement of the probes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The invention provides a circuit and a method for monitoring a chip configuration state in a server. The circuit comprises a functional chip, a logic control unit, a resistance configuration circuit connected with a configuration pin of the functional chip and other modules. The reset signal and the configuration pins of the functional chip are connected to the logic control unit. Aiming at the purpose of detecting whether the configuration information of the functional chip is correct, the invention realizes the recording and alarming when the configuration information of the chip is wrong by connecting the reset signal and the configuration signal to the logic control unit and by a detection and comparison mechanism of the logic control unit.
Description
Technical Field
The invention relates to a server chip configuration detection technology.
Background
In server design, the adopted functional chip has multiple configuration modes, and a designer needs to set configuration information according to actual needs. The chip collects the level state of a specific pin during reset to carry out internal configuration. After the chip reset signal is released, the specific pin will be restored to other functions. The main connections are as shown in figure 1.
Since the configuration function is shared with other functions, the configuration pins are also connected to other functional modules, and the connection may affect the configuration condition of the functional chip. Therefore, in the conventional test of the server, an oscilloscope is used for actually measuring the high and low level states when the configuration pins are reset, so as to ensure the correctness of the design. But this measurement is too labor intensive. Therefore, a design capable of automatically detecting the chip configuration state is required.
Disclosure of Invention
The present invention provides a circuit and a method for monitoring chip configuration status in a server, which has the advantages of automatic monitoring of chip configuration information, automatic error recording and alarming.
In order to achieve the above object, the present invention adopts the following technical solutions.
A circuit for monitoring chip configuration state in server comprises a functional chip, a logic control unit, a resistance configuration circuit connected with a functional chip configuration pin and other modules. The reset signal and the configuration pins of the functional chip are connected to the logic control unit.
Further, the Logic control unit is one of a CPLD (Complex Programmable Logic Device) or an FPGA (Field-Programmable Gate Array).
Further, the reset signal is from one or more of a key, a power-on reset circuit, or other logic unit.
Further, the logic control unit is connected to a BMC (Baseboard Management Controller) and configured to send the functional chip state information to the BMC.
Furthermore, the logic control unit is connected with a fault indicator lamp and used for displaying the fault state of the functional chip.
A method for monitoring chip configuration state in server, logic control unit continuously detects edge of reset signal, if low reset is effective in reset signal, then detects rising edge, otherwise detects falling edge. And after the corresponding edge is detected, the logic control unit reads the level state of the current configuration pin, compares the level state with a preset normal state, and records error information and gives an alarm if the level state and the preset normal state are inconsistent.
Further, when the level state of the configuration pin is compared with the preset normal state and the level state and the preset normal state are inconsistent, the logic control unit sends the information of the chip configuration fault to the BMC and lights a fault indicator lamp.
The invention has the beneficial effects that: aiming at the purpose of detecting whether the configuration information of the functional chip is correct, the invention realizes the recording and alarming when the configuration information of the chip is wrong by connecting the reset signal and the configuration signal to the logic control unit and by a detection and comparison mechanism of the logic control unit.
Drawings
Fig. 1 is a prior art circuit connection schematic.
Fig. 2 is a circuit connection diagram of the present embodiment.
Detailed Description
The invention is further described with reference to the following figures and examples.
A circuit for monitoring chip configuration state in server comprises a functional chip, a CPLD, a resistance configuration circuit connected with a functional chip configuration pin and other modules. The reset signal and the configuration pin of the functional chip are connected to the CPLD. The reset signal comes from the key, the power-on reset circuit and other logic units. And the CPLD is connected with the BMC and is used for sending the state information of the functional chip to the BMC. And the CPLD is connected with a fault indicator lamp and is used for displaying the fault state of the functional chip.
A CPLD continuously detects the edge of a reset signal, if the low reset is effective during the reset signal, the CPLD detects the rising edge, and otherwise, the CPLD detects the falling edge. And when the corresponding edge is detected, the CPLD reads the level state of the current configuration pin, compares the level state with the preset normal state, and records error information and gives an alarm if the level state is inconsistent with the preset normal state. And the CPLD sends the information of the chip configuration fault to the BMC and lights a fault indicator lamp.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (7)
1. A circuit for monitoring chip configuration state in a server is characterized by comprising a functional chip, a logic control unit, a resistance configuration circuit connected with a functional chip configuration pin and other modules; the reset signal and the configuration pin of the functional chip are connected to the logic control unit; the logic control unit is used for detecting the edge of the reset signal, reading the level states of other modules and the resistance configuration circuit on the current configuration pin after detecting the corresponding edge, comparing the level states with a preset normal state, and recording error information and giving an alarm if the level states are inconsistent.
2. The circuit for monitoring the configuration status of a chip in a server according to claim 1, wherein the logic control unit is one of a CPLD or an FPGA.
3. The circuit for monitoring the configuration status of a chip in a server according to claim 1, wherein the reset signal is from one or more of a key, a power-on reset circuit, or a logic unit.
4. The circuit for monitoring chip configuration status in a server of claim 1, wherein the logic control unit is connected to the BMC for sending the functional chip status information to the BMC.
5. The circuit for monitoring the configuration status of a chip in a server according to claim 1, wherein the logic control unit is connected to a fault indicator for displaying the fault status of the functional chip.
6. A method for monitoring chip configuration state in a server is characterized in that a logic control unit continuously detects the edge of a reset signal, if the reset signal is low reset effective, a rising edge is detected, otherwise, a falling edge is detected; when the corresponding edge is detected, the logic control unit reads the level states of other modules on the current configuration pin and the resistance configuration circuit, compares the level states with a preset normal state, and if the level states are not consistent with the preset normal state, the logic control unit records error information and gives an alarm;
the functional chip configuration pin is connected with the resistance configuration circuit and other modules; the reset signal and the configuration pin of the functional chip are connected to the logic control unit; the logic control unit is used for detecting the edge of the reset signal.
7. The method as claimed in claim 6, wherein when the level status of the configuration pin is different from the predetermined normal status, the logic control unit sends a chip configuration failure message to the BMC and turns on the failure indicator.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710635684.6A CN107678909B (en) | 2017-07-31 | 2017-07-31 | Circuit and method for monitoring chip configuration state in server |
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| CN201710635684.6A CN107678909B (en) | 2017-07-31 | 2017-07-31 | Circuit and method for monitoring chip configuration state in server |
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| CN107678909A CN107678909A (en) | 2018-02-09 |
| CN107678909B true CN107678909B (en) | 2020-06-16 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108919696B (en) * | 2018-05-29 | 2020-03-20 | 郑州云海信息技术有限公司 | Method capable of realizing UID-LED multi-state control |
| CN108923977A (en) * | 2018-07-10 | 2018-11-30 | 郑州云海信息技术有限公司 | A kind of configuration method of server, device and server apparatus |
| CN109101358A (en) * | 2018-07-27 | 2018-12-28 | 郑州云海信息技术有限公司 | Server system and its hardware log recording device and method |
| CN109508279A (en) * | 2018-11-28 | 2019-03-22 | 郑州云海信息技术有限公司 | A kind of server monitoring device, method and its system |
| CN111752223B (en) * | 2020-06-29 | 2022-04-01 | 配天机器人技术有限公司 | Signal configuration method, input/output device and computer storage medium |
| CN112463502B (en) * | 2020-12-11 | 2022-11-11 | 苏州浪潮智能科技有限公司 | Method, device and system for detecting pin state of programmable logic device |
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| CN103927279A (en) * | 2013-01-16 | 2014-07-16 | 京信通信系统（中国）有限公司 | FPGA configuration method, FPGA configuration system and processor |
| CN104461994A (en) * | 2014-11-12 | 2015-03-25 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA-based embedded processor dynamic configuration circuit and method |
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| CN101136036A (en) * | 2006-10-12 | 2008-03-05 | 中兴通讯股份有限公司 | Combined on site programmable gate array verification device |
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