CN102375775B - Computer system unrecoverable error indication signal detection circuit - Google Patents
Computer system unrecoverable error indication signal detection circuit Download PDFInfo
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- CN102375775B CN102375775B CN201010253254.6A CN201010253254A CN102375775B CN 102375775 B CN102375775 B CN 102375775B CN 201010253254 A CN201010253254 A CN 201010253254A CN 102375775 B CN102375775 B CN 102375775B
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Abstract
The invention discloses a computer system for detecting unrecoverable error indication signal, and comprises a plurality of central process units (CPU), a complex programmable logic apparatus, a south bridge and a substrate management controller, wherein when the computer system is in unrecoverable error, at least one CPU outputs an unrecoverable error indication signal; the complex programmable logic apparatus is electrically coupled to the CPU; the south bridge is electrically coupled to the complex programmable logic apparatus; and the substrate management controller is electrically coupled to the complex programmable apparatus. When the unrecoverable error indication signal is divided into a signal pulse signal and a plurality of continuous pulse signals, the complex programmable logic apparatus correspondingly transmits the pulse signals to the south bridge or the substrate management controller so as to restart the computer system. By using the detection circuit provided by the invention, the indication signal can be transmitted to the south bridge or the substrate management controller according to the classes of the indication signals so as to output a restart command through the south bridge or the substrate management controller to restart the system.
Description
Technical field
The present invention relates to a kind of computer system, relate in particular to a kind of computer system with detection system fatal error indicator signal.
Background technology
Current, whether server system, when normal operation, experiences the system mistake in some operational processs sometimes, according to these mistakes, can recover to divide, and roughly comprises recoverable error and irrecoverable error.When there is recoverable error, in order to improve the reliability of server system, it is configured to conventionally when producing recoverable error, catching these can recover or amendable mistake by its write error daily record, utilize the handling procedure of seizure and log recording to chance of server system user, to before whole system collapse, replace defective memory cell, allow system recover normal operation.Yet, when occurring that unrecoverable error mistakes, show that server system can not continue operation and must restart.
In view of this, how designing a kind of testing circuit, occur that unrecoverable error is mistaken both can send reset command and restart system in system, can record the specifying information relevant with CPU again, is those skilled in the art problem urgently to be resolved hurrily.
Summary of the invention
For prior art Computer system, detecting the unrecoverable error existing above-mentioned defect of mistaking, the invention provides a kind of novel computer system with detection system fatal error indicator signal.
According to an aspect of the present invention, provide a kind of computer system with detection system fatal error indicator signal, for computer system, this computer system comprises:
A plurality of central processor units, mistake when unrecoverable error appears in this computer system, and at least one central processor unit is exported a fatal error indicator signal;
One CPLD, is electrically coupled to described central processor unit, and receives this fatal error indicator signal;
One south bridge, is electrically coupled to described CPLD; And
One baseboard management controller, is electrically coupled to described CPLD;
Wherein, when described fatal error indicator signal is individual pulse signal, this CPLD is sent to this south bridge by described fatal error indicator signal, and by this south bridge output reset command, to restart this computer system; When described fatal error indicator signal is plural continuous impulse signal, this CPLD is sent to this baseboard management controller by described fatal error indicator signal, and by this baseboard management controller output reset command, to restart this computer system.
Preferably, described CPLD is sent to described south bridge or baseboard management controller by received fatal error indicator signal, and by the daily record of described baseboard management controller generation error.In addition, described error log comprises the numbering of the central processor unit relevant to this fatal error indicator signal.
Preferably, the described computer system with detection system fatal error indicator signal also comprises a plurality of voltage transformation modules, and each voltage transformation module is electrically coupled to corresponding central processor unit, respectively this voltage transformation module receives the fatal error indicator signal of this central processor unit output and amplifies the intensity of this fatal error indicator signal.According to one embodiment of the invention, voltage transformation module comprises a NPN transistor, and its emitter is coupled to described central processor unit, and its collector is coupled to described CPLD.According to another embodiment of the present invention, voltage transformation module comprises a CMOS transistor, and its source electrode is coupled to described central processor unit, and its drain electrode is coupled to described CPLD.
Preferably, when expendable gross error occurs computer system, from the fatal error indicator signal of corresponding central processor unit, be Low level effective.
Preferably, the universal input and output port of baseboard management controller by a plurality of universal input and output port records the described system fatal error indicator signal that a central processor unit of described a plurality of central processor units sends.
Preferably, this computer system is a server.
Adopt the computer system with detection system fatal error indicator signal of the present invention, when CPLD receives fatal error indicator signal, can be sent to south bridge or baseboard management controller according to the classification of indicator signal, to restart system by south bridge or baseboard management controller.In addition,, when CPLD receives fatal error indicator signal, baseboard management controller can generation error daily record, clearly to record fatal error indicator signal, comes from which central processor unit.
Accompanying drawing explanation
Reader, after having read the specific embodiment of the present invention with reference to accompanying drawing, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates according to one embodiment of the invention, in computer system for detection of the integrated stand composition of the testing circuit of system fatal error indicator signal; And
Fig. 2 further illustrates the circuit theory diagrams of the voltage transformation module in the system fatal error indicator signal testing circuit shown in Fig. 1.
Embodiment
With reference to the accompanying drawings, the specific embodiment of the present invention is described in further detail.
Fig. 1 illustrates according to one embodiment of the invention, has the integrated stand composition of the computer system of detection system fatal error indicator signal.For example, the computer system here can be server.With reference to Fig. 1, the computer system with detection system fatal error indicator signal comprises central processor unit (CPU, Central Processor Unit) 101 and 103, CPLD 109, south bridge 111 and baseboard management controller 113.When appearring in computer system, unrecoverable error mistakes, by central processor unit 101 or central processor unit 103 output one fatal error indicator signals.CPLD 109 is electrically coupled to central processor unit 101 and 103, and receives the system fatal error indicator signal from central processor unit 101 and 103.
In addition, south bridge 111 is electrically coupled to CPLD 109, and baseboard management controller 113 is electrically coupled to CPLD 109, thus, when the fatal error indicator signal from central processor unit is individual pulse signal, CPLD 109 is sent to south bridge 111 by this fatal error indicator signal, and by south bridge 111 output reset command, thereby restart computer system.And when the fatal error indicator signal from central processor unit is plural continuous impulse signal, CPLD 109 is sent to baseboard management controller 113 by this fatal error indicator signal, and by baseboard management controller 113 output reset command, thereby restart computer system.It is to be noted, in this computer system, why by south bridge 111 and baseboard management controller 113, export respectively reset command to restart system, because when fatal error indicator signal is a plurality of continuous pulse signal, south bridge can crash, so turn in this case by baseboard management controller 113, comes control system to restart.
If those of ordinary skill in the art should be appreciated that the computer system for single cpu, when there is expendable gross error, understand by this expendable gross error of this CPU automatic Check, and notifying south bridge to send reset command subsequently.Obviously, in this case, the CPU of fatal error indicator signal source is clear and definite and clearly, can't cause obscure maybe cannot be definite phenomenon., for the computer system with two or more CPU, available technology adopting multichannel fatal error indicator signal sends control module together to, and is sent request to south bridge by control module, by south bridge, exports reset command.Like this, indicator signal that specifically which CPU to send fatal error by can not determine, and when fatal error indicator signal is continuous pulse signal, south bridge can crash and cannot restart in time.
According to one embodiment of the invention, computer system also comprises voltage transformation module 105 and voltage transformation module 107, wherein voltage transformation module 105 is electrically connected central processor unit 101 and CPLD 109, and voltage transformation module 107 is electrically connected central processor unit 103 and CPLD 111.Those of ordinary skill in the art is to be understood that, voltage transformation module 105 and 107 in this embodiment is not that computer system of the present invention is necessary, they are only used to amplify or strengthen the intensity of fatal error indicator signal, and the present invention also has more than and is confined to this.
From the above, by computer system of the present invention, complete just the detection of fatal error indicator signal, could pick out very lucidly the numbering with the closely-related central processor unit of fatal error indicator signal.Preferably, voltage transformation module 105 and 107 is the identical change-over circuits of electronic component arrangements.
Should be understood that, no matter the fatal error indicator signal receiving is individual pulse or continuous a plurality of pulses, CPLD 109 all sends identifying information to baseboard management controller 113, and by baseboard management controller 113 generation error daily records.For example, this error log comprises the numbering of the central processor unit relevant to this fatal error indicator signal.For instance, when central processor unit 101 or 103 sends indicator signal, baseboard management controller 113 can record relevant journal entries, and journal entries can record the fatal error indicator signal being sent by central processor unit 101 or central processor unit 103.
Fig. 2 further illustrates the circuit theory diagrams of the voltage transformation module of the computer system with detection system fatal error indicator signal shown in Fig. 1.Be not difficult to find out, corresponding to the voltage transformation module 105 of central processor unit 101, corresponding to the voltage transformation module 107 of central processor unit 103, can be arranged to identical together.Hereinafter with arbitrary voltage transformation module, be elaborated.
For the purpose of describing, presetting fatal error indicator signal is Low level effective.That is to say, when fatal error indicator signal presents low level, there is expendable gross error in illustrative system; On the contrary, when fatal error indicator signal presents high level, illustrative system is in normal operating condition.Should be understood that, also predeterminable fatal error indicator signal is that high level is effective, and correspondingly changes electronic component arrangements model and parameter in voltage transformation module.
Take Low level effective as example, when the fatal error indicator signal from central processor unit 101 is high level, and while being electrically coupled to the emitter of NPN transistor Q1, Q1 is not because meeting unlocking condition in cut-off state, now, the collector of Q1 presents high level.Because the collector of Q1 is electrically connected to CPLD 109, what corresponding to the universal input port of Q1 collector, receive be also high level signal, and CPLD 109 can't transmit information to notify south bridge or baseboard management controller to send reset command.On the other hand, when the fatal error indicator signal from central processor unit 101 is low level, the base stage of Q1 and the voltage between emitter are in positively biased, and Q1 is in conducting state, now, the collector of Q1 and emitter form electrical path and present low level.Because the collector of Q1 is electrically connected to CPLD 109, what corresponding to the universal input port of Q1 collector, receive is also low level signal, and CPLD 109 is by transmission information and allow baseboard management controller 113 record current error log.Preferably, the universal input and output port of baseboard management controller by a plurality of universal input and output port records the system fatal error indicator signal that a central processor unit of a plurality of central processor units sends.For example, by error log, just can know central processor unit 101 and when gross error appears in system, send fatal error indicator signal.
Although those of ordinary skill in the art should be appreciated that voltage transformation module in Fig. 2 mainly by NPN transistor completed conversion between level (as, from the level signal of 1.1V, convert the level signal of 3.3V to), the present invention has more than and is confined to this.For example, can also adopt CMOS transistor to substitute NPN transistor, can complete level conversion function equally.
Adopt the computer system with detection system fatal error indicator signal of the present invention, when the CPLD in testing circuit receives fatal error indicator signal, can be sent to south bridge or baseboard management controller according to the classification of indicator signal, to restart system by south bridge or baseboard management controller.In addition,, when CPLD receives fatal error indicator signal, baseboard management controller can generation error daily record, clearly to record fatal error indicator signal, comes from which central processor unit.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, without departing from the spirit and scope of the present invention in the situation that, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replacement all drop in the claims in the present invention book limited range.
Claims (7)
1. a computer system with detection system fatal error indicator signal, is characterized in that, this computer system comprises:
A plurality of central processor units, mistake when unrecoverable error appears in this computer system, and at least one central processor unit is exported a fatal error indicator signal;
One CPLD, is electrically coupled to described central processor unit, and receives this fatal error indicator signal;
One south bridge, is electrically coupled to described CPLD; And
One baseboard management controller, is electrically coupled to described CPLD;
Wherein, when described fatal error indicator signal is individual pulse signal, this CPLD is sent to this south bridge by described fatal error indicator signal, and by this south bridge output reset command, to restart this computer system; When described fatal error indicator signal is plural continuous impulse signal, this CPLD is sent to this baseboard management controller by described fatal error indicator signal, and by this baseboard management controller output reset command, to restart this computer system
Wherein, described CPLD is sent to described south bridge or baseboard management controller by received fatal error indicator signal, and by the daily record of described baseboard management controller generation error, described error log comprises the numbering of the central processor unit relevant to this fatal error indicator signal.
2. the computer system with detection system fatal error indicator signal as claimed in claim 1, it is characterized in that, described system fatal error indicator signal testing circuit also comprises a plurality of voltage transformation modules, and each voltage transformation module is electrically coupled to corresponding central processor unit, respectively this voltage transformation module receives the fatal error indicator signal of this central processor unit output and amplifies the intensity of this fatal error indicator signal.
3. the computer system with detection system fatal error indicator signal as claimed in claim 2, it is characterized in that, described voltage transformation module comprises a NPN transistor, and its emitter is coupled to described central processor unit, and its collector is coupled to described CPLD.
4. the computer system with detection system fatal error indicator signal as claimed in claim 2, it is characterized in that, described voltage transformation module comprises a CMOS transistor, and its source electrode is coupled to described central processor unit, and its drain electrode is coupled to described CPLD.
5. the computer system with detection system fatal error indicator signal as claimed in claim 1, it is characterized in that, when expendable gross error occurs described computer system, from the fatal error indicator signal of corresponding central processor unit, be Low level effective.
6. the computer system with detection system fatal error indicator signal as claimed in claim 1, it is characterized in that, the universal input and output port of described baseboard management controller by a plurality of universal input and output port records the described system fatal error indicator signal that a central processor unit of described a plurality of central processor units sends.
7. the computer system with detection system fatal error indicator signal as claimed in claim 1, is characterized in that, described computer system is a server.
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| CN201010253254.6A CN102375775B (en) | 2010-08-11 | 2010-08-11 | Computer system unrecoverable error indication signal detection circuit |
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| CN201010253254.6A CN102375775B (en) | 2010-08-11 | 2010-08-11 | Computer system unrecoverable error indication signal detection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE112014003065T5 (en) * | 2014-04-25 | 2016-03-17 | Mitsubishi Electric Corporation | Programmable logic controller |
| NO3121726T3 (en) | 2014-06-24 | 2018-06-30 | ||
| CN108345562B (en) * | 2014-12-16 | 2022-03-29 | 超聚变数字技术有限公司 | Multi-path server and signal processing method thereof |
| CN106201961B (en) * | 2016-07-01 | 2019-05-07 | 英业达科技有限公司 | The calculator system and method for control processor working frequency |
| CN106919490A (en) * | 2017-02-19 | 2017-07-04 | 郑州云海信息技术有限公司 | Server failure detection method and device |
| CN109932995B (en) * | 2017-12-18 | 2021-06-15 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949182A (en) * | 2005-10-14 | 2007-04-18 | 戴尔产品有限公司 | Detecting correctable errors and logging information relating to their location in memory |
| CN101630278A (en) * | 2008-07-18 | 2010-01-20 | 深圳富泰宏精密工业有限公司 | Method for recording crash abnormal information of electronic device and electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949182A (en) * | 2005-10-14 | 2007-04-18 | 戴尔产品有限公司 | Detecting correctable errors and logging information relating to their location in memory |
| CN101630278A (en) * | 2008-07-18 | 2010-01-20 | 深圳富泰宏精密工业有限公司 | Method for recording crash abnormal information of electronic device and electronic device |
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Owner name: HANGZHOU POWER SUPPLY COMPANY,STATE GRID ZHEJIANG Effective date: 20141127 Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: YINGYEDA CO., LTD., TAIWAN Effective date: 20141127 |
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Inventor after: Xu Rongyong Inventor after: Zhang Wei Inventor after: Hua Chengjun Inventor after: Hong Jie Inventor after: Zhan Lei Inventor after: Wu Xiaohui Inventor after: Zheng Jianjun Inventor after: Nie Haitao Inventor after: Liu Lei Inventor after: Wei Yu Inventor before: Cai Yusheng Inventor before: Fan Wengang |
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Free format text: CORRECT: ADDRESS; FROM: TAIWAN, CHINA TO: 100031 XICHENG, BEIJING Free format text: CORRECT: INVENTOR; FROM: CAI YUSHENG FAN WENGANG TO: XU RONGYONG HUA CHENGJUN HONG JIE ZHAN LEI YU XIAOHUI ZHENG JIANJUN NIE HAITAO LIU LEI WEI YU ZHANG WEI |
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Effective date of registration: 20141127 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: Hangzhou Power Supply Company, State Grid Zhejiang Electric Power Company Patentee after: STATE GRID ZHEJIANG TONGLU POWER SUPPLY COMPANY Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. sixty-six Patentee before: Inventec Corporation |