CN102375775A - System unrecoverable error indication signal detection circuit - Google Patents
System unrecoverable error indication signal detection circuit Download PDFInfo
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- CN102375775A CN102375775A CN2010102532546A CN201010253254A CN102375775A CN 102375775 A CN102375775 A CN 102375775A CN 2010102532546 A CN2010102532546 A CN 2010102532546A CN 201010253254 A CN201010253254 A CN 201010253254A CN 102375775 A CN102375775 A CN 102375775A
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- indicator signal
- error indicator
- fatal error
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Abstract
The invention discloses a system unrecoverable error indication signal detection circuit. The system unrecoverable error indication signal detection circuit is used for a computer system, and comprises a plurality of central process units (CPU), a complex programmable logic apparatus, a south bridge and a substrate management controller, wherein when the computer system is in unrecoverable error, at least one CPU outputs an unrecoverable error indication signal; the complex programmable logic apparatus is electrically coupled to the CPU; the south bridge is electrically coupled to the complex programmable logic apparatus; and the substrate management controller is electrically coupled to the complex programmable apparatus. When the unrecoverable error indication signal is divided into a signal pulse signal and a plurality of continuous pulse signals, the complex programmable logic apparatus correspondingly transmits the pulse signals to the south bridge or the substrate management controller so as to restart the computer system. By using the detection circuit provided by the invention, the indication signal can be transmitted to the south bridge or the substrate management controller according to the classes of the indication signals so as to output a restart command through the south bridge or the substrate management controller to restart the system.
Description
Technical field
The present invention relates to a kind of computer system, relate in particular to the system's fatal error indicator signal testing circuit in this computer system.
Background technology
Current, whether server system experiences the system mistake in some operational processs sometimes when normal operation, can recover to divide according to these mistakes, roughly comprises recoverable error and irrecoverable error.When recoverable error occurring; In order to improve the reliability of server system, it is configured to usually when producing recoverable error, catches these and can recover or amendable mistake and with its write error daily record; Utilize the handling procedure of seizure and log record to give chance of server system user; So that before the total system collapse, replace defective memory cell, let system recovery normally move.Yet, mistake when unrecoverable error occurring, show that server system can not continue to move and must restart.
In view of this, how designing a kind of testing circuit, unrecoverable error occurs in system and mistake and both can send reset command and restart system, can write down the specifying information relevant with CPU again, is the problem that those skilled in the art need to be resolved hurrily.
Summary of the invention
Detecting the unrecoverable error existing above-mentioned defective of mistaking, the invention provides a kind of novel system's fatal error indicator signal testing circuit to computer system in the prior art.
According to an aspect of the present invention, a kind of system fatal error indicator signal testing circuit is provided, has been used for computer system, this system's fatal error indicator signal testing circuit comprises:
A plurality of central processor units are mistaken when unrecoverable error appears in this computer system, and at least one central processor unit is exported a fatal error indicator signal;
One CPLD is electrically coupled to said central processor unit, and receives this fatal error indicator signal;
One south bridge is electrically coupled to said CPLD; And
One baseboard management controller is electrically coupled to said CPLD;
Wherein, when said fatal error indicator signal was the individual pulse signal, this CPLD was sent to this south bridge with said fatal error indicator signal, and by this south bridge output reset command, to restart this computer system; When said fatal error indicator signal is plural continuous impulse signal; This CPLD is sent to this baseboard management controller with said fatal error indicator signal; And by this baseboard management controller output reset command, to restart this computer system.
Preferably, said CPLD is sent to said south bridge or baseboard management controller with the fatal error indicator signal that is received, and by the daily record of said baseboard management controller generation error.In addition, said error log comprises the numbering of the central processor unit relevant with this fatal error indicator signal.
Preferably; Said system fatal error indicator signal testing circuit also comprises a plurality of voltage transformation modules; And each voltage transformation module is electrically coupled to the corresponding central processor unit, and respectively this voltage transformation module receives the fatal error indicator signal of this central processor unit output and amplifies the intensity of this fatal error indicator signal.According to one embodiment of the invention, voltage transformation module comprises a NPN transistor, and its emitter is coupled to said central processor unit, and its collector is coupled to said CPLD.According to another embodiment of the present invention, voltage transformation module comprises a CMOS transistor, and its source electrode is coupled to said central processor unit, and its drain electrode is coupled to said CPLD.
Preferably, when expendable gross error takes place computer system, be that low level is effective from the fatal error indicator signal of corresponding central processor unit.
Preferably, the universal input and output port of baseboard management controller through a plurality of universal input and output port writes down the said system fatal error indicator signal that a central processor unit of said a plurality of central processor units is sent.
Preferably, this computer system is a server.
Adopt system of the present invention fatal error indicator signal testing circuit; When the CPLD in the testing circuit receives the fatal error indicator signal; Can be sent to south bridge or baseboard management controller according to the classification of indicator signal, to restart system through south bridge or baseboard management controller.In addition, when CPLD received the fatal error indicator signal, baseboard management controller can the generation error daily record, comes from which central processor unit clearly to write down the fatal error indicator signal.
Description of drawings
The reader with reference to advantages after the embodiment of the present invention, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates according to one embodiment of the invention, in computer system, is used for the integrated stand composition of the testing circuit of detection system fatal error indicator signal; And
Fig. 2 further specifies the circuit theory diagrams of the voltage transformation module in system's fatal error indicator signal testing circuit shown in Figure 1.
Embodiment
With reference to the accompanying drawings, specific embodiments of the invention is done further to describe in detail.
Fig. 1 illustrates according to one embodiment of the invention, in computer system, is used for the integrated stand composition of the testing circuit of detection system fatal error indicator signal.For example, the computer system here can be a server.With reference to Fig. 1; This system's fatal error indicator signal testing circuit (for simplicity; Testing circuit hereinafter referred to as) comprises central processor unit (CPU, Central Processor Unit) 101 and 103, CPLD 109, south bridge 111 and baseboard management controller 113.When appearring in computer system, unrecoverable error mistakes, by central processor unit 101 or central processor unit 103 outputs one fatal error indicator signal.CPLD 109 is electrically coupled to central processor unit 101 and 103, and receives the system's fatal error indicator signal from central processor unit 101 and 103.
In addition; South bridge 111 is electrically coupled to CPLD 109, and baseboard management controller 113 is electrically coupled to CPLD 109, thus; When the fatal error indicator signal from central processor unit is the individual pulse signal; CPLD 109 is sent to south bridge 111 with this fatal error indicator signal, and by south bridge 111 output reset command, thereby restart computer system.And when the fatal error indicator signal from central processor unit is plural continuous impulse signal; CPLD 109 is sent to baseboard management controller 113 with this fatal error indicator signal; And by baseboard management controller 113 output reset command, thereby restart computer system.It is to be noted; In this computer system; Why export reset command respectively to restart system by south bridge 111 and baseboard management controller 113; Be because when the fatal error indicator signal was a plurality of consecutive pulses signal, south bridge can crash, so commentaries on classics comes control system to restart by baseboard management controller 113 under this situation.
If those of ordinary skill in the art should be appreciated that the computer system for single cpu, when expendable gross error takes place, can check this expendable gross error automatically by this CPU, and notify south bridge to send reset command subsequently.Obviously, in this case, the CPU of fatal error indicator signal source is clear and definite and clearly, can't cause and obscure the phenomenon that maybe can't confirm., for the computer system with two or more CPU, available technology adopting multichannel fatal error indicator signal sends control module together to, and sends request by control module to south bridge, exports reset command through south bridge.Like this, indicator signal that specifically which CPU to send fatal error by can not be confirmed, and when the fatal error indicator signal was the consecutive pulses signal, south bridge can crash and can't in time restart.
According to one embodiment of the invention; Testing circuit also comprises voltage transformation module 105 and voltage transformation module 107; Wherein voltage transformation module 105 electrically connects central processor unit 101 and CPLD 109, and voltage transformation module 107 electrically connects central processor unit 103 and CPLD 111.Those of ordinary skill in the art is to be understood that; Voltage transformation module 105 and 107 among this embodiment is not that testing circuit of the present invention is necessary; They only are in order to amplify or strengthen the intensity of fatal error indicator signal, and the present invention also has more than and is confined to this.
From the above, accomplish the detection of fatal error indicator signal just through testing circuit of the present invention, could pick out numbering very lucidly with the closely-related central processor unit of fatal error indicator signal.Preferably, voltage transformation module 105 and 107 is the identical change-over circuits of electronic component arrangements.
Should be understood that; No matter the fatal error indicator signal that is received is individual pulse or continuous a plurality of pulses; CPLD 109 all sends identifying information to baseboard management controller 113, and by baseboard management controller 113 generation error daily records.For example, this error log comprises the numbering of the central processor unit relevant with this fatal error indicator signal.For instance; When central processing unit unit 101 or 103 sends indicator signal; Baseboard management controller 113 can write down relevant journal entries, and journal entries can write down the fatal error indicator signal of being sent by central processor unit 101 or central processor unit 103.
Fig. 2 further specifies the circuit theory diagrams of the voltage transformation module in system's fatal error indicator signal testing circuit shown in Figure 1.Be not difficult to find out, can be arranged to identical corresponding to the voltage transformation module 107 of central processor unit 103 together corresponding to the voltage transformation module 105 of central processor unit 101.Hereinafter be elaborated with arbitrary voltage transformation module.
For the purpose of describing, preestablishing the fatal error indicator signal is that low level is effective.That is to say that when the fatal error indicator signal presented low level, expendable gross error appearred in illustrative system; On the contrary, when the fatal error indicator signal presented high level, illustrative system was in normal operating condition.Should be understood that also predeterminable fatal error indicator signal is that high level is effective, and correspondingly change electronic component arrangements model and parameter in the voltage transformation module.
With low level effectively is example; When the fatal error indicator signal from central processor unit 101 is a high level, and when being electrically coupled to the emitter of NPN transistor Q1, Q1 is not in cut-off state because of meeting unlocking condition; At this moment, the collector of Q1 presents high level.Because the collector of Q1 is electrically connected to CPLD 109; What then receive corresponding to the general input port of Q1 collector also be high level signal, and CPLD 109 can't transmit information and send reset command to notify south bridge or baseboard management controller.On the other hand; When the fatal error indicator signal from central processor unit 101 was low level, the base stage of Q1 and the voltage between emitter were in positively biased, and Q1 is in conducting state; At this moment, the collector of Q1 and emitter form electrical path and present low level.Because the collector of Q1 is electrically connected to CPLD 109; What then receive corresponding to the general input port of Q1 collector also be low level signal, and CPLD 109 will transmit information and let baseboard management controller 113 write down current error log.Preferably, the universal input and output port of baseboard management controller through a plurality of universal input and output port writes down system's fatal error indicator signal that a central processor unit of a plurality of central processor units is sent.For example, just can know through error log and sent the fatal error indicator signal when central processor unit 101 gross error occurs in system.
Though those of ordinary skill in the art should be appreciated that among Fig. 2 voltage transformation module mainly through NPN transistor accomplished conversion between the level (as, convert the level signal of 3.3V to from the level signal of 1.1V), the present invention has more than and is confined to this.For example, can also adopt the CMOS transistor to substitute NPN transistor, can accomplish the level conversion function equally.
Adopt system of the present invention fatal error indicator signal testing circuit; When the CPLD in the testing circuit receives the fatal error indicator signal; Can be sent to south bridge or baseboard management controller according to the classification of indicator signal, to restart system through south bridge or baseboard management controller.In addition, when CPLD received the fatal error indicator signal, baseboard management controller can the generation error daily record, comes from which central processor unit clearly to write down the fatal error indicator signal.
In the preceding text, illustrate and describe embodiment of the present invention.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also specific embodiments of the invention do various changes and replacement.These changes and replacement all drop in claims of the present invention institute restricted portion.
Claims (9)
1. system's fatal error indicator signal testing circuit is used for computer system, it is characterized in that, this system's fatal error indicator signal testing circuit comprises:
A plurality of central processor units are mistaken when unrecoverable error appears in this computer system, and at least one central processor unit is exported a fatal error indicator signal;
One CPLD is electrically coupled to said central processor unit, and receives this fatal error indicator signal;
One south bridge is electrically coupled to said CPLD; And
One baseboard management controller is electrically coupled to said CPLD;
Wherein, when said fatal error indicator signal was the individual pulse signal, this CPLD was sent to this south bridge with said fatal error indicator signal, and by this south bridge output reset command, to restart this computer system; When said fatal error indicator signal is plural continuous impulse signal; This CPLD is sent to this baseboard management controller with said fatal error indicator signal; And by this baseboard management controller output reset command, to restart this computer system.
2. the system of claim 1 fatal error indicator signal testing circuit; It is characterized in that; Said CPLD is sent to said south bridge or baseboard management controller with the fatal error indicator signal that is received, and by the daily record of said baseboard management controller generation error.
3. system as claimed in claim 2 fatal error indicator signal testing circuit is characterized in that said error log comprises the numbering of the central processor unit relevant with this fatal error indicator signal.
4. the system of claim 1 fatal error indicator signal testing circuit; It is characterized in that; Said system fatal error indicator signal testing circuit also comprises a plurality of voltage transformation modules; And each voltage transformation module is electrically coupled to the corresponding central processor unit, and respectively this voltage transformation module receives the fatal error indicator signal of this central processor unit output and amplifies the intensity of this fatal error indicator signal.
5. system as claimed in claim 4 fatal error indicator signal testing circuit; It is characterized in that; Said voltage transformation module comprises a NPN transistor, and its emitter is coupled to said central processor unit, and its collector is coupled to said CPLD.
6. system as claimed in claim 4 fatal error indicator signal testing circuit; It is characterized in that; Said voltage transformation module comprises a CMOS transistor, and its source electrode is coupled to said central processor unit, and its drain electrode is coupled to said CPLD.
7. the system of claim 1 fatal error indicator signal testing circuit; It is characterized in that; When expendable gross error takes place said computer system, be that low level is effective from the fatal error indicator signal of corresponding central processor unit.
8. the system of claim 1 fatal error indicator signal testing circuit; It is characterized in that the universal input and output port of said baseboard management controller through a plurality of universal input and output port writes down the said system fatal error indicator signal that a central processor unit of said a plurality of central processor units is sent.
9. the system of claim 1 fatal error indicator signal testing circuit is characterized in that, said computer system is a server.
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Cited By (6)
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| CN104503947A (en) * | 2014-12-16 | 2015-04-08 | 华为技术有限公司 | Multi-server and signal processing method thereof |
| CN105393178A (en) * | 2014-04-25 | 2016-03-09 | 三菱电机株式会社 | Programmable logic controller |
| CN106201961A (en) * | 2016-07-01 | 2016-12-07 | 英业达科技有限公司 | Control calculator system and the method for processor working frequency |
| CN106919490A (en) * | 2017-02-19 | 2017-07-04 | 郑州云海信息技术有限公司 | Server failure detection method and device |
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| US10353763B2 (en) | 2014-06-24 | 2019-07-16 | Huawei Technologies Co., Ltd. | Fault processing method, related apparatus, and computer |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105393178A (en) * | 2014-04-25 | 2016-03-09 | 三菱电机株式会社 | Programmable logic controller |
| CN105393178B (en) * | 2014-04-25 | 2017-05-24 | 三菱电机株式会社 | Programmable logic controller |
| US10353763B2 (en) | 2014-06-24 | 2019-07-16 | Huawei Technologies Co., Ltd. | Fault processing method, related apparatus, and computer |
| US11360842B2 (en) | 2014-06-24 | 2022-06-14 | Huawei Technologies Co., Ltd. | Fault processing method, related apparatus, and computer |
| CN104503947A (en) * | 2014-12-16 | 2015-04-08 | 华为技术有限公司 | Multi-server and signal processing method thereof |
| CN106201961A (en) * | 2016-07-01 | 2016-12-07 | 英业达科技有限公司 | Control calculator system and the method for processor working frequency |
| CN106919490A (en) * | 2017-02-19 | 2017-07-04 | 郑州云海信息技术有限公司 | Server failure detection method and device |
| CN109932995A (en) * | 2017-12-18 | 2019-06-25 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
| CN109932995B (en) * | 2017-12-18 | 2021-06-15 | 鸿富锦精密电子(天津)有限公司 | Electronic device |
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| CN102375775B (en) | 2014-08-20 |
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Owner name: HANGZHOU POWER SUPPLY COMPANY,STATE GRID ZHEJIANG Effective date: 20141127 Owner name: STATE GRID CORPORATION OF CHINA Free format text: FORMER OWNER: YINGYEDA CO., LTD., TAIWAN Effective date: 20141127 |
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Inventor after: Xu Rongyong Inventor after: Zhang Wei Inventor after: Hua Chengjun Inventor after: Hong Jie Inventor after: Zhan Lei Inventor after: Wu Xiaohui Inventor after: Zheng Jianjun Inventor after: Nie Haitao Inventor after: Liu Lei Inventor after: Wei Yu Inventor before: Cai Yusheng Inventor before: Fan Wengang |
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Free format text: CORRECT: ADDRESS; FROM: TAIWAN, CHINA TO: 100031 XICHENG, BEIJING Free format text: CORRECT: INVENTOR; FROM: CAI YUSHENG FAN WENGANG TO: XU RONGYONG HUA CHENGJUN HONG JIE ZHAN LEI YU XIAOHUI ZHENG JIANJUN NIE HAITAO LIU LEI WEI YU ZHANG WEI |
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Effective date of registration: 20141127 Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing Patentee after: State Grid Corporation of China Patentee after: Hangzhou Power Supply Company, State Grid Zhejiang Electric Power Company Patentee after: STATE GRID ZHEJIANG TONGLU POWER SUPPLY COMPANY Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. sixty-six Patentee before: Inventec Corporation |