CN102694616B - Clock detection circuit, clock circuit and clock exception detection method - Google Patents
Clock detection circuit, clock circuit and clock exception detection method Download PDFInfo
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Abstract
The invention provides a clock detection circuit, a clock circuit and a clock exception detection method, wherein the clock detection circuit comprises a first clock driver, a second clock driver, a logical control unit, a logical switching circuit and a memory, and the logical control unit is used for acquiring configuration information from the memory, respectively carrying out exception detection on clock signals output by the first clock driver and the second clock driver according to the configuration information, and controlling the logical switching circuit to switch the first clock driver and the second clock driver when the clock signal output by the first clock driver is detected to generate an exception and the clock signal output by the second clock driver is further normal, so that the second clock driver provides the clock signal for an exchange chip through the logical switching circuit. According to the technical scheme of the invention, the defect that the detection of a low-frequency clock by using a high-frequency clock is limited is overcome while the redundancy of the clock signal is realized.
Description
Technical field
The present invention relates to the communication technology, relate in particular to a kind of clock detection circuit, clock circuit and clock method for detecting abnormality.
Background technology
All communication systems are all the synchronous logics driving with at least one dagital clock signal, so the importance of clock signal is unquestionable, any road clock signal goes wrong, and all can cause whole communication system normally to work.But practical application shows,, in order to address this problem, there is master/backup clock redundant technique in the less stable of clock source in some communication systems.For example, the telecommunication apparatus of ethernet port is because require to have higher reliability and fault-tolerant ability, so used two-way, master/backup clock source redundancy.
In master/backup clock redundant technique, by master clock is detected, when detecting that when abnormal, complete in time the switching of backup clock, thereby ensureing that to greatest extent business is not interrupted appears in master clock.The comparatively conventional abnormal method of detection clock is to use high frequency clock to detect low-frequency clock at present.The detailed process of the method is: adopt a reference clock, detected clock signal is counted with reference clock, by judge that whether the count value of each detected clock signal is equaled to preset value is found to be detected clock signal and whether occur extremely.In the method, require the frequency of reference clock higher than the frequency of detected clock, if cannot obtain the reference clock of higher frequency, cannot detect detected clock, as can be seen here, due to the requirement to reference clock frequency, the application of the method is restricted.
Summary of the invention
The invention provides a kind of clock detection circuit, clock circuit and clock method for detecting abnormality, in order to overcome by the limited defect of high frequency clock detection low-frequency clock.
One aspect of the present invention provides a kind of clock detection circuit, comprising: the first clock driver, second clock driver, logic control element, logic commutation circuit and memory;
Described the first clock driver is connected with the first clock source and described logic commutation circuit, for providing clock signal by described logic commutation circuit to exchange chip; Described second clock driver is connected with second clock source and described logic commutation circuit, and described logic commutation circuit is connected with described exchange chip;
Described memory, the configuration information using for being stored into row clock input;
Described logic control element is connected with described memory, described the first clock driver, described second clock driver and described logic commutation circuit, for obtaining described configuration information from described memory, the clock signal of the clock signal of respectively described the first clock driver being exported according to described configuration information and the output of described second clock driver is carried out abnormality detection; And it is abnormal to know that in detection the clock signal of described the first clock driver output occurs, and when the clock signal of described second clock source output is normal, control described logic commutation circuit and switch described the first clock driver and described second clock driver, so that described second clock driver provides clock signal by described logic commutation circuit to described exchange chip.
The present invention provides a kind of clock method for detecting abnormality on the other hand, comprising:
Obtain and detect the configuration information that clock signal is used;
The clock signal of the clock signal of respectively the first clock driver being exported according to described configuration information and the output of second clock driver is carried out abnormality detection; Wherein, described the first clock source is for providing clock signal to exchange chip;
The clock signal of knowing described the first clock driver output if detect occurs abnormal, and the clock signal of described second clock driver output is normal, switch described the first clock source and described second clock source, so that described second clock source provides clock signal to described exchange chip.
Another aspect of the invention provides a kind of clock circuit, comprises arbitrary clock detection circuit provided by the invention, the first clock source and second clock source.
Clock detection circuit provided by the invention and clock circuit, respectively the clock signal in the first clock source and second clock source is divided into two-way and offers respectively logic control element and logic commutation circuit by two clock drivers, the configuration information that logic control element provides according to processor carries out abnormality detection to the clock signal of two clock driver outputs respectively, and when forward direction exchange chip, to provide the clock signal of the clock driver output of clock signal to occur abnormal detecting, and the clock signal of another clock driver output is when normal, control logic commutation circuit is switched two-way clock driver, so that another clock driver provides clock signal to exchange chip, complete the switching of clock signal.As seen from the above analysis, the present invention is in the situation that realizing clock signal redundancy, use configuration information to carry out abnormality detection to clock signal, no longer as prior art, the clock signal with clock source output counts to detect the abnormal of clock signal to high frequency clock, no longer need the clock signal of higher frequency, overcome and used high-frequency signal to detect the defect that low frequency signal exists.
Brief description of the drawings
The structural representation of the clock detection circuit that Fig. 1 provides for one embodiment of the invention;
The structural representation of the clock detection circuit that Fig. 2 provides for another embodiment of the present invention;
The structural representation of the clock circuit that Fig. 3 provides for one embodiment of the invention;
The flow chart of the clock method for detecting abnormality that Fig. 4 A provides for one embodiment of the invention;
The flow chart of the clock method for detecting abnormality that Fig. 4 B provides for another embodiment of the present invention;
The logic control element that Fig. 5 provides for one embodiment of the invention carries out the flow chart of fast detecting within the first detection time to the clock signal of the first clock driver or the output of second clock driver;
The logic control element that Fig. 6 provides for one embodiment of the invention carries out the flow chart of slow detection within the second detection time to the clock signal of the first clock driver or the output of second clock driver;
The flow chart of the clock method for detecting abnormality that Fig. 7 provides for further embodiment of this invention;
The contrast schematic diagram of the first detection time that Fig. 8 provides for one embodiment of the invention and the clock signal of 125MHz;
The contrast schematic diagram of the second detection time that Fig. 9 provides for one embodiment of the invention and the clock signal of 125MHz.
Embodiment
The structural representation of the clock detection circuit that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the clock detection circuit of the present embodiment comprises: the first clock driver 11, second clock driver 12, logic control element 13, logic commutation circuit 14 and memory 15.
Wherein, the first clock driver 11 is connected with the first clock source and logic commutation circuit 14, for providing clock signal by logic commutation circuit 14 to exchange chip.Second clock driver 12 is connected with second clock source and logic commutation circuit 14, and logic commutation circuit 14 is connected with exchange chip.
Optionally, second clock driver 12 occurs when abnormal, to provide clock signal by logic commutation circuit 14 to exchange chip for the clock signal of exporting at the first clock driver 11.
Wherein, exchange chip can be medium access control (Media Access Control, MAC) chip and/or physics (Physical, PHY) chip, but is not limited to this.
In the present embodiment, the first clock source and second clock source backup each other, and that is to say, the clock signal that two clock sources provide is identical.This means that the clock signal that the first clock driver 11 and second clock driver 12 are exported is also identical.Described clock signal is identical refers to that the parameter (such as frequency, amplitude etc.) of clock signal is identical.
Memory 15, detects for storing the configuration information that clock signal is used.Logic control element 13 respectively with memory 15, the first clock driver 11, second clock driver 12 is connected with logic commutation circuit 14, for obtaining described configuration information from memory 15, according to the configuration information obtaining from memory 15, the clock signal that the clock signal of respectively the first clock driver 11 being exported and second clock driver 12 are exported is carried out abnormality detection, and detecting that the clock signal that the first clock driver 11 is exported occurs abnormal, and the clock signal that second clock driver 12 is exported is when normal, control logic commutation circuit 14 is switched the first clock driver 11 and second clock driver 12, so that second clock driver 12 provides clock signal by logic commutation circuit 14 to exchange chip.
Optionally, between logic control element 13 and memory 15, can use I2C bus to communicate.
Optionally, logic control element 13 can, to the 14 output switching instructions of logic commutation circuit, switch the first clock driver 11 and second clock driver 12 with control logic commutation circuit 14.
From above-mentioned, logic commutation circuit 14 is mainly under the control of logic control element 13, and responsible selection inputs to the clock signal of exchange chip.Logic commutation circuit 14 can occur when abnormal, to complete rapidly the switching of two-way clock signal under the control of logic control element 13 in the current clock signal that inputs to exchange chip, ensures that to greatest extent the business of exchange chip is unaffected.In specific implementation, logic commutation circuit 14 can be used the various ripe chips that take over seamlessly that can realize clock signal in prior art, can also use simple and lower-cost switching circuit, can also carry out adaptability design according to the function of logic commutation circuit 14 in the present embodiment by Hardware Engineer.
From above-mentioned, the first clock driver 11 and second clock driver 12 are mainly used in the output in the first clock source and second clock source to be divided into two-way, and a road offers logic commutation circuit 14, one tunnels and offers logic control element 13.In specific implementation, the first clock driver 11 and second clock driver 12 can be the clock drivers that the chip manufacturing process of various employing standards is produced, have advantages of that stability is higher, failure rate is lower, and then improve the reliability of the clock detection circuit of the present embodiment.
The logic control element 13 of the present embodiment can or be the realizations such as field programmable gate array (Field Programmable Gate Array, FPGA) by CPLD (Complex Programmable Logic Device, CPLD).Wherein, it is lower that CPLD realizes cost, is preferred version.
Preferably, logic control element 13 can use on clock detection circuit the devices such as existing CPLD to realize, and based on this, clock detection circuit need not increase additional circuit again, and it realizes simple in structure, is easy to realize, and realizes cost lower.
In specific implementation, memory 15 can be EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable Read-Only Memory, EEPROM), Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read-Only Memory, EPROM), programmable read only memory (Programmable Read-Only Memory, etc., but be not limited to this PROM).Wherein, EEPROM is preferred implementation.
Optionally, the clock detection circuit of the present embodiment can be the circuit with clock detection function of realizing on various line cards.Further alternative, logic control element 13 can use the CPLD device having existed on line card to realize.
From above-mentioned, the clock detection circuit of the present embodiment is divided into the clock signal in the first clock source and second clock source respectively two-way and is offered respectively logic control element and logic commutation circuit by two clock drivers, the configuration information that logic control element provides according to processor carries out abnormality detection to the clock signal of two clock driver outputs respectively, and when forward direction exchange chip, to provide the clock signal of the clock driver output of clock signal to occur abnormal detecting, and the clock signal of another clock driver output is when normal, control logic commutation circuit is switched two-way clock driver, making provides clock signal by another road clock driver to exchange chip, complete the switching of clock signal.In the present embodiment, in the situation that realizing clock signal redundancy, logic control element uses configuration information to carry out abnormality detection to clock signal, no longer as prior art, the clock signal with clock source output counts to detect the abnormal of clock signal to high frequency clock, no longer need the clock signal of higher frequency, overcome and used high-frequency signal to detect the defect that low frequency signal exists.In addition, the clock detection circuit providing due to the present embodiment does not re-use high-frequency signal, makes to carry out abnormality detection to the clock signal of any frequency, is no longer subject to the restriction of the clock signal frequency that clock source provides, and range of application is wider.
The structural representation of the clock detection circuit that Fig. 2 provides for another embodiment of the present invention.The present embodiment is based on realization embodiment illustrated in fig. 1.As shown in Figure 2, the clock detection circuit of the present embodiment also comprises: processor 17.
Processor 17, is connected with memory 15 by logic control element 13, for writing above-mentioned configuration information to memory 15.
The processor 17 of the present embodiment can be the CPU (Central Processing Unit, CPU) on clock detection circuit.
Wherein, processor 17 can carry out information interaction by local bus (LOCAL BUS) andlogic control unit 13, is conducive to improve the speed of information interaction.
Further, the clock detection circuit of the present embodiment can also comprise: exchange chip 16.Exchange chip 16 can be MAC chip and/or the PHY chip on the clock detection circuit that provides of the present embodiment, but is not limited to this.
In clock redundant technique, modal clock failure has 2 kinds: the abnormal saltus step of clock failure of oscillation and clock.Wherein, the abnormal saltus step of clock comprises: clock saltus step accelerates, converts and several situations of not saltus step.For above-mentioned two kinds of clock failures, the present embodiment provides fast detecting pattern and slow detection pattern, can detect the situation of clock failure of oscillation by fast detecting module, can detect the situation of the abnormal saltus step of clock by slow detection pattern.
Based on above-mentioned two kinds of detecting patterns, the configuration information of the present embodiment can comprise: the first detection time, the second detection time and the several parameters of count threshold.Wherein, the first detection time, for carrying out fast detecting for logic control element 13, be greater than the cycle of the clock signal that the first clock driver 11 or second clock driver 12 export the first detection time.Suppose, the cycle of the clock signal that the first clock driver 11 or second clock driver 12 are exported is T, first detection time T1 meet: T1>T, comparatively preferably can select T1=1.5T, but be not limited to this.Wherein, the second detection time and count threshold, for carrying out slow detection for logic control element 13, be greater than the cycle of the clock signal that the first clock driver 11 or second clock driver 12 export the second detection time, be specially the product in the cycle of the clock signal that above-mentioned count threshold and the first clock driver 11 or second clock driver 12 export.Comparatively preferred, second detection time T2 be generally tens or a hundreds of T.
Based on above-mentioned, taking memory 15 as EEPROM as example, table 1 has provided the meaning of each configuration byte of EEPROM interior volume, can configure respectively different configuration informations to the clock signal of different frequency, also can configure identical configuration information to the clock signal of all frequencies.Whether the flag of EEPROM space beginning is used for identifying EEPROM the programming of carrying out, and is the configuration information of the clock signal configuration to two kinds of frequencies below.As shown in table 1, the clock signal that is 25MHz for frequency, has configured respectively the second detection time under the first detection time, the slow detection pattern under fast detecting pattern and the count threshold under slow detection pattern; The clock signal that is 125MHz for frequency, has configured respectively the second detection time under the first detection time, the slow detection pattern under fast detecting pattern and the count threshold under slow detection pattern.Here be not all example with the configuration information of the clock signal of different frequency.If the clock signal of different frequency is used identical configuration information, clock frequency can be distinguished in EEPROM space in specific implementation.
Table 1
| Flag |
| 25MHz clock signal |
| The first detection time under fast detecting pattern |
| The second detection time under slow detection pattern |
| Count threshold under slow detection pattern |
| 125MHz clock signal |
| The first detection time under fast detecting pattern |
| The second detection time under slow detection pattern |
| Count threshold under slow detection pattern |
| ...... |
Based on above-mentioned, logic control element 13 is according to configuration information, the clock signal that the clock signal of respectively the first clock driver 11 being exported and second clock driver 12 are exported is carried out abnormality detection and is specially: logic control element 13 is counted specifically for the clock signal of within the first detection time and in the second detection time, the first clock driver 11 being exported respectively, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal that the first clock driver 11 is exported occurs abnormal; And the clock signal that logic control element 13 is also exported second clock driver 12 within the first detection time and in the second detection time is counted, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal that second clock driver 12 is exported occurs abnormal.
Accordingly, if the count value within the first detection time is not 0, and count value within the second detection time equals count threshold, illustrates that the clock signal that clock signal that the first clock driver 11 is exported or second clock driver 12 export is normal.
In this explanation, the process that the clock signal that the process that the process that the clock signal that logic control element 13 is exported the first clock driver 11 within the first detection time detects, process that the clock signal that logic control element 13 is exported the first clock driver 11 within the second detection time detects, the clock signal that logic control element 13 is exported second clock driver 12 within the first detection time detect and logic control element 13 are exported second clock driver 12 within the second detection time detects can be carried out with random order.Illustrate, logic control element 13 can arrange four passages simultaneously, the clock signal that the clock signal of within the first detection time, the first clock driver 11 being exported and second clock driver 12 are exported simultaneously detects, and the clock signal that the clock signal of meanwhile simultaneously the first clock driver 11 being exported within the second detection time and second clock driver 12 are exported detects.Or, logic control element 13 arranges two passages, the clock signal that the clock signal of first simultaneously the first clock driver 11 being exported within the first detection time and second clock driver 12 are exported detects, and then the clock signal that the clock signal of simultaneously the first clock driver 11 being exported within the second detection time and second clock driver 12 are exported detects.Or, logic control element 13 arranges two passages, first the clock signal of simultaneously the first clock driver 11 being exported within the first detection time and in the second detection time detects, and then the clock signal of simultaneously second clock driver 12 being exported within the first detection time and in the second detection time detects.
Wherein, the testing result of logic control element 13 has following several situation:
The first situation, the clock signal that the first clock driver 11 is exported is normal, and the clock signal that second clock driver 12 is exported is normal.In this case, logic control element 13 does not send switching command to logic commutation circuit 14, still provides clock signal by logic commutation circuit 14 to exchange chip 16 by the first clock driver 11.
The second situation: the clock signal that the first clock driver 11 is exported is normal, and the clock signal that second clock driver 12 is exported is abnormal.In this case, logic control element 13 does not send switching command to logic commutation circuit 14, still provides clock signal by logic commutation circuit 14 to exchange chip 16 by the first clock driver 11.
The third situation: the clock signal that the first clock driver 11 is exported is abnormal, and the clock signal that second clock driver 12 is exported is normal.In this case, logic control element 13 sends switching command to logic commutation circuit 14, provides clock signal by second clock driver 12 by logic commutation circuit 14 to exchange chip 16.
The 4th kind of situation: the clock signal that the first clock driver 11 is exported is abnormal, and the clock signal that second clock driver 12 is exported is abnormal.
Optionally, logic control element 13 can write above-mentioned various testing results the relevant position of logic control element 13, so that inquiry or the use etc. of testing result.
Further, logic control element 13 is to detect that clock signal that the first clock driver 11 is exported occurs abnormal, or the clock signal exported of second clock driver 12 occurs when abnormal, can export interrupt signal to processor 17.Accordingly, processor 17, according to interrupt signal, reads the also current detection result of stored logic control unit 13, and to outside output alarm information.Preferably, processor 17 can be by the current detection result store of the logic control element obtaining 13 in memory 15, but is not limited to this.Wherein, processor 17 obtains the also testing result of stored logic control unit 13, is conducive to for the follow-up fault tracing that carries out.Wherein, processor 17 is conducive to external staff to outside output alarm information and knows in time have clock signal to occur extremely, so that carry out in time malfunction elimination.
Wherein, processor 17 can be automatic printing test results report to the mode of outside output alarm information, can be also to send alarm sound etc.
Optionally, before logic control element 13 is exported interrupt signal to processor 17, this testing result and last testing result can be compared, judge that whether twice testing result be identical, if comparative result is identical, do not export interrupt signal to processor 17, if comparative result is different, export interrupt signal to processor 17.Can avoid like this logic control element 13 to repeat to export interrupt signal to processor 17, avoid processor 17 repeated obtains and store same detection result, be conducive to alleviate the processing load of logic control element 13 and processor 17.
In this explanation, the clock signal of exporting when the first clock driver 11 occurs abnormal, and provided after clock signal to exchange chip 16 by second clock driver 12, the clock signal that can export the first clock driver 11 is carried out malfunction elimination, for example, may replace or proofread and correct the first clock source etc.After recovering clock signals that the first clock driver 11 is exported is normal, can again replace with by the first clock driver 11 and provide clock signal to exchange chip 16, also can not replace still and provide clock signal by second clock driver 12 to exchange chip 16.
Further illustrate, the clock signal of exporting when second clock driver 12 occurs abnormal, and the recovering clock signals that the first clock driver 11 is exported normal after, logic control element 13 can, by sending switching command to logic commutation circuit 14, will provide clock signal to replace with by the first clock driver 11 to exchange chip 16 by second clock drive circuit 12 and provide clock signal to exchange chip 16.
From above-mentioned, the clock detection circuit that the present embodiment provides, carry out the abnormal detection of clock by logic control element according to configuration information, processor only need write configuration information, obtains and store testing result output alarm information to memory, does not need to take a large amount of cpu resources of clock detection circuit; In addition, carry out clock abnormality detection by configuration information, no longer need the reference clock of higher frequency, be no longer subject to the restriction of clock frequency to be detected; In addition, logic control element can detect various clock failures by fast detecting and slow detection, and control logic commutation circuit completes the switching of clock signal, can ensure to greatest extent that the business of exchange chip is not interrupted; Moreover the clock detection circuit that the present embodiment provides mainly can be realized by CPLD, the portability of hardware system is stronger, and user can, by write different configuration informations in memory, can realize the clock signal of different frequency is carried out to abnormality detection.
The structural representation of the clock circuit that Fig. 3 provides for one embodiment of the invention.As shown in Figure 3, the clock circuit of the present embodiment comprises: clock detection circuit 10, the first clock source 20 and second clock source 30.
Wherein, the structure of clock detection circuit 10 and operation principle can, referring to Fig. 1 or description embodiment illustrated in fig. 2, not repeat them here.
The first clock source 20 and second clock source 30 can adopt clock platelet in specific implementation, and the first clock source 20 and second clock source 30 backup each other, and that is to say the clock signal that two clock sources provide identical.Described clock signal is identical refers to that the parameter (such as frequency, amplitude etc.) of clock signal is identical.
The frequency of the clock signal that in the present embodiment, the first clock source 20 and second clock source 30 provide does not limit.
Further, as shown in Figure 3, the clock circuit of the present embodiment also comprises backboard 40.
Concrete, the first clock driver 11 of clock detection circuit 10 is connected with the first clock source 20 by backboard 40, and the second clock driver 12 of clock detection circuit 10 is connected with second clock source 30 by backboard 40.
From above-mentioned, the clock circuit of the present embodiment comprises the clock detection circuit that the embodiment of the present invention provides, in the situation that realizing clock signal redundancy, logic control element uses configuration information to carry out abnormality detection to clock signal, no longer as prior art, the clock signal with clock source output counts to detect the abnormal of clock signal to high frequency clock, no longer need the clock signal of higher frequency, overcome and used high-frequency signal to detect the defect that low frequency signal exists.In addition, because the clock detection circuit in the present embodiment does not re-use high-frequency signal, make to carry out abnormality detection to the clock signal of any frequency, be no longer subject to the restriction of the clock signal frequency that clock source provides, range of application is wider.
The flow chart of the clock method for detecting abnormality that Fig. 4 A provides for one embodiment of the invention.As shown in Figure 4 A, the method for the present embodiment comprises:
Step 41, obtain detect clock signal use configuration information.
The clock signal of step 42, the clock signal of respectively the first clock driver being exported according to configuration information and the output of second clock driver is carried out abnormality detection; Wherein, described the first clock source is for providing clock signal to exchange chip.
Know that the clock signal of the first clock driver output occurs extremely if step 43 detects, and the clock signal of second clock driver output is normal, switches the first clock source and second clock source, so that second clock source provides clock signal to exchange chip.
In an optional execution mode of the present embodiment, described configuration information comprises: the first detection time, the second detection time and count threshold, be greater than the cycle of the clock signal of the first clock driver or the output of second clock driver the first detection time, be the product in the cycle of the clock signal of count threshold and the first clock driver or the output of second clock driver the second detection time.
Based on above-mentioned optional execution mode, a kind of embodiment of step 42 comprises: within the first detection time and in the second detection time, the clock signal of the first clock driver output is counted respectively, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal of the first clock driver output occurs abnormal; Within the first detection time and in the second detection time, the clock signal of second clock driver output is counted respectively, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal of second clock driver output occurs abnormal.
In an optional execution mode of the present embodiment, when the clock signal of the first clock driver output or the clock signal of second clock driver output occur when abnormal, to outside output alarm information.
Optionally, the executive agent of the present embodiment can be the logic control element in clock detection circuit, but is not limited to this, all right other modules or unit, such as CPU etc.
The clock method for detecting abnormality that the present embodiment provides, by obtaining the configuration information that carries out the use of clock abnormality detection, then respectively the clock signal of two clock driver outputs is carried out to abnormality detection according to described configuration information, and when forward direction exchange chip, to provide the clock signal of the clock driver output of clock signal to occur abnormal detecting, and the clock signal of another clock driver output is when normal, control and provide clock signal by another road clock driver to exchange chip, complete the switching of clock signal, in the situation that realizing clock signal redundancy, use configuration information to carry out abnormality detection to clock signal, no longer as prior art, the clock signal with clock source output counts to detect the abnormal of clock signal to high frequency clock, no longer need the clock signal of higher frequency, overcome and used high-frequency signal to detect the defect that low frequency signal exists.In addition, due to the method that the present embodiment provides, do not re-use the clock signal of higher frequency, make to carry out abnormality detection to the clock signal of any frequency, be no longer subject to the restriction of the clock signal frequency that clock source provides, range of application is wider.
The clock detection circuit providing below in conjunction with the above embodiment of the present invention and clock circuit, detailed description logic control element carries out the flow process of clock abnormality detection.
The flow chart of the clock method for detecting abnormality that Fig. 4 B provides for another embodiment of the present invention.As shown in Figure 4 B, the method for the present embodiment comprises:
The logic control element of step 401, clock detection circuit obtains and detects the configuration information that clock signal is used from the memory of clock detection circuit.
The clock signal that step 402, described logic control element are exported first clock signal of clock driver output and the second clock driver of clock detection circuit of clock detection circuit respectively according to described configuration information is carried out abnormality detection.
Wherein, the first clock driver is connected with the logic commutation circuit of the first clock source and clock detection circuit, for providing clock signal by logic commutation circuit to the exchange chip of clock detection circuit.Second clock driver is connected with second clock source and logic commutation circuit, when abnormal, provides clock signal by logic commutation circuit for occurring in the clock signal of the first clock driver output to exchange chip.Logic commutation circuit is connected with exchange chip.
Step 403, abnormal when detecting that the clock signal of the first clock driver output occurs, and when the clock signal of second clock signal output is normal, logic control element control logic commutation circuit is switched the first clock driver and second clock driver, so that second clock driver provides clock signal by logic commutation circuit to exchange chip.
In an optional execution mode of the present embodiment, before step 401, can comprise: the processor of clock detection circuit writes above-mentioned configuration information in the memory of clock detection circuit.
In an optional execution mode of the present embodiment, described configuration information comprises: the first detection time, the second detection time and count threshold, be greater than the cycle of clock signal the first clock driver output or the output of second clock driver described the first detection time, be the product in the cycle of clock signal count threshold and the output of the first clock driver or the output of second clock driver described the second detection time.
Based on above-mentioned.The optional execution mode of one of step 402 comprises:
Step 4021, logic control element are counted the clock signal of the first clock driver output within the first detection time and in the second detection time respectively, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal of the first clock driver output occurs abnormal.
Step 4022, logic control element are counted the clock signal of second clock driver output within the first detection time and in the second detection time respectively, if the count value within the first detection time is 0, or the count value within the second detection time is not equal to count threshold, judge that the clock signal of second clock driver output occurs abnormal.
As shown in Figure 5, the process that logic control element carries out fast detecting to the clock signal of the first clock driver or second clock driver output within the first detection time comprises:
Step 501, logic control element are by counter O reset.
Step 502, logic control element are counted the clock signal of the first clock driver or the output of second clock driver within the first detection time.
Step 503, logic control element judge whether the count value within the first detection time is 0; When judged result is when being, execution step 504; When judged result is while being no, execution step 505.
Step 504, logic control element judge that the clock signal of the first clock driver or the output of second clock driver occurs abnormal.
Step 505, logic control element judge that the clock signal of the first clock driver or the output of second clock driver is normal.
As shown in Figure 6, the process that logic control element carries out slow detection to the clock signal of the first clock driver or second clock driver output within the second detection time comprises:
Step 601, logic control element are by counter O reset.
Step 602, logic control element are counted the clock signal of the first clock driver or the output of second clock driver within the second detection time.
Step 603, logic control element judge whether the count value within the second detection time equals the count threshold in configuration information; When judged result is while being no, execution step 604; When judged result is when being, execution step 605.
Step 604, logic control element judge that the clock signal of the first clock driver or the output of second clock driver occurs abnormal.
Step 605, logic control element judge that the clock signal of the first clock driver or the output of second clock driver is normal.
In the clock method for detecting abnormality providing at above-described embodiment, clock detection circuit is divided into the clock signal in the first clock source and second clock source respectively two-way and is offered respectively logic control element and logic commutation circuit by two clock drivers, the configuration information that logic control element provides according to processor carries out abnormality detection to the clock signal of two clock driver outputs respectively, and when forward direction exchange chip, to provide the clock signal of the clock driver output of clock signal to occur abnormal detecting, and the clock signal of another clock driver output is when normal, control logic commutation circuit is switched two-way clock driver, making provides clock signal by another road clock driver to exchange chip, complete the switching of clock signal, in the situation that realizing clock signal redundancy, logic control element uses configuration information to carry out abnormality detection to clock signal, no longer as prior art, the clock signal with clock source output counts to detect the abnormal of clock signal to high frequency clock, no longer need the clock signal of higher frequency, overcome and used high-frequency signal to detect the defect that low frequency signal exists.In addition, due in the above-described embodiments, clock detection circuit does not re-use the clock signal of higher frequency, makes to carry out abnormality detection to the clock signal of any frequency, is no longer subject to the restriction of the clock signal frequency that clock source provides, and range of application is wider.
The flow chart of the clock method for detecting abnormality that Fig. 7 provides for further embodiment of this invention.The present embodiment is realized based on Fig. 4 B illustrated embodiment.As shown in Figure 7, the method for the present embodiment also comprises after step 403:
Step 404, logic control element occur when abnormal in the clock signal of the first clock driver output or the clock signal of second clock driver output, to processor output interrupt signal.
Step 405, processor, according to above-mentioned interrupt signal, read the also current detection result of stored logic control unit, and to outside output alarm information.
Optionally, before step 404, logic control element can compare this testing result and last testing result, judge that whether twice testing result be identical, if comparative result is identical, not to processor output interrupt signal, if comparative result is different, to processor output interrupt signal.Can avoid like this logic control element to repeat, to processor output interrupt signal, avoid processor repeated obtain and store same detection result, be conducive to alleviate the processing load of logic control element and processor.
In the present embodiment, detecting that when abnormal, logic control element is exported interrupt signal to processor, makes processor according to interrupt signal, obtain and the current detection result of stored logic control unit, be conducive to for the follow-up fault tracing that carries out; In addition, processor is conducive to external staff to outside output alarm information and knows in time have clock signal to occur extremely, so that carry out in time malfunction elimination.
Ethernet mainly contains 25MHz, 125MHz, the equifrequent clock of 156.25MHz at present.Be example below taking clock frequency to be detected as 5MHz, line card taking clock detection circuit in Ethernet, CPLD taking logic control element on line card, the EEPROM taking memory on line card, CPU taking processor on line card are example, and the workflow of clock detection circuit is described.Specific as follows:
First, line card resets, and acquiescence adopts the first clock source to provide clock signal to the exchange chip on line card.
Secondly, CPLD reads the configuration in EEPROM, and first CPLD reads 2 bytes in EEPROM space.
If the value reading is 0xFF, judging EEPROM does not have normal programming, and CPLD does not make any handover operation.Now, can start CPU EEPROM is carried out to programming, write configuration information.
For example, if the value reading is default programming value (0x10), read the configuration information in EEPROM.In this enforcement, the prior good configuration information for different clock frequencies of programming in EEPROM.Because the present embodiment describes as an example of the clock signal of 125MHz example, based on this, CPLD selects Configuration Values corresponding to the clock signal of 125MHz from EEPROM, supposes that the result of selecting is to be the first detection time 15ns, be 12us the second detection time, and count threshold is 1500.
Then, CPLD reads after the configuration information in EEPROM, respectively the clock signal of two-way 125MHz is detected according to configuration information.Wherein, the testing process of Dui Mei road signal comprises:
(1) fast detecting pattern, referring to Fig. 8, owing to being the first detection time 15ns, the rising edge of CPLD clock signal to 125MHz in the timing time of 15ns is counted, and at least can count 1 count value.If be 0 in 15ns inside counting value, judge that failure of oscillation may occur clock.
(2) slow detection pattern, referring to Fig. 9, owing to being the second detection time 12us, the rising edge of CPLD clock signal of 125MHz within the time of 12us is counted, and can obtain out in theory 1500 count values.If actual count value and count threshold are inconsistent, judge that abnormal saltus step has appearred in clock.In this explanation, count threshold can be configured by EEPROM, can be determined value, also can be configured to a scope.
Then, according to detection case, produce following 4 kinds of test results, line card is taked corresponding counter-measure.
1) clock signal that the first clock source provides is normal, and the clock signal that second clock source provides is normal, and CPLD maintains and adopts the first clock source to provide clock signal to exchange chip.
2) clock signal that the first clock source provides is normal, the clock signal that second clock source provides is abnormal, CPLD output interrupt signal notice CPU, CPU reads the clock abnormal information that CPLD obtains, print out corresponding warning message, and clock abnormal information is stored in EEPROM, recall for follow-up.If fault is not got rid of always, CPLD continues to detect same clock abnormal information, no longer exports interrupt signal to CPU, and CPU is not Reduplicated writes EEPROM by same clock abnormal information.
3) clock signal that the first clock source provides is abnormal, and the clock signal that second clock source provides is normal, and the logic commutation circuit on CPLD control line card completes rapidly the switching of two-way clock signal, ensures that to greatest extent the business of exchange chip is unaffected.Meanwhile, CPLD output interrupt signal notice CPU, CPU reads the clock abnormal information that CPLD obtains, and prints and exports corresponding warning message, and clock abnormal information is stored in EEPROM, recalls for follow-up.If fault is not got rid of always, CPLD continues same clock abnormal information to be detected, no longer exports interrupt signal to CPU, and CPU is not Reduplicated writes EEPROM by same clock abnormal information.
4) clock signal that the first clock source provides is abnormal, the clock signal that second clock source provides is abnormal, CPLD output interrupt signal notice CPU, CPU reads CPLD and obtains clock abnormal information, print and export corresponding warning message, and clock abnormal information is stored in EEPROM, recall for follow-up.If fault is not got rid of always, CPLD continues same clock abnormal information to be detected, no longer exports interrupt signal to CPU, and CPU is not Reduplicated writes EEPROM by same clock abnormal information.
The present embodiment has following beneficial effect: 1, hardware circuit only need to utilize the device such as original CPU and CPLD on line card to realize.CPU only need to report to the police or empty EEPROM is carried out to programming in the time that clock signal is abnormal, and remaining work is completed by CPLD completely, does not take a large amount of cpu resources.2, can make detection to situations such as clock failure of oscillation and the abnormal saltus steps of clock, can be very fast on hardware make switching, ensure that the normal business of line card is unaffected.3, hardware system is portable strong, and user can carry out flexible configuration according to actual needs by programming EEPROM.4, do not need the clock of higher frequency, overcome the defect while using higher frequency clock to carry out abnormality detection to low frequency clock.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each embodiment of the method can complete by the relevant hardware of program command.Aforesaid program can be stored in a computer read/write memory medium.This program, in the time carrying out, is carried out the step that comprises above-mentioned each embodiment of the method; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.
Finally it should be noted that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these amendments or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a clock detection circuit, is characterized in that, comprising: the first clock driver, second clock driver, logic control element, logic commutation circuit and memory;
Described the first clock driver is connected with the first clock source and described logic commutation circuit, for providing clock signal by described logic commutation circuit to exchange chip; Described second clock driver is connected with second clock source and described logic commutation circuit, and described logic commutation circuit is connected with described exchange chip;
Described memory, the configuration information using for being stored into row clock input;
Described logic control element is connected with described memory, described the first clock driver, described second clock driver and described logic commutation circuit, for obtaining described configuration information from described memory, the clock signal of the clock signal of respectively described the first clock driver being exported according to described configuration information and the output of described second clock driver is carried out abnormality detection; And occur abnormal in the clock signal that described the first clock driver output detected, and when the clock signal of described second clock source output is normal, control described logic commutation circuit and switch described the first clock driver and described second clock driver, so that described second clock driver provides clock signal by described logic commutation circuit to described exchange chip;
Described configuration information comprises: the first detection time, the second detection time and count threshold, be greater than the cycle of the clock signal of described the first clock driver or the output of described second clock driver described the first detection time, be the product in the cycle of the clock signal of described count threshold and described the first clock driver or the output of described second clock driver described the second detection time;
Described logic control element is specifically for counting the clock signal of described the first clock driver output within described the first detection time and in described the second detection time respectively, if the count value within described the first detection time is 0, or the count value within described the second detection time is not equal to described count threshold, the clock signal of judging described the first clock driver output occurs abnormal, and within described the first detection time and in described the second detection time, the clock signal of described second clock driver output is counted, if the count value within described the first detection time is 0, or the count value within described the second detection time is not equal to described count threshold, the clock signal of judging described second clock driver output occurs abnormal.
2. clock detection circuit according to claim 1, is characterized in that, also comprises:
Processor, is connected with described memory by described logic control element, for writing described configuration information to described memory.
3. clock detection circuit according to claim 2, it is characterized in that, described logic control element is also for occurring in the clock signal of described the first clock driver output or the clock signal of described second clock driver output when abnormal, to described processor output interrupt signal;
Described processor also, for according to described interrupt signal, reads and stores the current detection result of described logic control element, and to outside output alarm information.
4. clock detection circuit according to claim 1, is characterized in that, also comprises: described exchange chip.
5. a clock method for detecting abnormality, is characterized in that, comprising:
Obtain and detect the configuration information that clock signal is used;
The clock signal of the clock signal of respectively the first clock driver being exported according to described configuration information and the output of second clock driver is carried out abnormality detection; Wherein, described the first clock source is for providing clock signal to exchange chip;
The clock signal of knowing described the first clock driver output if detect occurs abnormal, and the clock signal of described second clock driver output is normal, switch described the first clock source and described second clock source, so that described second clock source provides clock signal to described exchange chip;
Described configuration information comprises: the first detection time, the second detection time and count threshold, be greater than the cycle of the clock signal of described the first clock driver or the output of described second clock driver described the first detection time, be the product in the cycle of the clock signal of described count threshold and described the first clock driver or the output of described second clock driver described the second detection time;
The clock signal of the described clock signal of respectively the first clock driver being exported according to described configuration information and the output of second clock driver is carried out abnormality detection and is comprised:
Within described the first detection time and in described the second detection time, the clock signal of described the first clock driver output is counted respectively, if the count value within described the first detection time is 0, or the count value within described the second detection time is not equal to described count threshold, judge that the clock signal of described the first clock driver output occurs abnormal;
Within described the first detection time and in described the second detection time, the clock signal of described second clock driver output is counted respectively, if the count value within described the first detection time is 0, or the count value within described the second detection time is not equal to described count threshold, judge that the clock signal of described second clock driver output occurs abnormal.
6. clock method for detecting abnormality according to claim 5, is characterized in that, also comprises:
When the clock signal of described the first clock driver output or the clock signal of described second clock driver output occur when abnormal, to outside output alarm information.
7. a clock circuit, is characterized in that, comprising: clock detection circuit, the first clock source and second clock source described in claim 1-4 any one.
8. clock circuit according to claim 7, is characterized in that, also comprises: backboard;
The first clock driver of described clock detection circuit is connected with described the first clock source by described backboard; The second clock driver of described clock detection circuit is connected with described second clock source by described backboard.
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| CN104267638B (en) * | 2014-09-19 | 2017-01-25 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN104777378A (en) * | 2015-03-09 | 2015-07-15 | 国核自仪系统工程有限公司 | FPGA clock signal self-detecting method |
| CN106066817B (en) * | 2016-05-30 | 2023-04-07 | 珠海市一微半导体有限公司 | Clock monitoring circuit and method thereof |
| CN106226724B (en) * | 2016-08-03 | 2018-10-02 | 宁波三星医疗电气股份有限公司 | A kind of clock of power meter method for detecting abnormality |
| CN108931696B (en) * | 2017-05-25 | 2021-06-29 | 许继集团有限公司 | B-code clock abnormity detection method of intelligent substation and relay protection device |
| US10795783B2 (en) * | 2017-10-16 | 2020-10-06 | Microchip Technology Incorporated | Fault tolerant clock monitor system |
| CN110308765A (en) * | 2019-06-28 | 2019-10-08 | 苏州浪潮智能科技有限公司 | A kind of server clock signal monitoring system and monitoring method |
| CN110277065B (en) * | 2019-07-11 | 2020-09-01 | 武汉京东方光电科技有限公司 | Gate driving unit and driving method thereof, gate driving circuit and display panel |
| CN111400087B (en) * | 2020-02-26 | 2023-08-11 | 深圳震有科技股份有限公司 | Control method of operating system, terminal and storage medium |
| CN113448381B (en) * | 2021-05-28 | 2023-02-28 | 山东英信计算机技术有限公司 | CPLD working clock keeping method, system, storage medium and device |
| CN114261354B (en) * | 2021-12-24 | 2023-07-04 | 南京英锐创电子科技有限公司 | Low frequency clock circuit and control method |
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Address after: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee after: RUIJIE NETWORKS Co.,Ltd. Address before: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee before: Beijing Star-Net Ruijie Networks Co.,Ltd. |