CN110308765A - A kind of server clock signal monitoring system and monitoring method - Google Patents
A kind of server clock signal monitoring system and monitoring method Download PDFInfo
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- CN110308765A CN110308765A CN201910572310.3A CN201910572310A CN110308765A CN 110308765 A CN110308765 A CN 110308765A CN 201910572310 A CN201910572310 A CN 201910572310A CN 110308765 A CN110308765 A CN 110308765A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/325—Display of status information by lamps or LED's
- G06F11/326—Display of status information by lamps or LED's for error or online/offline status
Abstract
The present invention relates to server technology field, providing a kind of server clock signal monitoring system and monitoring method, monitoring system includes general topological clock circuit, crystal, clock signal exception monitoring circuit and alarm lamp；Crystal is used to generate the second clock signal an of fixed frequency, and is delivered to clock signal exception monitoring circuit for second clock signal as the input signal of clock signal exception monitoring circuit；Clock signal exception monitoring circuit obtains the first clock signal and second clock signal respectively, and judge the first clock signal and second clock signal with the presence or absence of abnormal, when there is one to break down in the first clock signal and second clock signal, alarm signal is then generated, while the alarm signal of generation is delivered to the alarm lamp；According to the alarm signal of the clock signal exception monitoring circuit output, alarm lamp execution light movement, thus realize quickly positioning as system clock exception and caused by server failure problem.
Description
Technical field
The invention belongs to server technology field more particularly to a kind of server clock signal monitoring system and monitoring sides
Method.
Background technique
Clock system plays decisive role for server stable operation.CPU, PCH, BMC on server master board,
CPLD and various PCIE devices etc. are worked under the control of external system clock, the sequential operation each time of each chip interior
It is all to be triggered under the action of clock, therefore server system is very high for the required precision of clock.If system clock occurs
Abnormal, the function of respective chip will be severely impacted, or even will cause the failure of complete machine delay machine.At present on server master board
The clock of core devices such as CPU and various PCIE devices etc. is generated by quartz crystal, by one or more levels Clock
Buffer is connected to chip.During server long-play, it is possible that quartz crystal and Clock Buffer core
Piece failure or as clock chip pin rosin joint and caused by clock abnormal conditions, cause back-end chip that cannot work.
Currently, in server system, the clock of CPU and various PCIE devices etc. is generated by quartz crystal/crystal oscillator, by south
To each terminal chip, which is an open loop system for distribution after bridge and one or more levels Clock Buffer are expanded
System, the monitoring and feedback to clock quality are lacked between crystal to chip, if in system operation due to crystal,
Clock Buffer, circuit board trace etc. break down and cause clock abnormal, and server master board and background monitoring system are not
It will appear warning mark, chip failure in this case is difficult where quick positioning question, needs engineer's field adjustable point
Analysis, causes difficulty to the maintenance of server.
Summary of the invention
For the defects in the prior art, the present invention provides a kind of server clock signal monitoring systems, it is intended to solve
Lack the monitoring and feedback to clock quality between crystal to chip in the prior art, chip failure is difficult quick positioning question
Place needs engineer's field adjustable to analyze, and difficult problem is caused to the maintenance of server.
The technical solution provided by the present invention is: a kind of server clock signal monitoring system, including general topological clock
Circuit, it is corresponding per the connection of the first clock signal all the way if the general topological clock circuit exports the first clock signal of main line
Terminal device device, the server clock signal monitoring system further include crystal, clock signal exception monitoring circuit and report
Alert indicator light；
The crystal is believed for generating the second clock signal an of fixed frequency, and by the second clock of generation
Number the clock signal exception monitoring circuit is delivered to as the input signal of the clock signal exception monitoring circuit；
The clock signal exception monitoring circuit is connect, for dividing respectively with the crystal and general topological clock circuit
First clock signal and second clock signal are not obtained, and judge whether are first clock signal and second clock signal
There are exceptions then to generate alarm signal, together when there is one to break down in first clock signal and second clock signal
When the alarm signal of generation is delivered to the alarm lamp；
The alarm lamp, for the alarm signal according to the clock signal exception monitoring circuit output, execution point
Bright movement.
As an improvement scheme, the general topological clock circuit includes crystal oscillator, South Bridge chip and clock buffer；
The crystal oscillator is connect with South Bridge chip signal, and the South Bridge chip is connect with the clock buffer signal.
As an improvement scheme, the clock signal exception monitoring circuit includes:
Clock edge detection circuit, for obtaining first clock signal from the clock buffer, from the crystal
The second clock signal is obtained, and uses first clock signal and the faster clock signal of second clock signal intermediate frequency rate
The slower clock signal of frequency is triggered, detection obtains the rising edge of the slower clock signal of frequency；
Rising edge clock counting circuit is connect with the clock edge detection circuit, for detecting when the clock edge
When circuit detects the rising edge of the slower clock signal of frequency, the rising edge of the faster clock signal of frequency is counted,
And when the clock edge detection circuit detects the rising edge of the slower clock signal of frequency again, stops counting, be denoted as
N；
Breakdown judge logic circuit is connect with the rising edge clock counting circuit, for judging the count value N and
Whether the frequency ratio M of one clock signal and second clock signal is equal, when N is equal with M, determines first clock signal
It is normal with second clock signal, when N and M are unequal, then determine that first clock signal and second clock signal have one
It is a to be in abnormality, then alarm signal is generated, while the alarm signal of generation is delivered to the alarm lamp.
As an improvement scheme, first clock signal from the idle pin of the clock buffer draw.
As an improvement scheme, first clock signal is from the clock buffer and the terminal device device
Between connection line on obtain.
As an improvement scheme, the clock signal exception monitoring circuit is built in Complex Programmable Logic Devices
In.
Another object of the present invention is to provide a kind of, and the server clock based on server clock signal monitoring system is believed
Number monitoring method, the method includes the following steps:
Crystal generates the second clock signal of a fixed frequency, and using the second clock signal of generation as described in
The input signal of clock signal exception monitoring circuit is delivered to the clock signal exception monitoring circuit；
Clock signal exception monitoring circuit obtains first clock signal and second clock signal respectively, and described in judgement
First clock signal and second clock signal are with the presence or absence of abnormal, when having one in first clock signal and second clock signal
It is a when breaking down, then alarm signal is generated, while the alarm signal of generation is delivered to the alarm lamp；
According to the alarm signal of the clock signal exception monitoring circuit output, movement is lighted in alarm lamp execution.
As an improvement scheme, the clock signal exception monitoring circuit obtain respectively first clock signal and
Second clock signal, and first clock signal and second clock signal are judged with the presence or absence of exception, when first clock
There is one in signal and second clock signal when breaking down, then generates alarm signal, while the alarm signal of generation being conveyed
The step of to the alarm lamp specifically include the following steps:
Clock edge detection circuit obtains first clock signal from the clock buffer, obtains institute from the crystal
Second clock signal is stated, and uses first clock signal and the faster clock signal triggering frequency of second clock signal intermediate frequency rate
The slower clock signal of rate, detection obtain the rising edge of the slower clock signal of frequency；
When the clock edge detection circuit detects the rising edge of the slower clock signal of frequency, rising edge clock meter
Number circuit counts the rising edge of the faster clock signal of frequency, and when the clock edge detection circuit detects again
When the rising edge of the slower clock signal of frequency, stops counting, be denoted as N；
Breakdown judge logic circuit judges the frequency ratio of the count value N and the first clock signal and second clock signal
Whether M is equal, when N is equal with M, determines that first clock signal and second clock signal are normal, when N is unequal with M
When, then determine that first clock signal and second clock signal have one in abnormality, then generates alarm signal, simultaneously
The alarm signal of generation is delivered to the alarm lamp.
In embodiments of the present invention, server clock signal monitoring system includes general topological clock circuit, crystal, clock
Abnormal signal observation circuit and alarm lamp；Crystal is used to generate the second clock signal an of fixed frequency, and by the
Two clock signals are delivered to clock signal exception monitoring circuit as the input signal of clock signal exception monitoring circuit；Clock letter
Number exception monitoring circuit obtains the first clock signal and second clock signal respectively, and judges the first clock signal and second clock
Signal when there is one to break down in the first clock signal and second clock signal, then generates alarm signal with the presence or absence of exception
Number, while the alarm signal of generation is delivered to the alarm lamp；According to the clock signal exception monitoring circuit output
Alarm signal, alarm lamp execution light movement, thus realize quickly positioning as system clock exception and caused by take
Business device failure problems.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described.In all the appended drawings, similar element
Or part is generally identified by similar appended drawing reference.In attached drawing, each element or part might not be drawn according to actual ratio.
Fig. 1 is the structural schematic diagram of server clock signal monitoring system provided by the invention；
Fig. 2 is the implementation flow chart of server clock signal monitoring method provided by the invention；
When Fig. 3 is that clock signal exception monitoring circuit provided by the invention obtains first clock signal and second respectively
Clock signal, and judge first clock signal and second clock signal with the presence or absence of abnormal, when first clock signal and
There is one in second clock signal when breaking down, then generate alarm signal, while the alarm signal of generation being delivered to described
The implementation flow chart of alarm lamp；
Wherein, the general topological clock circuit of 1-, 2- terminal device device, 3- crystal, 4- clock signal exception monitoring circuit,
5- alarm lamp, 6- crystal oscillator, 7- South Bridge chip, 8- clock buffer, 9- clock edge detection circuit, 10- rising edge clock
Counting circuit, 11- breakdown judge logic circuit.
Specific embodiment
It is described in detail below in conjunction with embodiment of the attached drawing to technical solution of the present invention.Following embodiment is only used for
Clearly illustrate of the invention, technical solution, therefore be only used as example, and cannot be used as a limitation and limit protection model of the invention
It encloses.
Fig. 1 shows the structural schematic diagram of server clock signal monitoring system provided by the invention, for ease of description,
Part related to the embodiment of the present invention is only gived in figure.
Server clock signal monitoring system includes general topological clock circuit 1, and the general topological clock circuit 1 exports
If the first clock signal of main line, corresponding terminal device device 2, the server clock letter are connected per the first clock signal all the way
Number monitoring system further includes crystal 3, clock signal exception monitoring circuit 4 and alarm lamp 5；
The crystal 3 is believed for generating the second clock signal an of fixed frequency, and by the second clock of generation
Number the clock signal exception monitoring circuit 4 is delivered to as the input signal of the clock signal exception monitoring circuit 4；
The clock signal exception monitoring circuit 4 connect with the crystal 3 and general topological clock circuit 1 respectively, is used for
First clock signal and second clock signal are obtained respectively, and judge first clock signal and second clock signal is
It is no to there is exception, when there is one to break down in first clock signal and second clock signal, then alarm signal is generated,
The alarm signal of generation is delivered to the alarm lamp 5 simultaneously；
The alarm lamp 5, the alarm signal for being exported according to the clock signal exception monitoring circuit 4 execute
Light movement.
In this embodiment, as shown in Figure 1, general topology clock circuit 1 includes crystal oscillator 6, South Bridge chip 7 and clock
buffer 8；The crystal oscillator 6 is connect with 7 signal of South Bridge chip, and the South Bridge chip 7 connects with 8 signal of clock buffer
It connects；
Wherein, the operational amplifier circuit in crystal oscillator 6 and South Bridge chip 7 has collectively constituted 3 electricity of crystal that can export fixed frequency
Road, the clock of the frequency will carry out frequency dividing or frequency multiplication in south bridge, generate the clock of more different frequencies.From South Bridge chip
One group of clock of 7 outputs is fanned out to clock beam CK1 (i.e. the first clock that more multiple groups have identical frequency after oversampling clock buffer 8
Signal), terminal device device 2 is ultimately connected to through each clock that clock buffer 8 is expanded out.
In embodiments of the present invention, as shown in Figure 1, the clock signal exception monitoring circuit 4 includes:
Clock edge detection circuit 9, for obtaining first clock signal from the clock buffer 8, from the crystalline substance
Body 3 obtains the second clock signal, and uses first clock signal and the faster clock of second clock signal intermediate frequency rate
Signal triggers the slower clock signal of frequency, and detection obtains the rising edge of the slower clock signal of frequency；
Rising edge clock counting circuit 10 is connect with the clock edge detection circuit 9, for examining when the clock edge
When slowdown monitoring circuit 9 detects the rising edge of the slower clock signal of frequency, the rising edge of the faster clock signal of frequency is counted
Number, and when the clock edge detection circuit 9 detects the rising edge of the slower clock signal of frequency again, stop counting,
It is denoted as N；
Breakdown judge logic circuit 11 is connect with the rising edge clock counting circuit 10, for judging the count value N
It is whether equal with the frequency ratio M of the first clock signal and second clock signal, when N is equal with M, determine first clock
Signal and second clock signal are normal, when N and M are unequal, then determine first clock signal and second clock signal
There is one in abnormality, then generates alarm signal, while the alarm signal of generation is delivered to the alarm lamp 5.
In this embodiment, the clock signal exception monitoring circuit 4 is built in Complex Programmable Logic Devices, by when
The clock that clock buffer 8 is exported accesses CPLD, and is compared with the clock of CPLD, passes through clock edge detection-clock count
The difference of two clocks is compared in equal logical operations, when exception occur in the clock of CPLD and the clock either side of clock buffer 8
When, it will triggering alarm, so as to quickly position as system clock is abnormal and caused by server failure problem.
As shown in Figure 1, the lead-out mode of first clock signal can there are many, what dotted line as shown in figure 1 indicated is two
Kind implementation, herein not to limit the present invention, specifically:
First clock signal is drawn from the idle pin of the clock buffer 8 or the first clock signal is from described
It is obtained in connection line between clock buffer 8 and the terminal device device 2.
As a specific embodiment of the invention, by taking rising edge samples as an example, clock edge detection circuit 9 is at first
When detecting the rising edge of second clock signal clock under clock signal function, it will triggering rising edge clock counting circuit 10 starts
The rising edge clock of first clock signal is counted, when clock edge sense circuit 9 detects second clock signal again
Rising edge when rising edge clock counting circuit 10 stop counting, save count value N, and start after accumulator register is reset new
The Edge check of one wheel and counting；
Breakdown judge logic circuit 11 judges whether count value N is equal to the frequency fCK1 and second clock of the first clock signal
The ratio M of the frequency fCK2 of signal, usual first clock signal and second clock signal have different clock frequencies, for
In the case that fCK1 is fCK2 integral multiple, frequency (period) ratio of the two should be equal in one clock cycle of second clock signal
The rising edge number of first clock signal.If the two is equal (M=N), prove that two clock signal inputs are normal, otherwise
(M ≠ N), it was demonstrated that at least one clock signal produces failure in the two, will light trouble lamp；
Such as: the frequency for wherein assuming the first clock signal exported in clock buffer 8 is fCK1=100MHz, the
The frequency of two clock signals is fCK2=25MHz, slower in the triggering of faster first clock signal of frequency sample frequency of going down
Second clock signal.Herein by taking rising edge samples as an example, when detecting second clock signal under the effect of the first clock signal
When the rising edge of clock, it will triggering starts to count the rising edge clock of the first clock signal, when detecting second again
Stop counting when the rising edge clock of clock signal, save count value N, and starts the side of a new round after accumulator register is reset
Along detection and count.
Judge whether count value N is equal to the ratio of the frequency fCK1 of the first clock signal and the frequency fCK2 of second clock signal
Value 4.If the equal i.e. N=4 of the two, proves that two clock signal inputs are normal, at least one clock signal in the two
Failure is produced, trouble lamp will be lighted.
On the basis of above-mentioned embodiment shown in FIG. 1, Fig. 2 shows server clock signal monitorings provided by the invention
The implementation flow chart of method, specifically include the following steps:
In step s101, crystal 3 generates the second clock signal of a fixed frequency, and when by described the second of generation
Clock signal is delivered to the clock signal exception monitoring circuit 4 as the input signal of the clock signal exception monitoring circuit 4；
In step s 102, clock signal exception monitoring circuit 4 obtains first clock signal and second clock respectively
Signal, and first clock signal and second clock signal are judged with the presence or absence of abnormal, when first clock signal and the
There is one in two clock signals when breaking down, then generates alarm signal, while the alarm signal of generation is delivered to the report
Alert indicator light 5；
In step s 103, the alarm signal exported according to the clock signal exception monitoring circuit 4, alarm lamp 5
Movement is lighted in execution.
As shown in figure 3, the clock signal exception monitoring circuit 4 obtains first clock signal and second clock respectively
Signal, and first clock signal and second clock signal are judged with the presence or absence of abnormal, when first clock signal and the
There is one in two clock signals when breaking down, then generates alarm signal, while the alarm signal of generation is delivered to the report
The step of alert indicator light 5 specifically include the following steps:
In step s 201, clock edge detection circuit 9 obtains first clock signal from the clock buffer 8,
Obtain the second clock signal from the crystal 3, and using first clock signal and second clock signal intermediate frequency rate compared with
The slower clock signal of fast clock signal triggering frequency, detection obtain the rising edge of the slower clock signal of frequency；
In step S202, when the clock edge detection circuit 9 detects the rising edge of the slower clock signal of frequency
When, rising edge clock counting circuit 10 counts the rising edge of the faster clock signal of frequency, and works as the clock edge
When detection circuit 9 detects the rising edge of the slower clock signal of frequency again, stops counting, be denoted as N；
In step S203, when breakdown judge logic circuit 11 judges the count value N and the first clock signal and second
Whether the frequency ratio M of clock signal is equal, when N is equal with M, is determining first clock signal and second clock signal just
Often, when N and M are unequal, then determine that first clock signal and second clock signal have one in abnormality, then give birth to
The alarm lamp 5 is delivered at alarm signal, while by the alarm signal of generation.
In embodiments of the present invention, server clock signal monitoring system include general topological clock circuit 1, crystal 3, when
Clock abnormal signal observation circuit 4 and alarm lamp 5；Crystal 3 is used to generate the second clock signal an of fixed frequency, and
Clock signal exception monitoring circuit 4 is delivered to using second clock signal as the input signal of clock signal exception monitoring circuit 4；
Clock signal exception monitoring circuit 4 obtains the first clock signal and second clock signal respectively, and judge the first clock signal and
Second clock signal when there is one to break down in the first clock signal and second clock signal, is then given birth to the presence or absence of exception
The alarm lamp 5 is delivered at alarm signal, while by the alarm signal of generation；According to the clock signal exception monitoring
Movement is lighted in the alarm signal that circuit 4 exports, the execution of alarm lamp 5, to realize quickly positioning due to system clock exception
Server failure problem caused by and.
The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；Although referring to aforementioned each reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified, or equivalent substitution of some or all of the technical features；And
These are modified or replaceed, the range for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution,
It should all cover within the scope of the claims and the description of the invention.
Claims (8)
1. a kind of server clock signal monitoring system, including general topological clock circuit, the general topological clock circuit is defeated
If the first clock signal of main line out, corresponding terminal device device is connected per the first clock signal all the way, which is characterized in that described
Server clock signal monitoring system further includes crystal, clock signal exception monitoring circuit and alarm lamp；
The crystal is made for generating the second clock signal an of fixed frequency, and by the second clock signal of generation
The clock signal exception monitoring circuit is delivered to for the input signal of the clock signal exception monitoring circuit；
The clock signal exception monitoring circuit is connect, for obtaining respectively respectively with the crystal and general topological clock circuit
First clock signal and second clock signal are taken, and judges that first clock signal and second clock signal whether there is
It is abnormal, when there is one to break down in first clock signal and second clock signal, then alarm signal is generated, simultaneously will
The alarm signal of generation is delivered to the alarm lamp；
The alarm lamp, for the alarm signal according to the clock signal exception monitoring circuit output, execution is lighted dynamic
Make.
2. server clock signal monitoring system according to claim 1, which is characterized in that the general topological clock electricity
Road includes crystal oscillator, South Bridge chip and clock buffer；
The crystal oscillator is connect with South Bridge chip signal, and the South Bridge chip is connect with the clock buffer signal.
3. server clock signal monitoring system according to claim 2, which is characterized in that the clock signal is supervised extremely
Slowdown monitoring circuit includes:
Clock edge detection circuit is obtained for obtaining first clock signal from the clock buffer from the crystal
The second clock signal, and triggered using first clock signal and the faster clock signal of second clock signal intermediate frequency rate
The slower clock signal of frequency, detection obtain the rising edge of the slower clock signal of frequency；
Rising edge clock counting circuit is connect with the clock edge detection circuit, for working as the clock edge detection circuit
When detecting the rising edge of the slower clock signal of frequency, the rising edge of the faster clock signal of frequency is counted, and works as
When the clock edge detection circuit detects the rising edge of the slower clock signal of frequency again, stops counting, be denoted as N；
Breakdown judge logic circuit is connect, when for judging the count value N and first with the rising edge clock counting circuit
Whether the frequency ratio M of clock signal and second clock signal is equal, when N is equal with M, determines first clock signal and the
Two clock signals are normal, when N and M are unequal, then determine that first clock signal and second clock signal have at one
In abnormality, then alarm signal is generated, while the alarm signal of generation is delivered to the alarm lamp.
4. server clock signal monitoring system according to claim 3, which is characterized in that first clock signal from
The idle pin of the clock buffer is drawn.
5. server clock signal monitoring system according to claim 3, which is characterized in that first clock signal from
It is obtained in connection line between the clock buffer and the terminal device device.
6. server clock signal monitoring system according to claim 1, which is characterized in that the clock signal is supervised extremely
Slowdown monitoring circuit is built in Complex Programmable Logic Devices.
7. a kind of server clock signal monitoring method based on server clock signal monitoring system described in claim 1,
It is characterized in that, the method includes the following steps:
Crystal generates the second clock signal of a fixed frequency, and using the second clock signal of generation as the clock
The input signal of abnormal signal observation circuit is delivered to the clock signal exception monitoring circuit；
Clock signal exception monitoring circuit obtains first clock signal and second clock signal respectively, and judges described first
Clock signal and second clock signal are with the presence or absence of abnormal, when there is a hair in first clock signal and second clock signal
When raw failure, then alarm signal is generated, while the alarm signal of generation is delivered to the alarm lamp；
According to the alarm signal of the clock signal exception monitoring circuit output, movement is lighted in alarm lamp execution.
8. server clock signal monitoring method according to claim 7, which is characterized in that the clock signal is supervised extremely
Slowdown monitoring circuit obtains first clock signal and second clock signal respectively, and judges first clock signal and second clock
Signal when there is one to break down in first clock signal and second clock signal, then generates report with the presence or absence of exception
Alert signal, at the same the step of alarm signal of generation is delivered to the alarm lamp specifically include the following steps:
Clock edge detection circuit obtains first clock signal from the clock buffer, obtains described the from the crystal
Two clock signals, and using first clock signal and second clock signal intermediate frequency rate faster clock signal triggering frequency compared with
Slow clock signal, detection obtain the rising edge of the slower clock signal of frequency；
When the clock edge detection circuit detects the rising edge of the slower clock signal of frequency, rising edge clock counts electricity
Road counts the rising edge of the faster clock signal of frequency, and when the clock edge detection circuit detects frequency again
When the rising edge of slower clock signal, stops counting, be denoted as N；
Breakdown judge logic circuit judges that the frequency ratio M of the count value N and the first clock signal and second clock signal are
It is no equal, when N is equal with M, determine that first clock signal and second clock signal are normal, when N and M are unequal,
Then determine that first clock signal and second clock signal have one then to generate alarm signal in abnormality, simultaneously will
The alarm signal of generation is delivered to the alarm lamp.
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| CN201910572310.3A CN110308765A (en) | 2019-06-28 | 2019-06-28 | A kind of server clock signal monitoring system and monitoring method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114261354A (en) * | 2021-12-24 | 2022-04-01 | 南京英锐创电子科技有限公司 | Low-frequency clock circuit and control method |
| CN115877917A (en) * | 2023-02-21 | 2023-03-31 | 南京芯驰半导体科技有限公司 | Signal processing system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694616A (en) * | 2012-06-11 | 2012-09-26 | 福建星网锐捷网络有限公司 | Clock detection circuit, clock circuit and clock exception detection method |
| CN103365757A (en) * | 2013-07-29 | 2013-10-23 | 浙江中控技术股份有限公司 | Clock detecting method and device |
| CN106597096A (en) * | 2016-12-02 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Clock frequency monitoring method |
| CN106776244A (en) * | 2017-03-10 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of server clock failure automatic detection repair system and method |
| CN109004932A (en) * | 2018-06-29 | 2018-12-14 | 合肥微商圈信息科技有限公司 | A kind of method of real-time detection differential clocks frequency correctness |
-
2019
- 2019-06-28 CN CN201910572310.3A patent/CN110308765A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694616A (en) * | 2012-06-11 | 2012-09-26 | 福建星网锐捷网络有限公司 | Clock detection circuit, clock circuit and clock exception detection method |
| CN103365757A (en) * | 2013-07-29 | 2013-10-23 | 浙江中控技术股份有限公司 | Clock detecting method and device |
| CN106597096A (en) * | 2016-12-02 | 2017-04-26 | 武汉新芯集成电路制造有限公司 | Clock frequency monitoring method |
| CN106776244A (en) * | 2017-03-10 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of server clock failure automatic detection repair system and method |
| CN109004932A (en) * | 2018-06-29 | 2018-12-14 | 合肥微商圈信息科技有限公司 | A kind of method of real-time detection differential clocks frequency correctness |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114261354A (en) * | 2021-12-24 | 2022-04-01 | 南京英锐创电子科技有限公司 | Low-frequency clock circuit and control method |
| CN114261354B (en) * | 2021-12-24 | 2023-07-04 | 南京英锐创电子科技有限公司 | Low frequency clock circuit and control method |
| CN115877917A (en) * | 2023-02-21 | 2023-03-31 | 南京芯驰半导体科技有限公司 | Signal processing system |
| CN115877917B (en) * | 2023-02-21 | 2023-11-10 | 南京芯驰半导体科技有限公司 | Signal processing system |
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