CN114238005B - GPIO anti-shake function test method, system, device and chip - Google Patents
GPIO anti-shake function test method, system, device and chip Download PDFInfo
- Publication number
- CN114238005B CN114238005B CN202210164709.XA CN202210164709A CN114238005B CN 114238005 B CN114238005 B CN 114238005B CN 202210164709 A CN202210164709 A CN 202210164709A CN 114238005 B CN114238005 B CN 114238005B
- Authority
- CN
- China
- Prior art keywords
- gpio
- interference signals
- shake function
- judging
- shake
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000010998 test method Methods 0.000 title claims description 15
- 238000012360 testing method Methods 0.000 claims abstract description 38
- 238000012545 processing Methods 0.000 claims abstract description 17
- 238000001514 detection method Methods 0.000 claims abstract description 13
- 230000006870 function Effects 0.000 claims description 123
- 230000002159 abnormal effect Effects 0.000 claims description 33
- 238000004590 computer program Methods 0.000 claims description 6
- 238000003708 edge detection Methods 0.000 claims description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000011990 functional testing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 23
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 238000013024 troubleshooting Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a method, a system, a device and a chip for testing GPIO anti-shake function, wherein the method is applied to the chip, firstly, GPIO to be tested and GPIO for auxiliary detection in the chip are determined, then interference signals with any time width can be generated in the chip according to a clock in the chip, the interference signals are sent to the GPIO to be tested through the GPIO for auxiliary detection, then the interference signals received by the GPIO to be tested after anti-shake processing are received, whether the anti-shake function of the GPIO to be tested is normal is judged by judging whether the number of all the interference signals received by the GPIO to be tested after anti-shake processing is equal to a first preset number, and therefore, an external signal generator is not required to be added in the mode, and meanwhile, the interference signals with any time length required by testing can be generated.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a method, a system, a device and a chip for testing a GPIO anti-shake function.
Background
With the development of chip technology, the functions of the chip are more and more, and at present, the chip mostly adopts GPIO (General-purpose input/output), and one GPIO can multiplex various signal pins, so that a user can customize the functions of the chip through the GPIO conveniently. The anti-shake function of the GPIO can remove interference signals in signals input into the GPIO, which directly influences whether the signals input into the chip through the GPIO are accurate, so that the test of the anti-shake function of the GPIO is very important.
In the prior art, an external signal source is usually used to test the anti-shake function of the GPIO, an analog interference signal generated by the external signal source is input to a chip through the GPIO, and then whether the chip receives the analog interference signal is observed to determine whether the GPIO filters out the interference signal, so as to determine whether the anti-shake function of the GPIO is intact. However, the interference signal generated by the external signal source may not satisfy the time width of the interference signal required by the anti-shaking function test of the GPIO, i.e., the external signal source may not generate the appropriate interference signal required by the test, which has a certain limitation.
Disclosure of Invention
The invention aims to provide a method, a system, a device and a chip for testing a GPIO anti-shake function, which do not need to add an additional signal generator and can generate an interference signal with any time length required by the test.
In order to solve the technical problem, the invention provides a GPIO anti-shake function test method which is applied to a chip and comprises the following steps:
determining a first GPIO to be detected and a second GPIO assisting in detection of the chip;
generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
receiving N interference signals subjected to the first GPIO anti-shaking processing through the first GPIO, wherein N is an integer not less than 0 and not more than M;
judging whether the total number of the N interference signals is equal to a first preset value or not;
and if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
Preferably, generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, where M is an integer not less than 1 includes:
and generating M interference signals with different time widths, and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1.
Preferably, generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, where M is an integer not less than 1 includes:
generating A interference signals with time widths smaller than a first time width threshold value and B interference signals with time widths not smaller than the first time width threshold value, wherein A and B are integers not smaller than 0;
sending, by the second GPIO, a number of interference signals whose time widths are smaller than the first time width threshold and B number of interference signals whose time widths are not smaller than the first time width threshold to the first GPIO;
judging whether the total number of the N interference signals is equal to a first preset value or not, including:
and judging whether the total number of the N interference signals is B or not, if so, judging that the anti-shaking function of the first GPIO is normal, otherwise, judging that the anti-shaking function of the first GPIO is abnormal.
Preferably, the determining whether the total number of the N interference signals is equal to a first preset value includes:
performing edge detection on the N interference signals to obtain J level jumps in the N interference signals;
judging whether J/2 is equal to a first preset value or not; and if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
Preferably, after determining that the anti-shake function of the first GPIO is abnormal, the method further includes:
and recording and storing abnormal anti-shake function of the first GPIO.
Preferably, after determining that the anti-shake function of the first GPIO is normal or determining that the anti-shake function of the first GPIO is abnormal, the method further includes:
generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
receiving I interference signals subjected to anti-shaking processing by the second GPIO through the second GPIO, wherein I is an integer not less than 0, and I is not more than M;
judging whether the total number of the I interference signals is equal to a second preset value or not;
and if so, judging that the anti-shake function of the second GPIO is normal, otherwise, judging that the anti-shake function of the second GPIO is abnormal.
Preferably, after determining that the anti-shake function of the second GPIO is abnormal, the method further includes:
and recording and storing abnormal anti-shake function of the second GPIO.
In order to solve the above technical problem, the present invention further provides a GPIO anti-shaking function testing system, including:
the GPIO determining unit is used for determining a first GPIO to be detected and a second GPIO for assisting detection;
the interference signal generation unit is used for generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
the interference signal receiving unit is used for receiving N interference signals subjected to the first GPIO anti-shaking processing through the first GPIO, wherein N is an integer not less than 0, and N is not more than M;
and the anti-shake function judging unit is used for judging whether the total number of the N interference signals is equal to a first preset value, if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
In order to solve the above technical problem, the present invention further provides a GPIO anti-shaking function testing apparatus, including:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the steps of the GPIO anti-shake function test method.
In order to solve the technical problem, the invention further provides a chip which comprises the GPIO anti-shake function testing device.
The invention provides a method, a system, a device and a chip for testing GPIO anti-shake functions, wherein the method comprises the steps of firstly determining a GPIO to be detected and a GPIO for auxiliary detection of the chip, then generating interference signals with any time width in the chip according to a clock in the chip, sending the interference signals to the GPIO to be detected through the GPIO for auxiliary detection, then receiving the interference signals received by the GPIO to be detected after anti-shake processing, and judging whether the anti-shake functions of the GPIO to be detected are normal or not by judging whether the number of all the interference signals received by the GPIO to be detected after the anti-shake functions is equal to a first preset number.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flowchart of a GPIO anti-shake function test method provided by the present invention;
FIG. 2 is a schematic structural diagram of a GPIO anti-shake function test system provided by the present invention;
fig. 3 is a schematic structural diagram of a GPIO anti-shaking function testing apparatus provided in the present invention;
fig. 4 is a schematic structural diagram of a chip according to the present invention.
Detailed Description
The core of the invention is to provide a method, a system, a device and a chip for testing the GPIO anti-shake function, which do not need to add an additional signal generator and can generate an interference signal with any time length required by the test.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a GPIO anti-shaking function testing method provided by the present invention, applied to a chip, including:
s11: determining a first GPIO to be detected and a second GPIO assisting in detection of the chip;
s12: generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
s13: receiving N interference signals subjected to the first GPIO anti-shaking processing through a first GPIO, wherein N is an integer not less than 0, and N is not more than M;
s14: judging whether the total number of the N interference signals is equal to a first preset value or not, if so, entering S15, and otherwise, entering S16;
s15: judging that the anti-shake function of the first GPIO is normal;
s16: and judging that the anti-shake function of the first GPIO is abnormal.
At present, in the prior art, an external signal source is usually used to test the anti-shake function of the GPIO, a signal generated by the external signal source is used to simulate an interference signal, the simulated interference signal is input to a chip through the GPIO to be detected, and then whether the chip receives the simulated interference signal is observed to determine whether the anti-shake function of the chip can filter out the interference signal, so as to determine whether the anti-shake function of the GPIO is normal. However, sometimes the interference signal generated by the external signal source may not meet the time width of the interference signal required by the anti-shake function test of the GPIO, and the external signal source needs an additional signal generator, which increases the test cost.
In order to solve the above problem, in this embodiment, an anti-shake function testing module is designed inside the chip, and through this module, the anti-shake function testing of the GPIO of the chip can be completed. Specifically, when the GPIO receives a signal, there is a time width threshold for starting the anti-shake function, and the time width threshold may be configured according to an actual use situation, and the present invention is not particularly limited thereto, for example, when the configured time width threshold for starting the anti-shake function by the GPIO is 10us, the GPIO considers that all signals with a received time width of less than 10us are interference signals, and then filters the interference signals The number of the interference signals which should be remained after the first GPIO anti-shaking processing is performed under the normal condition can be known, and finally, whether the anti-shaking function of the first GPIO is normal is determined by determining whether the number of the remaining N interference signals which are actually received is equal to the number of the interference signals which should be remained after the first GPIO anti-shaking processing is performed under the normal condition. For example, when the configured GPIO starts the anti-shake function with a time width threshold of 10us, a tester may generate 11 interference signals, which are 1us, 2us, ·, 10us, and 11us, inside the chip through configuration, and send the interference signals to the first GPIO through the second GPIO, at this time, if the anti-shake function of the first GPIO is normal, the interference signals with a time width below 10us should all be filtered out, that is, the finally received interference signals should only have two interference signals with time widths of 10us and 11us, when the tester detects that the number of the finally received interference signals is two, the anti-shake function of the first GPIO can be proved to be normal, otherwise, the anti-shake function of the first GPIO is proved to be abnormal.
It should be noted that, the module for generating the interference signal inside the chip uses a clock with the fastest internal frequency of the chip, for example, the fastest clock inside the chip is k, and the clock period Tm =1/k, so that the time width of the interference signal with the smallest time width that the module can generate is Tm, and then the interference signal with the time width of N x Tm can be generated by configuring a register inside the chip, where the size of N can be configured according to actual requirements, so as to generate the interference signal with any time width, thereby more comprehensively verifying whether the anti-jitter function of the GPIO of the chip is normal.
In summary, the invention provides a GPIO anti-shake function test method, which includes determining a GPIO to be detected and a GPIO for auxiliary detection of a chip, generating an interference signal with any time width in the chip according to a clock in the chip, sending the interference signal to the GPIO to be detected through the GPIO for auxiliary detection, receiving the interference signal received by the GPIO to be detected after anti-shake processing, and determining whether the anti-shake function of the GPIO to be detected is normal by determining whether the number of all the interference signals received by the GPIO to be detected after the GPIO is subjected to the anti-shake function is equal to a first preset number.
On the basis of the above-described embodiment:
as a preferred embodiment, generating M interference signals and transmitting the M interference signals to the first GPIO through the second GPIO, where M is an integer not less than 1, includes:
and generating M interference signals with different time widths, and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1.
In this embodiment, in consideration of the fact that in an actual use situation, a tester may need a plurality of interference signals with different time widths, in this embodiment, the generated M interference signals may be M interference signals with different time widths, so that the test has more versatility.
As a preferred embodiment, generating M interference signals and transmitting the M interference signals to the first GPIO through the second GPIO, where M is an integer not less than 1, includes:
generating A interference signals with time widths smaller than a first time width threshold value and B interference signals with time widths not smaller than the first time width threshold value, wherein A and B are integers not smaller than 0;
sending A interference signals with time widths smaller than a first time width threshold value and B interference signals with time widths not smaller than the first time width threshold value to the first GPIO through the second GPIO;
judging whether the total number of the N interference signals is equal to a first preset value or not, including:
and judging whether the total number of the N interference signals is B, if so, judging that the anti-shaking function of the first GPIO is normal, and otherwise, judging that the anti-shaking function of the first GPIO is abnormal.
In this embodiment, it is considered that the time width threshold for starting the anti-shake function by the GPIO may be configured by the tester, so in this embodiment, the tester may also generate a plurality of interference signals with time widths smaller than the first time width threshold and a plurality of interference signals with time widths not smaller than the first time width threshold according to the configured first time threshold, and finally determine whether the anti-shake function of the first GPIO is normal by determining whether the number of the interference signals received after the first GPIO anti-shake processing is equal to the number of the interference signals generated with time widths not smaller than the first time width threshold, thereby improving the feasibility of the scheme.
As a preferred embodiment, the determining whether the total number of the N interference signals is equal to a first preset value includes:
carrying out edge detection on the N interference signals to obtain J level jumps existing in the N interference signals;
judging whether J/2 is equal to a first preset value or not; if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
In this embodiment, the chip determines the number of the received interference signals by performing edge detection on the received interference signals, specifically, the interference signals with different time widths all have a rising edge and a falling edge, that is, one interference signal should correspond to two edge transitions, the total number of the edge transitions is divided by two by detecting the total number of the edge transitions in all the received interference signals, so as to obtain the number of the received interference signals, and whether the number of the interference signals is equal to the first preset value is determined by this way, so that the implementation manner is simple.
As a preferred embodiment, after determining that the anti-shake function of the first GPIO is abnormal, the method further includes:
and recording and storing the abnormal anti-shake function of the first GPIO.
In this embodiment, when the anti-shake function of the GPIO is out of order, the user may have a subsequent need to check the failed GPIO, so this scheme can also record after determining that the anti-shake function of the first GPIO is abnormal, so that the user can perform subsequent troubleshooting.
As a preferred embodiment, after determining that the anti-shake function of the first GPIO is normal or determining that the anti-shake function of the first GPIO is abnormal, the method further includes:
generating M interference signals and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
receiving I interference signals subjected to anti-shaking processing by a second GPIO through the second GPIO, wherein I is an integer not less than 0, and I is not more than M;
judging whether the total number of the I interference signals is equal to a second preset value or not;
and if so, judging that the anti-shaking function of the second GPIO is normal, otherwise, judging that the anti-shaking function of the second GPIO is abnormal.
In the embodiment, the situation that the anti-shake function of the GPIO is only embodied in the process of receiving data by the GPIO is considered, and therefore whether the anti-shake function of the GPIO is normal or not does not affect the data sending function of the GPIO, and therefore after the situation that whether the anti-shake function of the first GPIO is normal or not is judged, the functions of the first GPIO and the second GPIO can be exchanged, namely the first GPIO sends an interference signal to the second GPIO, so that the anti-shake function test of the second GPIO is completed.
As a preferred embodiment, after determining that the anti-shake function of the second GPIO is abnormal, the method further includes:
and recording and storing the abnormal anti-shake function of the second GPIO.
In this embodiment, when the anti-shake function of the GPIO is out of order, the user may have a subsequent need to check the failed GPIO, so this scheme can also record after determining that the anti-shake function of the second GPIO is abnormal, so that the user can perform subsequent troubleshooting.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a GPIO anti-shake function testing system provided by the present invention, including:
a GPIO determining unit 21 configured to determine a first GPIO to be detected and a second GPIO that assists in detection;
the interference signal generating unit 22 is configured to generate M interference signals and send the M interference signals to the first GPIO through the second GPIO, where M is an integer not less than 1;
the interference signal receiving unit 23 is configured to receive, through the first GPIO, N interference signals subjected to the first GPIO anti-shake processing, where N is an integer not less than 0, and N is not greater than M;
and the anti-shake function judging unit 24 is configured to judge whether the total number of the N interference signals is equal to a first preset value, determine that the anti-shake function of the first GPIO is normal if the total number of the N interference signals is equal to the first preset value, and determine that the anti-shake function of the first GPIO is abnormal if the total number of the N interference signals is not equal to the first preset value.
For the introduction of the GPIO anti-shake function test system provided by the present invention, please refer to the above method embodiment, which is not described herein again.
The present invention further provides a GPIO anti-shake function testing device, please refer to fig. 3, where fig. 3 is a schematic structural diagram of the GPIO anti-shake function testing device provided by the present invention, and the testing device includes:
a memory 31 for storing a computer program;
and the processor 32 is used for executing a computer program to realize the steps of the GPIO anti-shake function test method.
For the introduction of the GPIO anti-shake function testing apparatus provided by the present invention, please refer to the above method embodiment, and the present invention is not described herein again.
The invention also provides a chip, which comprises the GPIO anti-shaking function testing device, please refer to fig. 4, and fig. 4 is a schematic structural diagram of a chip provided by the invention.
Besides being connected with other modules of the chip, each GPIO port in the chip is also connected with the GPIO anti-shake function testing device provided by the invention, and the GPIO anti-shake function testing device can generate interference signals with different time lengths, send the interference signals to be detected through the GPIO for assisting detection, and receive the interference signals of the GPIO to be detected after anti-shake processing, so that the test of the GPIO anti-shake function is completed.
For other descriptions of the chip provided by the present invention, please refer to the above method embodiment, which is not repeated herein.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A GPIO anti-shake function test method is characterized in that the test method is applied to a chip and comprises the following steps:
determining a first GPIO to be detected and a second GPIO assisting in detection of the chip;
generating M interference signals based on an internal clock of the chip and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
receiving N interference signals subjected to the first GPIO anti-shaking processing through the first GPIO, wherein N is an integer not less than 0 and not more than M;
judging whether the total number of the N interference signals is equal to a first preset value or not;
and if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
2. The GPIO anti-shake function test method of claim 1, wherein generating M interference signals and transmitting the M interference signals to the first GPIO through the second GPIO, M being an integer no less than 1, includes:
and generating M interference signals with different time widths, and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1.
3. The GPIO anti-shake function test method of claim 1, wherein generating M interference signals and transmitting the M interference signals to the first GPIO through the second GPIO, M being an integer no less than 1, includes:
generating A interference signals with time widths smaller than a first time width threshold value and B interference signals with time widths not smaller than the first time width threshold value, wherein A and B are integers not smaller than 0;
sending, by the second GPIO, a number of interference signals whose time widths are smaller than the first time width threshold and B number of interference signals whose time widths are not smaller than the first time width threshold to the first GPIO;
judging whether the total number of the N interference signals is equal to a first preset value or not, including:
and judging whether the total number of the N interference signals is B or not, if so, judging that the anti-shaking function of the first GPIO is normal, otherwise, judging that the anti-shaking function of the first GPIO is abnormal.
4. The GPIO anti-jitter function testing method of claim 1, wherein determining whether a total number of the N interference signals is equal to a first preset value comprises:
performing edge detection on the N interference signals to obtain J level jumps in the N interference signals;
judging whether J/2 is equal to a first preset value or not; and if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
5. The GPIO anti-shake function test method of claim 1, wherein after determining that the anti-shake function of the first GPIO is abnormal, further comprising:
and recording and storing abnormal anti-shake function of the first GPIO.
6. The GPIO anti-shake function test method of any one of claims 1 to 5, wherein after determining that the anti-shake function of the first GPIO is normal or determining that the anti-shake function of the first GPIO is abnormal, further comprising:
generating M interference signals and sending the M interference signals to the second GPIO through the first GPIO, wherein M is an integer not less than 1;
receiving I interference signals subjected to anti-shaking processing by the second GPIO through the second GPIO, wherein I is an integer not less than 0, and I is not more than M;
judging whether the total number of the I interference signals is equal to a second preset value or not;
and if so, judging that the anti-shake function of the second GPIO is normal, otherwise, judging that the anti-shake function of the second GPIO is abnormal.
7. The GPIO anti-shake function test method of claim 6, wherein after determining that the anti-shake function of the second GPIO is abnormal, further comprising:
and recording and storing abnormal anti-shake function of the second GPIO.
8. A GPIO anti-shake function test system, characterized in that includes:
the GPIO determining unit is used for determining a first GPIO to be detected and a second GPIO for assisting detection;
the interference signal generation unit is used for generating M interference signals based on an internal clock of the chip and sending the M interference signals to the first GPIO through the second GPIO, wherein M is an integer not less than 1;
the interference signal receiving unit is used for receiving N interference signals subjected to the first GPIO anti-shaking processing through the first GPIO, wherein N is an integer not less than 0, and N is not more than M;
and the anti-shake function judging unit is used for judging whether the total number of the N interference signals is equal to a first preset value, if so, judging that the anti-shake function of the first GPIO is normal, otherwise, judging that the anti-shake function of the first GPIO is abnormal.
9. The utility model provides a GPIO anti-shake functional test device which characterized in that includes:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the GPIO anti-shake function test method according to any one of claims 1 to 7.
10. A chip characterized by comprising the GPIO anti-jitter function testing apparatus of claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210164709.XA CN114238005B (en) | 2022-02-23 | 2022-02-23 | GPIO anti-shake function test method, system, device and chip |
| PCT/CN2022/135692 WO2023160099A1 (en) | 2022-02-23 | 2022-11-30 | Gpio anti-shake function test method, system and apparatus and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210164709.XA CN114238005B (en) | 2022-02-23 | 2022-02-23 | GPIO anti-shake function test method, system, device and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114238005A CN114238005A (en) | 2022-03-25 |
| CN114238005B true CN114238005B (en) | 2022-05-24 |
Family
ID=80747806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210164709.XA Active CN114238005B (en) | 2022-02-23 | 2022-02-23 | GPIO anti-shake function test method, system, device and chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN114238005B (en) |
| WO (1) | WO2023160099A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114238005B (en) * | 2022-02-23 | 2022-05-24 | 苏州浪潮智能科技有限公司 | GPIO anti-shake function test method, system, device and chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729988A (en) * | 2019-09-25 | 2020-01-24 | 中山大学 | Circuit, output device, detection system and method for outputting clock jitter signal |
| CN111952994A (en) * | 2020-08-12 | 2020-11-17 | 珠海泰为电子有限公司 | Microprocessor chip and application method thereof |
| CN113157501A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Micro-system module AC parameter testing method based on ATE tester |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103308843A (en) * | 2012-03-09 | 2013-09-18 | 鸿富锦精密工业（深圳）有限公司 | Chip with receiver test function and circuit board with receiver test function |
| TWI515550B (en) * | 2014-08-27 | 2016-01-01 | 緯創資通股份有限公司 | Chip device and electronic system thereof |
| US10248585B2 (en) * | 2016-06-14 | 2019-04-02 | Oracle International Corporation | System and method for filtering field programmable gate array input/output |
| CN210347850U (en) * | 2019-05-21 | 2020-04-17 | 中国电子技术标准化研究院 | Ultrahigh frequency passive chip performance test system and loss measurement device thereof |
| US10554237B1 (en) * | 2019-06-21 | 2020-02-04 | Motorola Solutions, Inc. | Apparatus and method for accessory detection in a portable communication device |
| CN112286750A (en) * | 2020-10-29 | 2021-01-29 | 山东云海国创云计算装备产业创新中心有限公司 | GPIO (general purpose input/output) verification method and device, electronic equipment and medium |
| CN114238005B (en) * | 2022-02-23 | 2022-05-24 | 苏州浪潮智能科技有限公司 | GPIO anti-shake function test method, system, device and chip |
-
2022
- 2022-02-23 CN CN202210164709.XA patent/CN114238005B/en active Active
- 2022-11-30 WO PCT/CN2022/135692 patent/WO2023160099A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729988A (en) * | 2019-09-25 | 2020-01-24 | 中山大学 | Circuit, output device, detection system and method for outputting clock jitter signal |
| CN111952994A (en) * | 2020-08-12 | 2020-11-17 | 珠海泰为电子有限公司 | Microprocessor chip and application method thereof |
| CN113157501A (en) * | 2021-02-26 | 2021-07-23 | 西安微电子技术研究所 | Micro-system module AC parameter testing method based on ATE tester |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023160099A1 (en) | 2023-08-31 |
| CN114238005A (en) | 2022-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111538539B (en) | Storage system starting method and device and computer readable storage medium | |
| EP2584471A1 (en) | Method and terminal for selecting internal circuit according to USB interface status | |
| CN113434355B (en) | Module verification method, UVM verification platform, electronic device and storage medium | |
| CN114238005B (en) | GPIO anti-shake function test method, system, device and chip | |
| CN110647486B (en) | PCIe link training method, end equipment and communication system | |
| CN112286750A (en) | GPIO (general purpose input/output) verification method and device, electronic equipment and medium | |
| WO2014082275A1 (en) | Method and apparatus for detecting cable connection condition | |
| US8391162B2 (en) | Apparatus and method for testing SMNP cards | |
| CN108369565A (en) | Communication device, communication means, program and communication system | |
| US20130141076A1 (en) | Spread Spectrum Clock Signal Detection System and Method | |
| US10884448B1 (en) | Clock glitch detection circuit | |
| CN111861858A (en) | Method and device for starting image compression function verification and related equipment | |
| CN116319475A (en) | Signal analysis method, device, equipment and storage medium | |
| CN113495225B (en) | Power supply stability test method, system and equipment | |
| CN114527832B (en) | Pulse signal edge measuring method and device, storage medium and micro-control unit | |
| JP2016165080A (en) | Receiver, determination method, and determination program | |
| CN113177063B (en) | Thermal reset method and related device of PCI bus equipment | |
| CN110988661B (en) | FPGA prototype verification development board time division analysis system, method, medium and terminal | |
| CN111309475B (en) | Detection task execution method and equipment | |
| JP2003271694A (en) | Simulation method and device for verifying logic circuit including processor and error detecting program for verifying logic circuit | |
| CN113160875A (en) | Chip test system and test method | |
| CN213814410U (en) | Frequency converter control panel test equipment, system and electronic device | |
| CN115616387B (en) | Control signal calibration method and system based on chip | |
| CN113407408B (en) | Data transmission rule verification method, device, equipment and storage medium | |
| CN113394785B (en) | Method and device for determining control strategy of active filter and readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |