CN111952994A

CN111952994A - Microprocessor chip and application method thereof

Info

Publication number: CN111952994A
Application number: CN202010804791.9A
Authority: CN
Inventors: 李建霖; 吴亚杰; 王乐鹏; 李庆顺; 李政霖; 向增
Original assignee: Zhuhai Taiwei Electronic Co ltd
Current assignee: Zhuhai Taiwei Electronic Co ltd
Priority date: 2020-08-12
Filing date: 2020-08-12
Publication date: 2020-11-17

Abstract

The invention provides a microprocessor chip and an application method thereof, wherein the chip comprises a first processing unit and a second processing unit, the first processing unit carries out analog-to-digital conversion on a first input signal and calculates to obtain a sine and cosine value of the first input signal, the second processing unit obtains the sine and cosine value output by the first processing unit and carries out analog-to-digital conversion and frequency spectrum separation on a second input signal to obtain an expected value in the input signal. The method of the invention adopts the chip to realize the comprehensive treatment of the electric energy quality of reactive compensation, unbalance adjustment and harmonic treatment. The invention can realize the comprehensive control function of the electric energy quality of reactive compensation, unbalance adjustment and harmonic control by using the chip as the only processor.

Description

Microprocessor chip and application method thereof

Technical Field

The invention relates to the technical field of microelectronics, in particular to a microprocessor chip suitable for positive and negative sequence active, reactive and harmonic extraction, display and control of an electric signal and a method applied to the chip.

Background

The comprehensive electric energy quality treating device is used for treating three-phase current unbalance, reactive compensation and harmonic treatment on the low-voltage distribution user side.

At present, most of the existing reactive compensation, imbalance adjustment and electric energy quality comprehensive treatment schemes in the market adopt a combination scheme of a TI chip and an FPGA/CPLD chip of Altera or Xilinx, the TI chip realizes control of an algorithm module, and the FPGA/CPLD chip of Altera or Xilinx realizes PWM.

However, in order to implement complex functions, some occasions require the architecture of multiple TI chips + Altera or Xilinx FPGAs/CPLDs. Secondly, the design of the whole scheme of the FPGA/CPLD architecture of the TI chip + Altera or Xilinx requires a user to independently develop all codes, and the working difficulty is high.

Disclosure of Invention

The invention mainly aims to provide a microprocessor chip which has small area and strong function and can realize the comprehensive management of the electric energy quality of reactive compensation, unbalance adjustment and harmonic management.

The invention also aims to provide an application method of the microprocessor chip for electric energy quality comprehensive control, which can realize reactive compensation, unbalance adjustment and harmonic control.

In order to achieve the above main objective, the present invention provides a microprocessor chip, which includes a first processing unit and a second processing unit, wherein the first processing unit performs analog-to-digital conversion on a first input signal and calculates to obtain a sine and cosine value of the first input signal, and the second processing unit obtains the sine and cosine value output by the first processing unit and performs analog-to-digital conversion and spectrum separation on a second input signal to obtain an expected value in the input signal.

In a further scheme, the chip further comprises a third processing unit, the third processing unit compares an expected value output by the second processing unit as an input of feedback control with an actual value of a third input signal subjected to analog-to-digital conversion to obtain a modulation signal, the modulation signal is subjected to PWM pulse width modulation to obtain a PWM pulse, and the PWM pulse is output through a GPIO interface to control the power switching tube.

In a further scheme, when the PWM pulse passes through the GPIO interface output chip to drive the power switching tube to operate, a new input signal is formed again to enter the GPIO interface of the chip to perform error comparison with the expected value output by the second processing unit, so that the actual value of the new input signal is continuously close to the expected value.

In a further aspect, the first processing unit includes a first analog-to-digital converter, a DFT module, an ATAN function module, and a sine and cosine module, an input end of the first analog-to-digital converter is connected to a first input signal, an output end of the first analog-to-digital converter is connected to an input end of the DFT module, an output end of the DFT module is connected to an input end of the ATAN function module, an output end of the ATAN function module is connected to an input end of the sine and cosine module, and output ends of the sine and cosine module output sine and cosine signals, respectively.

In a further aspect, the second processing unit includes a second analog-to-digital converter, a first Matrix module, an FFT module, an HCC module, and a second Matrix module, where the second analog-to-digital converter accesses a second input signal, an output end of the second analog-to-digital converter is connected to an input end of the first Matrix module, an output end of the first Matrix module is connected to an input end of the FFT module, an output end of the FFT module is connected to an input end of the HCC module, an output end of the HCC module is connected to an input end of the second Matrix module, the first Matrix module and the second Matrix module receive the sine cosine value, and an output end of the second Matrix module outputs a desired value.

In a further aspect, the third processing unit includes a third analog-to-digital converter, a controller module, and a pulse width modulation module, an input end of the third analog-to-digital converter is connected to a third input signal, an output end of the third analog-to-digital converter is connected to an input end of the controller module, an input end of the controller module receives an error value between an actual value and an expected value of the third input signal subjected to analog-to-digital conversion, an output end of the controller module is connected to an input end of the pulse width modulation module, and an output end of the pulse width modulation module is connected to the GPIO interface.

Therefore, the invention realizes angle tracking phase locking through the DFT, ATAN and sine and cosine modules arranged in the chip, then realizes frequency spectrum separation through the FFT and HCC arranged in the chip to obtain an expected value, finally realizes compensation control and pulse width modulation through the IIR extended controller and the PWM module arranged in the chip, and drives the power switch tube to act through the PWM pulse outside the GPIO output chip, thereby forming an input signal again to enter the GPIO, and then carrying out iterative analysis, calculation and control again through ADC analog-to-digital conversion, and continuously repeating, so that the actual value is continuously close to the expected value.

Therefore, the processor chip can replace a plurality of chips to realize the same function, and the chip can be used as the only processor to realize the comprehensive control function of the electric energy quality of reactive power compensation, unbalance adjustment and harmonic control; the architecture is unique, the use is simple, a plurality of function realization modes are fixed, and the user can achieve the aim only by configuring the register.

In order to achieve the above another object, the present invention provides an application method of a microprocessor chip, where the microprocessor chip employs the above microprocessor chip, and the application method includes: step S1, carrying out angle tracking phase locking on the first input signal by using a first processing unit arranged in a chip, and calculating to obtain a sine and cosine value of the first input signal; and step S2, according to the obtained sine and cosine values, performing analog-to-digital conversion and spectrum separation on the second input signal by using a second processing unit built in the chip to obtain expected values in the input signal.

A further scheme is that the method further includes step S3, comparing an expected value output by the second processing unit as an input of feedback control with an actual value of a third input signal subjected to analog-to-digital conversion, performing compensation control and pulse width modulation by using a third processing unit built in the chip, forming a PWM pulse, outputting the PWM pulse through a GPIO interface to drive a power switching tube to operate outside the chip, so as to form a new input signal again, enter the GPIO interface of the chip, and repeat continuously, so that the actual value of the new input signal is continuously close to the expected value.

Further, the step S1 specifically includes: analog signals of input voltages U1, U2 and U3 are obtained, analog-to-digital conversion is carried out on the input voltages U1, U2 and U3 through a first analog-to-digital converter, the input voltages U1, U2 and U3 are converted into components of two-phase coordinates A and B through a DFT module, a sine and cosine value of any phase of the input voltages U1, U2 and U3 is obtained through calculation of an ATAN function module and a sine and cosine module, and phase angle tracking phase locking of the input voltages U1, U2 and U3 is completed.

Further, the step S2 specifically includes: the method comprises the steps of obtaining analog signals of input currents I1, I2 and I3, carrying out analog-to-digital conversion on the input currents I1, I2 and I3 through a second analog-to-digital converter, outputting digital signals to a first Matrix module, carrying out Matrix transformation on the first Matrix module according to received sine and cosine values to output Matrix signals to an FFT module, and carrying out spectrum separation through the FFT module and an HCC module to obtain expected values.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a microprocessor chip according to the present invention.

FIG. 2 is a block diagram of a method for implementing a microprocessor chip according to an embodiment of the present invention.

FIG. 3 is a diagram of a first processing unit in an embodiment of a method for implementing a microprocessor chip according to the present invention.

FIG. 4 is a diagram of a second processing unit in an embodiment of a method for implementing a microprocessor chip according to the present invention.

FIG. 5 is a diagram of a third processing unit in an embodiment of a method for implementing a microprocessor chip according to the present invention.

FIG. 6 is a diagram illustrating a data structure of components of a signal separated by an FFT module according to an embodiment of the present invention.

The invention is further explained with reference to the drawings and the embodiments.

Detailed Description

A microprocessor chip embodiment:

referring to fig. 1, the microprocessor chip of the present invention includes a first processing unit and a second processing unit, the first processing unit performs analog-to-digital conversion on a first input signal and calculates to obtain a sine and cosine value of the first input signal, the second processing unit obtains the sine and cosine value output by the first processing unit and performs analog-to-digital conversion and spectrum separation on a second input signal to obtain an expected value in the input signal.

In this embodiment, the chip further includes a third processing unit, where the third processing unit compares an expected value output by the second processing unit as an input of feedback control with an actual value of a third input signal subjected to analog-to-digital conversion to obtain a modulation signal, and the modulation signal is subjected to PWM pulse width modulation to obtain a PWM pulse, which is output through the GPIO interface to control the power switching tube.

When the PWM pulse passes through the GPIO interface output chip to drive the power switch tube to act, a new input signal is formed again and enters the GPIO interface of the chip to be compared with the expected value output by the second processing unit in an error mode, and the actual value of the new input signal is enabled to be close to the expected value continuously.

In this embodiment, the first processing unit includes a first analog-to-digital converter 11, a DFT module 12, an ATAN function module 13, and a sine and cosine module 14, an input end of the first analog-to-digital converter 11 is connected to a first input signal, an output end of the first analog-to-digital converter 11 is connected to an input end of the DFT module 12, an output end of the DFT module 12 is connected to an input end of the ATAN function module 13, an output end of the ATAN function module 13 is connected to an input end of the sine and cosine module 14, and output ends of the sine and cosine module 14 output sine and cosine signals, respectively.

In this embodiment, the second processing unit includes a second analog-to-digital converter 21, a first Matrix module 22, an FFT module 23, an HCC module 24, and a second Matrix module 25, where the second analog-to-digital converter 21 is connected to the second input signal, an output end of the second analog-to-digital converter 21 is connected to an input end of the first Matrix module 22, an output end of the first Matrix module 22 is connected to an input end of the FFT module 23, an output end of the FFT module 23 is connected to an input end of the HCC module 24, an output end of the HCC module 24 is connected to an input end of the second Matrix module 25, the first Matrix module 22 and the second Matrix module 25 receive the positive cosine value, and an output end of the second Matrix module 25 outputs the expected value.

In this embodiment, the third processing unit includes a third analog-to-digital converter 31, a controller module 32, and a pulse width modulation module 33, an input end of the third analog-to-digital converter 31 is connected to the third input signal, an output end of the third analog-to-digital converter 31 is connected to an input end of the controller module 32, an input end of the controller module 32 receives an error value between an actual value and a desired value of the third input signal subjected to analog-to-digital conversion, an output end of the controller module 32 is connected to an input end of the pulse width modulation module 33, and an output end of the pulse width modulation module 33 is connected to the GPIO interface. The controller module 32 is an IIR/PR/PID controller.

Specifically, the chip of the invention comprises modules such as an analog-to-digital converter, a Matrix customized Matrix, a DFT, an ATAN, a SINCOS, an FFT, an IIR extension module, a PWM and the like which are integrated on the chip. The implementation mode is high in integration level, wide in application range and high in reliability, and is suitable for power equipment needing positive and negative sequence active, reactive and harmonic extraction, display and control.

Therefore, the invention realizes angle tracking phase locking sin _ ux and cos _ ux through the built-in DFT, ATAN and sine-cosine module 14 of the chip, then realizes frequency spectrum separation through the built-in FFT and HCC of the chip to obtain an expected value, finally realizes compensation control and pulse width modulation through the built-in extended IIR controller and the PWM module of the chip, and drives the power switch tube to act through the external of the GPIO output chip to form an input signal again to enter the GPIO, and then performs iterative analysis, calculation and control again through ADC analog-to-digital conversion so as to continuously repeat, thereby enabling the actual value to be continuously close to the expected value.

An embodiment of an application method of a microprocessor chip comprises the following steps:

an application method of a microprocessor chip is applied to the microprocessor chip, and referring to fig. 2, the application method for the reactive power compensation, the unbalance adjustment and the comprehensive power quality management function comprises the following steps:

first, step S1 is executed to perform angle tracking phase locking on the first input signal by using the first processing unit built in the chip, and calculate a cosine sine value of the first input signal. Wherein, step S1 specifically includes: analog signals of input voltages U1, U2 and U3 are obtained, analog-to-digital conversion is carried out on the input voltages U1, U2 and U3 through a first analog-to-digital converter 11, the input voltages U1, U2 and U3 are converted into components of two-phase coordinates A and B through a DFT module 12, a sine and cosine value of any phase of the input voltages U1, U2 and U3 is obtained through calculation of an function module 13 and a sine and cosine module 14, and phase angle tracking phase locking of the input voltages U1, U2 and U3 is completed.

Then, step S2 is executed to perform analog-to-digital conversion and spectrum separation on the second input signal by the second processing unit built in the chip according to the obtained sine and cosine value, so as to obtain the expected value of the input signal. Wherein, step S2 specifically includes: the method comprises the steps of obtaining analog signals of input currents I1, I2 and I3, performing analog-to-digital conversion on the input currents I1, I2 and I3 through a second analog-to-digital converter 21, outputting digital signals to a first Matrix module 22, performing Matrix transformation on the first Matrix module 22 according to received sine and cosine values to output Matrix signals to an FFT module 23, and performing frequency spectrum separation through the FFT module 23 and an HCC module 24 to obtain expected values.

Then, step S3 is executed, the expected value output by the second processing unit is used as the input of feedback control, and after error comparison is performed between the expected value and the actual value of the third input signal after analog-to-digital conversion, the third processing unit built in the chip is used to perform compensation control and pulse width modulation, PWM pulses are formed, and the power switching tube is driven to operate through the external of the GPIO interface output chip, so that a new input signal is formed again to enter the GPIO interface of the chip, and the steps are repeated, so that the actual value of the new input signal is continuously close to the expected value.

In addition, the power switch tube is driven to act through a driving circuit outside the output chip of the GPIO interface, and the calculated current is injected into a power grid after being filtered by a filter circuit, so that the comprehensive control function of the power quality of reactive compensation, unbalance adjustment and harmonic control is realized; and thus, a new input signal is formed again to enter the GPIO interface of the chip and is repeated continuously, so that the actual value of the new input signal is close to the expected value continuously.

In practical application, a chip is taken as a core, and a signal conditioning circuit is matched to detect three-phase current and voltage of a power distribution network to obtain sampling values of the three-phase current and voltage, wherein first input signals are three-phase voltage signals U1, U2 and U3, second input signals are external CT current signals I1, I2 and I3, and third input signals are three-phase current signals IF1, IF2 and IF 3.

The chip algorithm of the embodiment is mainly classified into 3 types: (1) phase locking; (2) extracting active, reactive and harmonic components of positive and negative sequences; (3) feedback control and modulation.

As shown in fig. 3, the main function of the phase lock (1) is to realize phase angle tracking phase locking of input voltage signals U1, U2, and U3, convert U1, U2, and U3 into two-phase coordinates, i.e., components a and B, by using DFT module 12, and obtain a sine and cosine value of any one phase of input voltages U1, U2, and U3 through computation by ATAN and sine and cosine module 14(SINCOS), thereby realizing the phase locking function.

As shown in fig. 4, (2) the main function of extracting positive and negative sequence active, reactive, and harmonic components is to perform analog-to-digital conversion and signal separation on the input analog ADC signal (e.g. input currents I1, I2, I3) to obtain the desired components in the input signal. The Matrix module is used to prepare for signal separation, and the HCC module 24 is used to correct and compensate the separated components, so as to make the expected value closer to the actual value.

As shown in fig. 6, (3) the main functions of feedback control and modulation are to control and modulate an error signal and output it. The expected value of the previous 2 types of outputs is used as the input of feedback control, error comparison is carried out on the expected value and the actual value of analog-to-digital conversion, a modulation signal is finally obtained by an IIR/PR/PID controller, a modulation pulse is obtained by the modulation signal through a PWM pulse width modulation technology, and the expected value is output through a GPIO to drive a power switch tube.

Certainly, in a scene without feedback control, such as display, the link of the type (3) is not needed, and the positive and negative sequence active, reactive, harmonic and other components of the input ADC signal can be separated only through the links of the type (1) and the type (2), so that the whole process is clear, a user can save a large amount of algorithm programming design by using the chip, and only a configuration program needs to operate according to the links of the type (1) and the type (2).

If a scene of feedback control needs to be carried out, the links of the type (1), the type (2) and the type (3) need to be connected in series to form a whole link, a user only needs to configure a corresponding register, a large amount of algorithm programming design is omitted, and the operation is simple and efficient.

The data structure of each component of the signal obtained by separation by the FFT module 23 is shown in fig. 6, taking 256 input data as an example.

Therefore, the invention realizes angle tracking phase locking through the DFT, ATAN and sine-cosine module 14 arranged in the chip, then realizes frequency spectrum separation through the FFT and HCC arranged in the chip to obtain an expected value, finally realizes compensation control and pulse width modulation through the IIR extended controller and the PWM module arranged in the chip, and drives the power switch tube to act through the external of the GPIO output chip on the PWM pulse, thereby forming an input signal again to enter the GPIO, and then carrying out iterative analysis, calculation and control again through ADC analog-to-digital conversion, and continuously repeating, so that the actual value is continuously close to the expected value.

In addition, the built-in algorithm of the chip can completely realize the functions of the electric energy quality comprehensive treatment scheme of reactive compensation, unbalance adjustment and harmonic treatment, a user does not need to write an algorithm program, the whole work can realize complex functions only by configuring registers of various functional modules as shown in figure 1, and the work difficulty index is reduced.

A user does not need to write an algorithm program, the complex function can be realized only by configuring registers of modules (as shown in the following) in a related schematic diagram in the whole work, and the work difficulty index is reduced.

It should be noted that the above is only a preferred embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept also fall within the protection scope of the present invention.

Claims

1. A microprocessor chip, comprising:

the device comprises a first processing unit and a second processing unit, wherein the first processing unit performs analog-to-digital conversion on a first input signal and calculates to obtain a sine and cosine value of the first input signal, and the second processing unit obtains the sine and cosine value output by the first processing unit and performs analog-to-digital conversion and frequency spectrum separation on a second input signal to obtain an expected value in the input signal.

2. The chip of claim 1, wherein:

the chip further comprises a third processing unit, the third processing unit takes the expected value output by the second processing unit as the input of feedback control, and compares the expected value with the actual value of a third input signal subjected to analog-to-digital conversion to obtain a modulation signal, the modulation signal is subjected to PWM pulse width modulation to obtain PWM pulses, and the PWM pulses are output through the GPIO interface to control the power switch tube.

3. The chip of claim 1, wherein:

4. The chip of claim 1 or 2, wherein:

the first processing unit comprises a first analog-to-digital converter, a DFT module, an ATAN function module and a sine-cosine module, wherein the input end of the first analog-to-digital converter is connected with a first input signal, the output end of the first analog-to-digital converter is connected with the input end of the DFT module, the output end of the DFT module is connected with the input end of the ATAN function module, the output end of the ATAN function module is connected with the input end of the sine-cosine module, and the output end of the sine-cosine module respectively outputs a sine signal and a cosine signal.

5. The chip of claim 1 or 2, wherein:

the second processing unit comprises a second analog-to-digital converter, a first Matrix module, an FFT module, an HCC module, and a second Matrix module, the second analog-to-digital converter is connected to a second input signal, an output end of the second analog-to-digital converter is connected to an input end of the first Matrix module, an output end of the first Matrix module is connected to an input end of the FFT module, an output end of the FFT module is connected to an input end of the HCC module, an output end of the HCC module is connected to an input end of the second Matrix module, the first Matrix module and the second Matrix module receive the positive cosine value, and an output end of the second Matrix module outputs an expected value.

6. The chip of claim 2, wherein:

the third processing unit comprises a third analog-to-digital converter, a controller module and a pulse width modulation module, wherein the input end of the third analog-to-digital converter is connected with a third input signal, the output end of the third analog-to-digital converter is connected with the input end of the controller module, the input end of the controller module receives an error value between an actual value and an expected value of the third input signal after analog-to-digital conversion, the output end of the controller module is connected with the input end of the pulse width modulation module, and the output end of the pulse width modulation module is connected with the GPIO interface.

7. A method for using a microprocessor chip, wherein the microprocessor chip is the microprocessor chip of any one of claims 1 to 6, the method comprising:

step S1, carrying out angle tracking phase locking on the first input signal by using a first processing unit arranged in a chip, and calculating to obtain a sine and cosine value of the first input signal;

and step S2, according to the obtained sine and cosine values, performing analog-to-digital conversion and spectrum separation on the second input signal by using a second processing unit built in the chip to obtain expected values in the input signal.

8. The method of claim 7, further comprising:

and step S3, comparing the error of the expected value output by the second processing unit with the actual value of the third input signal after analog-to-digital conversion, performing compensation control and pulse width modulation by using the third processing unit built in the chip to form PWM pulse, outputting the PWM pulse through the GPIO interface to drive the power switch tube to act, so as to form a new input signal again, entering the GPIO interface of the chip, and repeating the steps to enable the actual value of the new input signal to be close to the expected value continuously.

9. The method according to claim 7 or 8, characterized in that:

the step S1 specifically includes: analog signals of input voltages U1, U2 and U3 are obtained, analog-to-digital conversion is carried out on the input voltages U1, U2 and U3 through a first analog-to-digital converter, the input voltages U1, U2 and U3 are converted into components of two-phase coordinates A and B through a DFT module, a sine and cosine value of any phase of the input voltages U1, U2 and U3 is obtained through calculation of an ATAN function module and a sine and cosine module, and phase angle tracking phase locking of the input voltages U1, U2 and U3 is completed.

10. The method according to claim 7 or 8, characterized in that:

the step S2 specifically includes: the method comprises the steps of obtaining analog signals of input currents I1, I2 and I3, carrying out analog-to-digital conversion on the input currents I1, I2 and I3 through a second analog-to-digital converter, outputting digital signals to a first Matrix module, carrying out Matrix transformation on the first Matrix module according to received sine and cosine values to output Matrix signals to an FFT module, and carrying out spectrum separation through the FFT module and an HCC module to obtain expected values.