CN102694616A - Clock detection circuit, clock circuit and clock exception detection method - Google Patents
Clock detection circuit, clock circuit and clock exception detection method Download PDFInfo
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Abstract
The invention provides a clock detection circuit, a clock circuit and a clock exception detection method, wherein the clock detection circuit comprises a first clock driver, a second clock driver, a logical control unit, a logical switching circuit and a memory, and the logical control unit is used for acquiring configuration information from the memory, respectively carrying out exception detection on clock signals output by the first clock driver and the second clock driver according to the configuration information, and controlling the logical switching circuit to switch the first clock driver and the second clock driver when the clock signal output by the first clock driver is detected to generate an exception and the clock signal output by the second clock driver is further normal, so that the second clock driver provides the clock signal for an exchange chip through the logical switching circuit. According to the technical scheme of the invention, the defect that the detection of a low-frequency clock by using a high-frequency clock is limited is overcome while the redundancy of the clock signal is realized.
Description
Technical field
The present invention relates to the communication technology, relate in particular to a kind of clock detection circuit, clock circuit and clock method for detecting abnormality.
Background technology
All communication systems all are the synchronous logics that drives with at least one dagital clock signal, so the importance of clock signal is unquestionable, any one tunnel clock signal goes wrong, and all can cause the whole communication system can't operate as normal.But practical application shows, the less stable in clock source in order to address this problem, the master/backup clock redundant technique occurred in some communication systems.For example, the telecommunication apparatus of ethernet port is because require to have higher reliability and fault-tolerant ability, so used two-way, master/backup clock source redundancy.
In the master/backup clock redundant technique, through master clock is detected, occur in time accomplishing the switching of backup clock, thereby guaranteeing that to greatest extent business is not interrupted when unusual when detecting master clock.The unusual method of detection clock comparatively commonly used at present is to use high frequency clock to detect low-frequency clock.The detailed process of this method is: adopt a reference clock, with reference clock clock signal to be detected is counted, through judging whether count value to each clock signal to be detected equals preset value and find whether clock signal to be detected takes place unusually.In the method, require the frequency of reference clock to be higher than the frequency of clock to be detected, if can't obtain the reference clock of higher frequency; Then can't detect clock to be detected; This shows that the requirement owing to the reference clock frequency makes the application of this method be restricted.
Summary of the invention
The present invention provides a kind of clock detection circuit, clock circuit and clock method for detecting abnormality, detects the limited defective of low-frequency clock in order to overcome with high frequency clock.
One aspect of the present invention provides a kind of clock detection circuit, comprising: first clock driver, second clock driver, logic control element, logic commutation circuit and memory;
Said first clock driver is connected with said logic commutation circuit with the first clock source, is used for to exchange chip clock signal being provided through said logic commutation circuit; Said second clock driver is connected with said logic commutation circuit with the second clock source, and said logic commutation circuit is connected with said exchange chip;
Said memory is used to store the configuration information that carries out clock signal detection use;
Said logic control element is connected with said memory, said first clock driver, said second clock driver and said logic commutation circuit; Be used for obtaining said configuration information, respectively the clock signal of said first clock driver output and the clock signal of said second clock driver output carried out abnormality detection according to said configuration information from said memory; And it is unusual to know that in detection the clock signal of said first clock driver output takes place; And the clock signal of said second clock source output just often; Control said logic commutation circuit and switch said first clock driver and said second clock driver, so that said second clock driver provides clock signal through said logic commutation circuit to said exchange chip.
The present invention provides a kind of clock method for detecting abnormality on the other hand, comprising:
Obtain and detect the configuration information that clock signal is used;
Respectively the clock signal of first clock driver output and the clock signal of second clock driver output are carried out abnormality detection according to said configuration information; Wherein, the said first clock source is used for to exchange chip clock signal being provided;
If detecting the clock signal of knowing said first clock driver output takes place unusual; And the clock signal of said second clock driver output is normal; Then switch said first clock source and said second clock source, so that said second clock source provides clock signal to said exchange chip.
Another aspect of the invention provides a kind of clock circuit, comprises arbitrary clock detection circuit provided by the invention, the first clock source and second clock source.
Clock detection circuit provided by the invention and clock circuit; Respectively the clock signal in the first clock source and second clock source is divided into two-way and offers logic control element and logic commutation circuit respectively through two clock drivers; Logic control element carries out abnormality detection to the clock signal of two clock driver outputs respectively according to the configuration information that processor provides; And detecting to provide the clock signal of the clock driver output of clock signal to take place unusual when the forward direction exchange chip; And the clock signal of another clock driver output just often; The control logic commutation circuit is switched the two-way clock driver, so that another clock driver provides clock signal to exchange chip, accomplishes the switching of clock signal.Visible by above-mentioned analysis; The present invention is realizing under the redundant situation of clock signal; Use configuration information that clock signal is carried out abnormality detection; The clock signal of no longer as prior art, using the clock source to export is counted high frequency clock and is detected the unusual of clock signal, no longer needs the clock signal of higher frequency, has overcome and has used high-frequency signal to detect the defective that low frequency signal exists.
Description of drawings
The structural representation of the clock detection circuit that Fig. 1 provides for one embodiment of the invention;
The structural representation of the clock detection circuit that Fig. 2 provides for another embodiment of the present invention;
The structural representation of the clock circuit that Fig. 3 provides for one embodiment of the invention;
Fig. 4 A is the flow chart of the clock method for detecting abnormality that provides of one embodiment of the invention;
Fig. 4 B is the flow chart of the clock method for detecting abnormality that provides of another embodiment of the present invention;
The logic control element that Fig. 5 provides for one embodiment of the invention carries out the flow chart of fast detecting to the clock signal of first clock driver or the output of second clock driver in first detection time;
The logic control element that Fig. 6 provides for one embodiment of the invention carries out the flow chart of slow detection to the clock signal of first clock driver or the output of second clock driver in second detection time;
The flow chart of the clock method for detecting abnormality that Fig. 7 provides for further embodiment of this invention;
The contrast sketch map of first detection time that Fig. 8 provides for one embodiment of the invention and the clock signal of 125MHz;
The contrast sketch map of second detection time that Fig. 9 provides for one embodiment of the invention and the clock signal of 125MHz.
Embodiment
The structural representation of the clock detection circuit that Fig. 1 provides for one embodiment of the invention.As shown in Figure 1, the clock detection circuit of present embodiment comprises: first clock driver 11, second clock driver 12, logic control element 13, logic commutation circuit 14 and memory 15.
Wherein, first clock driver 11 is connected with logic commutation circuit 14 with the first clock source, and being used for provides clock signal through logic commutation circuit 14 to exchange chip.Second clock driver 12 is connected with logic commutation circuit 14 with the second clock source, and logic commutation circuit 14 is connected with exchange chip.
Optional, second clock driver 12 is used for clock signal in 11 outputs of first clock driver to be taken place when unusual, to exchange chip clock signal is provided through logic commutation circuit 14.
Wherein, exchange chip can be medium access control (Media Access Control, MAC) chip and/or physics (Physical, a PHY) chip, but be not limited thereto.
In the present embodiment, the first clock source and second clock source backup each other, and that is to say, the clock signal that two clock sources are provided is identical.This means that first clock driver 11 also is identical with the clock signal of second clock driver 12 outputs.Said clock signal is identical to be meant that the parameter (for example frequency, amplitude etc.) of clock signal is identical.
Optional, can use the I2C bus to communicate between logic control element 13 and the memory 15.
Optional, logic control element 13 can switch first clock driver 11 and second clock driver 12 with control logic commutation circuit 14 to logic commutation circuit 14 output switching commands.
By above-mentioned visible, logic commutation circuit 14 mainly is under the control of logic control element 13, and responsible selection inputs to the clock signal of exchange chip.Logic commutation circuit 14 can take place when unusual in the current clock signal that inputs to exchange chip, under the control of logic control element 13, accomplishes the switching of two-way clock signal rapidly, guarantees the professional unaffected of exchange chip to greatest extent.On concrete the realization; Logic commutation circuit 14 can be used the various ripe chips that take over seamlessly that can realize clock signal in the prior art; Can also use simple and lower-cost switching circuit, can also carry out adaptability design according to the function of logic commutation circuit 14 in the present embodiment by the Hardware Engineer.
By above-mentioned visible, first clock driver 11 is divided into two-way with the output that second clock driver 12 is mainly used in the first clock source and second clock source, and one the tunnel offers logic commutation circuit 14, a tunnel offers logic control element 13.On concrete the realization; First clock driver 11 can be the clock driver of the chip manufacturing process production of various employing standards with second clock driver 12; Have the advantage that stability is higher, failure rate is lower, and then improve the reliability of the clock detection circuit of present embodiment.
The logic control element 13 of present embodiment can by CPLD (Complex Programmable Logic Device, CPLD) or be that (Field Programmable Gate Array FPGA) waits realization to field programmable gate array.Wherein, CPLD realizes that cost is lower, is preferred version.
Preferably, logic control element 13 can use on the clock detection circuit device such as existing C PLD to realize that based on this, clock detection circuit need not increase additional circuit again, and its realizations is simple in structure, is easy to realize, the realization cost is lower.
On concrete the realization; Memory 15 can be EEPROM (Electrically Erasable Programmable Read-Only Memory; EEPROM), Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read-Only Memory; EPROM), (Programmable Read-Only Memory PROM) etc., but is not limited thereto programmable read only memory.Wherein, EEPROM is preferred implementation.
Optional, the clock detection circuit of present embodiment can be the circuit of on various ply-yarn drills, realizing with clock detection function.Further optional, logic control element 13 can use the CPLD device that has existed on the ply-yarn drill to realize.
By above-mentioned visible; The clock detection circuit of present embodiment is divided into the clock signal in the first clock source and second clock source two-way and offers logic control element and logic commutation circuit respectively respectively through two clock drivers; Logic control element carries out abnormality detection to the clock signal of two clock driver outputs respectively according to the configuration information that processor provides; And detecting to provide the clock signal of the clock driver output of clock signal to take place unusual when the forward direction exchange chip; And the clock signal of another clock driver output just often; The control logic commutation circuit is switched the two-way clock driver, and making provides clock signal by another road clock driver to exchange chip, accomplishes the switching of clock signal.In the present embodiment; Realizing under the redundant situation of clock signal; Logic control element uses configuration information that clock signal is carried out abnormality detection; The clock signal of no longer as prior art, using the clock source to export is counted high frequency clock and is detected the unusual of clock signal, no longer needs the clock signal of higher frequency, has overcome and has used high-frequency signal to detect the defective that low frequency signal exists.In addition,, make and to carry out abnormality detection to the clock signal of any frequency that no longer receive the restriction of the clock signal frequency that the clock source provides, range of application is wider because the clock detection circuit that provides of present embodiment does not re-use high-frequency signal.
The structural representation of the clock detection circuit that Fig. 2 provides for another embodiment of the present invention.Present embodiment is based on realization embodiment illustrated in fig. 1.As shown in Figure 2, the clock detection circuit of present embodiment also comprises: processor 17.
The processor 17 of present embodiment can be on the clock detection circuit CPU (Central Processing Unit, CPU).
Wherein, processor 17 can carry out information interaction through local bus (LOCAL BUS) and logic control element 13, helps improving the speed of information interaction.
Further, the clock detection circuit of present embodiment can also comprise: exchange chip 16.Exchange chip 16 can be MAC chip and/or the PHY chip on the clock detection circuit that provides of present embodiment, but is not limited thereto.
In the clock redundant technique, modal clock failure has 2 kinds: the unusual saltus step of clock failure of oscillation and clock.Wherein, the unusual saltus step of clock comprises: the clock saltus step accelerates, conversion and several kinds of situation of not saltus step.To above-mentioned two kinds of clock failures, present embodiment provides fast detecting pattern and slow detection pattern, can detect the situation of clock failure of oscillation through the fast detecting module, can detect the situation of the unusual saltus step of clock through the slow detection pattern.
Based on above-mentioned two kinds of detecting patterns, the configuration information of present embodiment can comprise: first detection time, second detection time and count threshold Several Parameters.Wherein, be used to supply logic control element 13 to carry out fast detecting first detection time, first detection time is greater than the cycle of the clock signal of first clock driver 11 or 12 outputs of second clock driver.Suppose that the cycle of the clock signal of first clock driver 11 or second clock driver 12 outputs is T, then first detection time T1 satisfy: T1>T, comparatively preferably can select T1=1.5T, but be not limited thereto.Wherein, Second detection time and count threshold; Be used to supply logic control element 13 to carry out slow detection; Second detection time is greater than the cycle of the clock signal of first clock driver 11 or second clock driver 12 outputs, is specially the product in the cycle of the clock signal that above-mentioned count threshold and first clock driver 11 or second clock driver 12 export.Comparatively preferred, second detection time T2 be generally tens or a hundreds of T.
Based on above-mentioned; With memory 15 is that EEPROM is an example; Table 1 has provided the meaning of each configuration byte of EEPROM interior volume, can dispose different configuration informations respectively to clock signals of different frequencies, also can be to the identical configuration information of clock signal configuration of all frequencies.Whether the flag of EEPROM space beginning is used to identify EEPROM has the programming of carrying out, and is the configuration information to the clock signal configuration of two kinds of frequencies below.As shown in table 1, be the clock signal of 25MHz for frequency, disposed first detection time, second detection time under the slow detection pattern and the count threshold under the slow detection pattern under the fast detecting pattern respectively; For frequency is the clock signal of 125MHz, has disposed first detection time, second detection time under the slow detection pattern and the count threshold under the slow detection pattern under the fast detecting pattern respectively.Here the configuration information with clock signals of different frequencies is not all example.If clock signals of different frequencies is used identical configuration information, then clock frequency can be distinguished in the EEPROM space on concrete the realization.
Table 1
| Flag |
| The 25MHz clock signal |
| First detection time under the fast detecting pattern |
| Second detection time under the slow detection pattern |
| Count threshold under the slow detection pattern |
| The 125MHz clock signal |
| First detection time under the fast detecting pattern |
| Second detection time under the slow detection pattern |
| Count threshold under the slow detection pattern |
| ...... |
Based on above-mentioned; Logic control element 13 is according to configuration information; The clock signal of respectively clock signal and the second clock driver 12 of 11 outputs of first clock driver being exported is carried out abnormality detection and is specially: logic control element 13 specifically is used in first detection time with in second detection time, the clock signal of first clock driver, 11 outputs being counted respectively; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that then the clock signal of first clock driver, 11 outputs takes place unusual; And logic control element 13 is also counted the clock signal of second clock driver 12 outputs in first detection time with in second detection time; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that the clock signal of second clock driver 12 outputs takes place unusual.
Accordingly, if the count value in first detection time is not 0, and the count value in second detection time equals count threshold, explains that the clock signal of clock signal or 12 outputs of second clock driver of first clock driver, 11 outputs is normal.
In this explanation, the process that the clock signal that process that the clock signal that the process that the clock signal that the process that the clock signal that logic control element 13 was exported first clock driver 11 in first detection time detects, logic control element 13 were exported first clock driver 11 in second detection time detects, logic control element 13 were exported second clock driver 12 in first detection time detects and logic control element 13 were exported second clock driver 12 in second detection time detects can be carried out with random order.Illustrate; Logic control element 13 can be provided with four passages simultaneously; In first detection time, the clock signal of first clock driver, 11 outputs and the clock signal of second clock driver 12 outputs are detected simultaneously, meanwhile in second detection time, simultaneously the clock signal of first clock driver, 11 outputs and the clock signal of second clock driver 12 outputs are detected.Perhaps; Logic control element 13 is provided with two passages; In first detection time, simultaneously the clock signal of first clock driver, 11 outputs and the clock signal of second clock driver 12 outputs are detected earlier, and then in second detection time, simultaneously the clock signal of first clock driver, 11 outputs and the clock signal of second clock driver 12 outputs are detected.Perhaps; Logic control element 13 is provided with two passages; The clock signal of at first simultaneously first clock driver 11 being exported in first detection time and in second detection time detects, and then the clock signal of simultaneously second clock driver 12 being exported in first detection time and in second detection time detects.
Wherein, the testing result of logic control element 13 has following several kinds of situation:
First kind of situation, the clock signal of first clock driver, 11 outputs is normal, and the clock signal of second clock driver 12 outputs is normal.In this case, logic control element 13 does not send switching command to logic commutation circuit 14, still to exchange chip 16 clock signal is provided through logic commutation circuit 14 by first clock driver 11.
Second kind of situation: the clock signal of first clock driver, 11 outputs is normal, and the clock signal of second clock driver 12 outputs is unusual.In this case, logic control element 13 does not send switching command to logic commutation circuit 14, still to exchange chip 16 clock signal is provided through logic commutation circuit 14 by first clock driver 11.
The third situation: the clock signal of first clock driver, 11 outputs is unusual, and the clock signal of second clock driver 12 outputs is normal.In this case, logic control element 13 sends switching command to logic commutation circuit 14, to exchange chip 16 clock signal is provided through logic commutation circuit 14 by second clock driver 12.
The 4th kind of situation: the clock signal of first clock driver, 11 outputs is unusual, and the clock signal of second clock driver 12 outputs is unusual.
Optional, logic control element 13 can write above-mentioned various testing results the relevant position of logic control element 13, so that the inquiry of testing result or use etc.
Further, logic control element 13 takes place unusual in the clock signal that detects the output of first clock driver 11, or the clock signal of second clock driver 12 outputs takes place when unusual, can be to processor 17 output interrupt signals.Accordingly, processor 17 reads the also current detection result of stored logic control unit 13 according to interrupt signal, and to outside output alarm information.Preferably, processor 17 can store the current detection result of the logic control element that obtains 13 in the memory 15 into, but is not limited thereto.Wherein, processor 17 obtains the also testing result of stored logic control unit 13, helps supplying the follow-up fault tracing that carries out.Wherein, processor 17 helps the external staff to outside output alarm information and in time knows have clock signal to take place unusually, so that in time carry out malfunction elimination.
Wherein, processor 17 can be to print test results report automatically to the mode of outside output alarm information, also can be to send alarm sound etc.
Optional; Logic control element 13 can compare this testing result and last testing result before processor 17 output interrupt signals, judged whether twice testing result be identical; If comparative result is identical; Then not to processor 17 output interrupt signals, if comparative result is different, then to processor 17 output interrupt signals.Can avoid logic control element 13 to repeat like this, avoid processor 17 to repeat to obtain and store the same detection result, help alleviating the processing burden of logic control element 13 and processor 17 to processor 17 output interrupt signals.
In this explanation; The clock signal of exporting when first clock driver 11 takes place unusual; And by second clock driver 12 after exchange chip 16 provides clock signal; Can carry out malfunction elimination to the clock signal of first clock driver, 11 outputs, for example may replace or proofread and correct the first clock source etc.After the recovering clock signals of first clock driver 11 output is normal; Can replace with again by first clock driver 11 and to exchange chip 16 clock signal is provided, also can not replace still provides clock signal by second clock driver 12 to exchange chip 16.
Further specify; The clock signal of exporting when second clock driver 12 takes place unusual; And the recovering clock signals of first clock driver 11 output normal after; Logic control element 13 can will provide clock signal to replace with by first clock driver 11 to exchange chip 16 by second clock drive circuit 12 and to exchange chip 16 clock signal will be provided through sending switching command to logic commutation circuit 14.
By above-mentioned visible; The clock detection circuit that present embodiment provides; Carry out the unusual detection of clock by logic control element according to configuration information; Processor only needs to write configuration information, obtain and store testing result and output alarm information to memory, need not take a large amount of cpu resources of clock detection circuit; In addition, carry out the clock abnormality detection, no longer need the reference clock of higher frequency, no longer receive the restriction of clock frequency to be detected through configuration information; In addition, logic control element can detect various clock failures through fast detecting and slow detection, and the switching of control logic commutation circuit completion clock signal, can guarantee to greatest extent that the business of exchange chip is not interrupted; Moreover the clock detection circuit that present embodiment provides can be realized that mainly the portability of hardware system is stronger by CPLD, and the user can realize clock signals of different frequencies is carried out abnormality detection through in memory, writing different configuration informations.
The structural representation of the clock circuit that Fig. 3 provides for one embodiment of the invention.As shown in Figure 3, the clock circuit of present embodiment comprises: clock detection circuit 10, the first clock source 20 and second clock source 30.
Wherein, the structure of clock detection circuit 10 and operation principle can repeat no more at this referring to Fig. 1 or description embodiment illustrated in fig. 2.
The first clock source 20 can adopted the clock platelet with second clock source 30 on concrete the realization, and the first clock source 20 backups each other with second clock source 30, that is to say the clock signal that two clock sources are provided identical.Said clock signal is identical to be meant that the parameter (for example frequency, amplitude etc.) of clock signal is identical.
In the present embodiment, the frequency of the clock signal that provides of the first clock source 20 and second clock source 30 is not done qualification.
Further, as shown in Figure 3, the clock circuit of present embodiment also comprises backboard 40.
Concrete, first clock driver 11 of clock detection circuit 10 is connected with the first clock source 20 through backboard 40, and the second clock driver 12 of clock detection circuit 10 is connected with second clock source 30 through backboard 40.
By above-mentioned visible; The clock circuit of present embodiment comprises the clock detection circuit that the embodiment of the invention provides; Realizing that under the redundant situation of clock signal, logic control element uses configuration information that clock signal is carried out abnormality detection, the clock signal of no longer as prior art, using the clock source to export is counted high frequency clock and is detected the unusual of clock signal; The clock signal that no longer needs higher frequency has overcome and has used high-frequency signal to detect the defective that low frequency signal exists.In addition,, make and to carry out abnormality detection to the clock signal of any frequency that no longer receive the restriction of the clock signal frequency that the clock source provides, range of application is wider because the clock detection circuit in the present embodiment does not re-use high-frequency signal.
Fig. 4 A is the flow chart of the clock method for detecting abnormality that provides of one embodiment of the invention.Shown in Fig. 4 A, the method for present embodiment comprises:
In an optional execution mode of present embodiment; Said configuration information comprises: first detection time, second detection time and count threshold; First detection time is greater than the cycle of the clock signal of first clock driver or second clock driver output, the product in the cycle of the clock signal that second detection time, to be count threshold exported with first clock driver or second clock driver.
Based on above-mentioned optional execution mode; A kind of embodiment of step 42 comprises: in first detection time with in second detection time, the clock signal of first clock driver output is counted respectively; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that the clock signal of first clock driver output takes place unusual; In first detection time with in second detection time, the clock signal of second clock driver output is counted respectively; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that the clock signal of second clock driver output takes place unusual.
In an optional execution mode of present embodiment, when the clock signal of the clock signal of first clock driver output or the output of second clock driver takes place when unusual, to outside output alarm information.
Optional, the executive agent of present embodiment can be the logic control element in the clock detection circuit, but is not limited thereto, can also other modules or unit, and CPU etc. for example.
The clock method for detecting abnormality that present embodiment provides; Carry out the configuration information that the clock abnormality detection is used through obtaining; Respectively the clock signal of two clock driver outputs is carried out abnormality detection according to said configuration information then; And detecting to provide the clock signal of the clock driver output of clock signal to take place unusual when the forward direction exchange chip, and the clock signal of another clock driver output is just often, control provides clock signal by another road clock driver to exchange chip; Accomplish the switching of clock signal; Realizing using configuration information that clock signal is carried out abnormality detection under the redundant situation of clock signal, the clock signal of no longer as prior art, using the clock source to export is counted high frequency clock and is detected the unusual of clock signal; The clock signal that no longer needs higher frequency has overcome and has used high-frequency signal to detect the defective that low frequency signal exists.In addition, because the method that provides of present embodiment, do not re-use the clock signal of higher frequency, make and can carry out abnormality detection to the clock signal of any frequency, no longer receive the restriction of the clock signal frequency that the clock source provides, range of application is wider.
Clock detection circuit and clock circuit below in conjunction with the above embodiment of the present invention provides specify the flow process that logic control element carries out the clock abnormality detection.
Fig. 4 B is the flow chart of the clock method for detecting abnormality that provides of another embodiment of the present invention.Shown in Fig. 4 B, the method for present embodiment comprises:
The logic control element of step 401, clock detection circuit obtains from the memory of clock detection circuit and detects the configuration information that clock signal is used.
Wherein, first clock driver is connected with the logic commutation circuit of the first clock source and clock detection circuit, is used for to the exchange chip of clock detection circuit clock signal being provided through the logic commutation circuit.The second clock driver is connected with the logic commutation circuit with the second clock source, is used for clock signal in first clock driver output and takes place to exchange chip clock signal to be provided through the logic commutation circuit when unusual.The logic commutation circuit is connected with exchange chip.
In an optional execution mode of present embodiment, can comprise before the step 401: the processor of clock detection circuit writes above-mentioned configuration information in the memory of clock detection circuit.
In an optional execution mode of present embodiment; Said configuration information comprises: first detection time, second detection time and count threshold; Said first detection time, be the product in the cycle of clock signal count threshold and the output of first clock driver or the output of second clock driver said second detection time greater than the cycle of the clock signal output of first clock driver or the output of second clock driver.
Based on above-mentioned.A kind of optional execution mode of step 402 comprises:
Step 4021, logic control element are counted the clock signal of first clock driver output in first detection time and in second detection time respectively; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that the clock signal of first clock driver output takes place unusual.
Step 4022, logic control element are counted the clock signal of second clock driver output in first detection time and in second detection time respectively; If the count value in first detection time is 0; Perhaps the count value in second detection time is not equal to count threshold, judges that the clock signal of second clock driver output takes place unusual.
As shown in Figure 5, logic control element comprised the process that the clock signal of first clock driver or second clock driver output is carried out fast detecting in first detection time:
Step 501, logic control element are with counter O reset.
Step 502, logic control element were counted the clock signal of first clock driver or the output of second clock driver in first detection time.
Step 503, logic control element judge whether the count value in first detection time is 0; When judged result when being, execution in step 504; When judged result for not the time, execution in step 505.
Step 504, logic control element judge that the clock signal of first clock driver or the output of second clock driver takes place unusual.
Step 505, logic control element judge that the clock signal of first clock driver or the output of second clock driver is normal.
As shown in Figure 6, logic control element comprised the process that the clock signal of first clock driver or second clock driver output is carried out slow detection in second detection time:
Step 601, logic control element are with counter O reset.
Step 602, logic control element were counted the clock signal of first clock driver or the output of second clock driver in second detection time.
Step 603, logic control element judge whether the count value in second detection time equals the count threshold in the configuration information; When judged result for not the time, execution in step 604; When judged result when being, execution in step 605.
Step 604, logic control element judge that the clock signal of first clock driver or the output of second clock driver takes place unusual.
Step 605, logic control element judge that the clock signal of first clock driver or the output of second clock driver is normal.
In the clock method for detecting abnormality that the foregoing description provides; Clock detection circuit is divided into the clock signal in the first clock source and second clock source two-way and offers logic control element and logic commutation circuit respectively respectively through two clock drivers; Logic control element carries out abnormality detection to the clock signal of two clock driver outputs respectively according to the configuration information that processor provides; And detecting to provide the clock signal of the clock driver output of clock signal to take place unusual when the forward direction exchange chip; And the clock signal of another clock driver output just often; The control logic commutation circuit is switched the two-way clock driver, and making provides clock signal by another road clock driver to exchange chip, accomplishes the switching of clock signal; Realizing under the redundant situation of clock signal; Logic control element uses configuration information that clock signal is carried out abnormality detection; The clock signal of no longer as prior art, using the clock source to export is counted high frequency clock and is detected the unusual of clock signal; The clock signal that no longer needs higher frequency has overcome and has used high-frequency signal to detect the defective that low frequency signal exists.In addition, because in the above-described embodiments, clock detection circuit does not re-use the clock signal of higher frequency, makes and can carry out abnormality detection to the clock signal of any frequency, no longer receives the restriction of the clock signal frequency that the clock source provides, and range of application is wider.
The flow chart of the clock method for detecting abnormality that Fig. 7 provides for further embodiment of this invention.Present embodiment is realized based on Fig. 4 B illustrated embodiment.As shown in Figure 7, the method for present embodiment also comprises after step 403:
Optional; Before step 404, logic control element can compare this testing result and last testing result, judges whether twice testing result be identical; If comparative result is identical; Then not to processor output interrupt signal, if comparative result is different, then to processor output interrupt signal.Can avoid logic control element to repeat like this, avoid processor to repeat to obtain and store the same detection result, help alleviating the processing burden of logic control element and processor to processor output interrupt signal.
In the present embodiment, detecting when unusual, logic control element is exported interrupt signal to processor, makes processor according to interrupt signal, obtains and the current detection result of stored logic control unit, helps supplying the follow-up fault tracing that carries out; In addition, processor helps the external staff to outside output alarm information and in time knows have clock signal to take place unusually, so that in time carry out malfunction elimination.
Ethernet mainly contains 25MHz, 125MHz, the equifrequent clock of 156.25MHz at present.Be that 5MHz is an example with clock frequency to be detected below; It with the clock detection circuit ply-yarn drill in the Ethernet; With the logic control element be on the ply-yarn drill CPLD, with the memory be on the ply-yarn drill EEPROM, be that CPU on the ply-yarn drill is an example with the processor, the workflow of clock detection circuit is described.Specific as follows:
At first, ply-yarn drill resets, and the acquiescence first clock source of adopting provides clock signal to the exchange chip on the ply-yarn drill.
Secondly, CPLD reads the configuration among the EEPROM, and at first CPLD reads 2 bytes in EEPROM space.
If the value that reads is 0xFF, judging EEPROM does not have normal programming, and CPLD does not make any handover operation.At this moment, can start CPU EEPROM is carried out programming, promptly write configuration information.
If the value that reads then reads the configuration information among the EEPROM for preset programming value (for example 0x10).In this enforcement, programming in advance is directed against the configuration information of different clock frequencies well among the EEPROM.Because present embodiment is that example describes with the clock signal of 125MHz; Based on this, CPLD selects the corresponding Configuration Values of clock signal of 125MHz from EEPROM, suppose that the result who selects is to be first detection time 15ns; Be 12us second detection time, and count threshold is 1500.
Then, after CPLD reads the configuration information among the EEPROM, respectively the clock signal of two-way 125MHz is detected according to configuration information.Wherein, the testing process to every road signal comprises:
(1) fast detecting pattern, referring to Fig. 8, because be 15ns first detection time, CPLD rising edge of clock signal to 125MHz in the timing time of 15ns is counted, and can count 1 count value at least.If in 15ns inside counting value is 0, judge that then failure of oscillation possibly take place clock.
(2) slow detection pattern, referring to Fig. 9, because be 12us second detection time, the rising edge of clock signal of CPLD 125MHz in the time of 12us is counted, and can obtain out 1500 count values in theory.If actual count value and count threshold are inconsistent, judge that unusual saltus step has appearred in clock.In this explanation, count threshold can be configured through EEPROM, can be determined value, also can be configured to a scope.
Then, according to detection case, produce following 4 kinds of test results, ply-yarn drill is taked corresponding counter-measure.
1) clock signal that provides of the first clock source is normal, and the clock signal that the second clock source provides is normal, and CPLD keeps the first clock source of employing provides clock signal to exchange chip.
2) clock signal that provides of the first clock source is normal; The clock signal that the second clock source provides is unusual; CPLD output interrupt signal notice CPU, CPU reads the clock abnormal information that CPLD obtains, the corresponding warning message of printout; And the clock abnormal information stored among the EEPROM, supply follow-uply to recall.If fault is not got rid of always, CPLD continues to detect same clock abnormal information, then no longer exports interrupt signal and gives CPU, and CPU is not Reduplicated to write EEPROM with same clock abnormal information.
3) clock signal that provides of the first clock source is unusual, and the clock signal that the second clock source provides is normal, and the logic commutation circuit on the CPLD control ply-yarn drill is accomplished the switching of two-way clock signal rapidly, guarantees the professional unaffected of exchange chip to greatest extent.Simultaneously, CPLD output interrupt signal notice CPU, CPU reads the clock abnormal information that CPLD obtains, and prints and exports corresponding warning message, and the clock abnormal information is stored among the EEPROM, supplies follow-uply to recall.If fault is not got rid of always, CPLD continues to detect same clock abnormal information, no longer exports interrupt signal and gives CPU, and CPU is not Reduplicated to write EEPROM with same clock abnormal information.
4) clock signal that provides of the first clock source is unusual; The clock signal that the second clock source provides is unusual; CPLD output interrupt signal notice CPU, CPU reads CPLD and obtains the clock abnormal information, prints and export corresponding warning message; And the clock abnormal information stored among the EEPROM, supply follow-uply to recall.If fault is not got rid of always, CPLD continues to detect same clock abnormal information, no longer exports interrupt signal and gives CPU, and CPU is not Reduplicated to write EEPROM with same clock abnormal information.
Present embodiment has following beneficial effect: 1, hardware circuit only need utilize device such as original CPU and CPLD realization on the ply-yarn drill.CPU only need report to the police when clock signal is unusual or the EEPROM of sky is carried out programming, and remaining work is then accomplished by CPLD fully, does not take a large amount of cpu resources.2, can make detection to situation such as clock failure of oscillation and the unusual saltus steps of clock, can be very fast on the hardware make switching, guarantee that ply-yarn drill is normal professional unaffected.3, hardware system is portable strong, and the user can carry out flexible configuration according to actual needs through programming EEPROM.4, the clock that does not need higher frequency has overcome the defective when using the higher frequency clock that the low frequency clock is carried out abnormality detection.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each method embodiment can be accomplished through the relevant hardware of program command.Aforesaid program can be stored in the computer read/write memory medium.This program the step that comprises above-mentioned each method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
What should explain at last is: above each embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although the present invention has been carried out detailed explanation with reference to aforementioned each embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, perhaps to wherein part or all technical characteristic are equal to replacement; And these are revised or replacement, do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (10)
1. a clock detection circuit is characterized in that, comprising: first clock driver, second clock driver, logic control element, logic commutation circuit and memory;
Said first clock driver is connected with said logic commutation circuit with the first clock source, is used for to exchange chip clock signal being provided through said logic commutation circuit; Said second clock driver is connected with said logic commutation circuit with the second clock source, and said logic commutation circuit is connected with said exchange chip;
Said memory is used to store the configuration information that carries out clock signal detection use;
Said logic control element is connected with said memory, said first clock driver, said second clock driver and said logic commutation circuit; Be used for obtaining said configuration information, respectively the clock signal of said first clock driver output and the clock signal of said second clock driver output carried out abnormality detection according to said configuration information from said memory; And take place unusual in the clock signal that detects said first clock driver output; And the clock signal of said second clock source output just often; Control said logic commutation circuit and switch said first clock driver and said second clock driver, so that said second clock driver provides clock signal through said logic commutation circuit to said exchange chip.
2. clock detection circuit according to claim 1; It is characterized in that; Said configuration information comprises: first detection time, second detection time and count threshold; Said first detection time is greater than the cycle of the clock signal of said first clock driver or said second clock driver output, the product in the cycle of the clock signal that said second detection time, to be said count threshold exported with said first clock driver or said second clock driver;
Said logic control element specifically is used in said first detection time with in said second detection time, the clock signal of said first clock driver output being counted respectively; If the count value in said first detection time is 0; Perhaps the count value in said second detection time is not equal to said count threshold; The clock signal of judging said first clock driver output takes place unusual; And in said first detection time with in said second detection time, the clock signal of said second clock driver output is counted; If the count value in said first detection time is 0, perhaps the count value in said second detection time is not equal to said count threshold, judges that the clock signal of said second clock driver output takes place unusual.
3. clock detection circuit according to claim 1 and 2 is characterized in that, also comprises:
Processor is connected with said memory through said logic control element, is used for writing said configuration information to said memory.
4. clock detection circuit according to claim 3; It is characterized in that; The clock signal in the clock signal of said first clock driver output or the output of said second clock driver of also being used for said logic control element takes place when unusual, to said processor output interrupt signal;
Said processor also is used for reading and store the current detection result of said logic control element according to said interrupt signal, and to outside output alarm information.
5. clock detection circuit according to claim 1 and 2 is characterized in that, also comprises: said exchange chip.
6. a clock method for detecting abnormality is characterized in that, comprising:
Obtain and detect the configuration information that clock signal is used;
Respectively the clock signal of first clock driver output and the clock signal of second clock driver output are carried out abnormality detection according to said configuration information; Wherein, the said first clock source is used for to exchange chip clock signal being provided;
If detecting the clock signal of knowing said first clock driver output takes place unusual; And the clock signal of said second clock driver output is normal; Then switch said first clock source and said second clock source, so that said second clock source provides clock signal to said exchange chip.
7. clock method for detecting abnormality according to claim 6; It is characterized in that; Said configuration information comprises: first detection time, second detection time and count threshold; Said first detection time is greater than the cycle of the clock signal of said first clock driver or said second clock driver output, the product in the cycle of the clock signal that said second detection time, to be said count threshold exported with said first clock driver or said second clock driver;
The said clock signal of respectively clock signal and the second clock driver of the output of first clock driver being exported according to said configuration information is carried out abnormality detection and is comprised:
In said first detection time with in said second detection time, the clock signal of said first clock driver output is counted respectively; If the count value in said first detection time is 0; Perhaps the count value in said second detection time is not equal to said count threshold, judges that the clock signal of said first clock driver output takes place unusual;
In said first detection time with in said second detection time, the clock signal of said second clock driver output is counted respectively; If the count value in said first detection time is 0; Perhaps the count value in said second detection time is not equal to said count threshold, judges that the clock signal of said second clock driver output takes place unusual.
8. according to claim 6 or 7 described clock method for detecting abnormality, it is characterized in that, also comprise:
When the clock signal of the clock signal of said first clock driver output or the output of said second clock driver takes place when unusual, to outside output alarm information.
9. a clock circuit is characterized in that, comprising: each described clock detection circuit of claim 1-5, the first clock source and second clock source.
10. clock circuit according to claim 9 is characterized in that, also comprises: backboard;
First clock driver of said clock detection circuit is connected with the said first clock source through said backboard; The second clock driver of said clock detection circuit is connected with said second clock source through said backboard.
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| CN106066817A (en) * | 2016-05-30 | 2016-11-02 | 珠海市微半导体有限公司 | clock monitoring circuit and method thereof |
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| CN113448381A (en) * | 2021-05-28 | 2021-09-28 | 山东英信计算机技术有限公司 | CPLD working clock keeping method, system, storage medium and device |
| CN114261354A (en) * | 2021-12-24 | 2022-04-01 | 南京英锐创电子科技有限公司 | Low-frequency clock circuit and control method |
| CN114261354B (en) * | 2021-12-24 | 2023-07-04 | 南京英锐创电子科技有限公司 | Low frequency clock circuit and control method |
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Address after: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee after: RUIJIE NETWORKS Co.,Ltd. Address before: Cangshan District of Fuzhou City, Fujian province 350002 Jinshan Road No. 618 Garden State Industrial Park 19 floor Patentee before: Beijing Star-Net Ruijie Networks Co.,Ltd. |