JP3139738B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit having fault tolerance, and more particularly to a technique for improving the reliability of a logic circuit by a programmable logic circuit.

[0002]

2. Description of the Related Art With the development of computer technology in recent years, computers have penetrated into every corner of society, and the reliability and fault-tolerance (fault tolerance) of a computer system and an integrated circuit as a component thereof have been improved. Increasingly required.

[0003] The method of implementing a fault-tolerant circuit is described in detail in, for example, publications (by Yoshihiro Toma, Takashi Minatani and Hideo Fujiwara, "Configuration and Design of Fault-Tolerant Systems", Maki Shoten, 1991).

In order to realize the fault tolerance of a circuit, it is first necessary to detect the occurrence of a circuit failure. When a failure occurs, an indication of the occurrence of the failure, a stop of the circuit operation, a recovery of data, a restoration of a circuit function, etc. are performed according to the required reliability and fault tolerance.

Conventionally, in a memory circuit, fault tolerance has been realized by replacing a failed memory cell with a redundant memory cell, encoding data with an error correction code, storing the data, and correcting the error at the time of reading. .

On the other hand, although there is no general-purpose method for a logic circuit such as a memory circuit, there has been a self-checking circuit that detects a failure by itself as a method widely used conventionally. This self-checking circuit is realized mainly by configuring a logic circuit with an error detection code such as an m-out-of-n code. The presence or absence of a failure can be determined by observing whether the output of the circuit is a codeword or a non-codeword.

[0007] A method of configuring a fault-tolerant logic circuit using a self-checking circuit can be generally classified into the following two methods.

(1) The first method is a method in which the entire circuit is constituted by a self-checking circuit using a redundant code. The occurrence of a failure is detected by a failure detection circuit connected to the output of the circuit.

(2) A second method is to mount a plurality of the same circuits and compare their outputs by a self-checking comparator.

In any of the methods, in order to enable the function of the circuit to be restored when a permanent failure occurs, it is necessary to add a redundant circuit dedicated to the circuit in place of the failure. . When a failure occurs, the circuit in which the failure occurred is separated by a selector circuit, and the majority output is taken by a majority function circuit to mask an erroneous output caused by the failure.
Perform circuit function recovery.

[0011]

In the prior art described above, in order to realize a fault-tolerant logic circuit, it is necessary to newly design a circuit for fault-tolerant operation for each target circuit. Therefore, there is a problem that the design cost increases.

Also, in order to enable recovery of the circuit function when a permanent failure occurs in the circuit, it is necessary to prepare an alternative identical circuit. In order to cope with a plurality of faults, the same redundant circuit as a substitute must be prepared by the number of the faults, so that there is a problem that the required circuit amount increases.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a fault-tolerant logic circuit that does not require a special circuit design for fault-tolerance. .

Another object of the present invention is to provide a highly reliable programmable logic circuit.

Still another object of the present invention is to provide a fault-tolerant logic circuit having a small circuit amount and capable of recovering a circuit function even when a plurality of faults occur.

[0016]

According to the present invention, there is provided a programmable logic circuit comprising a plurality of programmable logic cells each comprising a self-checking circuit. Achieved by logic circuits.

[0017]

[0018]

[0019]

[0020]

The outline of the present invention will be described below. The present invention realizes a fault-tolerant logic circuit by configuring a programmable logic circuit with a plurality of programmable logic cells realized by a self-checking circuit. The self-checking programmable logic cell autonomously detects its own fault, and the result is transmitted to the control circuit when the fault occurs. The control circuit at the time of occurrence of the failure outputs the presence or absence of the failure to the outside based on the result.

When a failure occurs, the clock signal for operating the flip-flop included in the self-checking programmable logic cell is stopped to prevent propagation of data contamination due to the failure. If the failure is temporary, the process is resumed by operating the clock signal again when the failure is resolved. In addition, by stopping the clock signal when a failure occurs before the value stored in the flip-flop incorporated in the self-checking programmable logic cell changes, it is possible to prevent the failure of the processing result up to that time due to the failure. As a result, it is possible to continue the processing using the processing result until the occurrence of the failure. A clock signal whose phase is ahead of the clock signal to be stopped is separately generated, a failure is detected based on the clock signal, and the clock signal is stopped before the flip-flop stores data contaminated by the failure.

When the program information of the programmable logic circuit is stored in a rewritable memory, the function of the logic cell in which a permanent failure has occurred is replaced by a normal logic cell by providing means for reprogramming. As a result, the failure can be repaired, and the circuit function before the failure can be restored. A unique address is assigned to all the rewritable memories storing the program information, and the means for reprogramming specifies the address of the memory to be read, reads the contents of the memory, and specifies the address of the memory to be written. Reprogramming is performed by writing the contents of the memory read out earlier.

In addition to the rewritable memory for storing the program information, a unique address is assigned to the flip-flop incorporated in the programmable logic cell, so that the contents stored in the flip-flop in the same procedure as the rewritable memory. Can also read and write.

The failure detection result of the self-checking programmable logic cell is collected in a row or column of the self-checking programmable logic cell and transmitted to a means for reprogramming in a unit of row or column. The reprogramming means performs data transfer in units of rows or columns based on the failure detection results transmitted in units of rows or columns of the logic cell. A row or column of unused redundant logic cells is prepared for fault repair, and the used logic between the row or column of the logic cell containing the failed logic cell and the row or column of the redundant logic cell is prepared. The fault is repaired by moving the cell row or column in parallel by the above data transfer toward the redundant logic cell row or column.

The self-checking programmable logic cell separately checks the input from the row direction and the input from the column direction to separately detect the failure of the logic cell adjacent in the row direction and the failure of the logic cell adjacent in the column direction. To detect. The means for reprogramming thereby determines whether to perform data transfer in the row direction or the column direction.

By using the fault tolerant logic circuit according to the present invention, a circuit designer can use a conventional FPGA.
Just by mapping the target circuit in the same manner as in the above, a fault-tolerant logic circuit can be obtained.

That is, no special knowledge on fault tolerant and no special design for fault tolerant operation are required. In the case where the program information is stored in a rewritable memory, the failure can be repaired by transferring the function of the failed logic cell to an unused logic cell. When a plurality of faults can be repaired, the number of redundant circuits can be reduced as compared with the prior art method of preparing a dedicated redundant circuit.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. In a preferred embodiment of the present invention, a fault-tolerant logic circuit is constituted by a programmable logic circuit realized by a self-checking circuit.

In a memory circuit, a versatile and practical fault-tolerant method such as an error-correcting code exists largely due to its structure in which the same circuits are regularly arranged. On the other hand, as a logic circuit having a regular structure, a Field Programmable Gate Array (FPGA) is used.
ay) and other programmable logic circuits. FPGA is
A desired circuit function is realized by connecting a plurality of programmable logic cells whose functions are programmable by a programmable wiring, and the program information is held in a state of, for example, a built-in memory or a fuse. .

In the preferred embodiment of the present invention, a fault-tolerant logic circuit can be realized without depending on a circuit to be mounted, by configuring each programmable logic cell of the FPGA with a self-checking circuit. .

FIG. 1 is a block diagram for explaining a configuration principle of a fault-tolerant logic circuit according to an embodiment of the present invention.

Referring to FIG. 1, in an embodiment of the present invention, a fault-tolerant logic circuit 4 includes a self-checking programmable logic cell array in which a plurality of programmable logic cells 1 realized by a self-checking circuit are connected to each other. 2 and a control circuit 3 when a failure occurs.

The functions of the self-checking programmable logic cell 1 and the wiring between them are programmed by the state of a built-in memory or a fuse to realize a desired circuit function.

When a failure occurs in the self-checking programmable logic cell 1, the occurrence of the failure is detected by its self-checking property.

Next, the occurrence of the failure is transmitted to the control circuit 3 at the time of occurrence of the failure. The control circuit 3 responds to the failure by transmitting a notification of the occurrence of the failure to the outside or performing a predetermined control operation such as stopping the clock signal of the logic cell array 2.

The program information is stored in a static
Random access memory (SRAM: Static Rando)
(m Access Memory), the logic cell and the wiring can be reprogrammed. That is, by reprogramming the function of the failed logic cell from outside the control circuit 3 or the fault-tolerant logic circuit 4 to replace the function of the failed logic cell with a normal logic cell, the failure can be repaired.

FIG. 2 is a diagram showing an example of the configuration of the fault tolerant logic circuit 4 according to the first embodiment of the present invention.

Referring to FIG. 2, a self-checking programmable logic cell array (hereinafter referred to as "logic cell array")
2) are composed of a plurality of self-checking programmable logic cells (hereinafter referred to as “logic cells”) 1 connected to each other and a signal line C1 for transmitting occurrence of a fault.

For the configuration of the self-checking programmable logic cell 1, see, for example, the description of the above publication ("Composition and Design of Fault Tolerant System" by Yoshihiro Toma, Takashi Minatani, Hideo Fujiwara, Maki Shoten, 1991). In this embodiment, various types of self-checking circuits as disclosed in this publication can be used.

The function of the logic cell 1 is programmed by the state of the memory and the fuse incorporated therein, and realizes a desired circuit function.

When a failure occurs in a certain logic cell 1, the failure is immediately detected by its self-checking property,
The occurrence of a failure is transmitted to the outside of the circuit via the signal line C1.
The system outside the fault tolerant logic circuit 4 is:
The occurrence of a failure can be known from the signal line C1, and the failure can be dealt with. When the program information of the logic cell 1 is held in a rewritable memory such as an SRAM, the function of the failed logic cell is reprogrammed from the outside so as to be transferred to a normal logic cell, thereby restoring the circuit function. You can also.

As a result, according to the embodiment of the present invention,
A circuit designer can obtain the above-described self-checking logic circuit only by mapping a target circuit to a logic cell, similarly to a normal FPGA.

The signal line C1 may be constituted by a bus line as shown in FIG. 2, or may be a wired-OR.
A circuit or a wired-AND circuit may be used. Alternatively, as shown in FIG. 3, an OR circuit may be used, and an AND circuit or another gate element may be used. Further, by performing error detection coding on the signal line C1 itself, the signal line C1
One fault can be detected.

FIG. 4 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 4, a second embodiment of the present invention is different from the first embodiment of the present invention shown in FIG.
A clock control circuit 7 is added.

The signal line C1 for transmitting the failure detection of the self-checking logic cell array 2 is connected to the clock control circuit 7 and the outside. The clock control circuit 7 generates two internal clock signals CCLK and SCLK from the external clock signal CLK externally input to the signal line C4, and outputs them to the signal lines C2 and C3, respectively. Clock signal SCLK is used as a clock signal for controlling the failure detection circuit of logic cell 1. The clock signal C
CLK is input to the flip-flop of logic cell 1,
It enables the logic cell array 2 to provide the function of a sequential circuit.

When the occurrence of a failure in the logic cell array 2 is transmitted by the signal line C1, the clock control circuit 7 stops supplying the clock signal CCLK, thereby preventing the influence of the failure from being propagated.

FIG. 5 is a timing waveform chart showing the operation of the fault-tolerant logic circuit 4 according to the second embodiment of the present invention shown in FIG. Referring to FIG.
Is an external clock signal, and SCLK, CCLK
Are two clock signals generated by the above-described clock control circuit 7, and SCLK and CCLK have the same frequency and the same phase. X0 to Xn and Y0 to Yn represent the states of signal lines in the sequential circuit realized in the logic cell array 2 (X0 to Xn and Y0 to Yn will be described later). C1 is a signal line indicating the presence or absence of a failure in the logic cell array 2. In this embodiment, it is assumed that logic "0" indicates no failure and logic "1" indicates failure.

Generally, an arbitrary sequential circuit can be represented by a model as shown in FIG. Referring to FIG. 7, flip-flops F0 to Fn are connected to signal lines X0 to Xn (combination circuit 8) at the rising timing of clock signal CCLK.
Is output to the signal lines Y0 to Yn, and the value is held until the next rising of the clock signal CCLK.

The values of the signal lines Y0 to Yn determine the next values of the signal lines X0 to Xn through the combination circuit 8.

After the signal lines Y0 to Yn change, the signal line X
There is a delay time t before 0 to Xn is determined (see t in FIG. 5). If the cycle of the clock signal CCLK is not longer than the delay time t, the sequential circuit does not operate as expected.

In FIG. 5, the knitted line portions X0 to Xn (cross-hatched portions) 100 are Y0 to Yn.
The value within the time t after the change of n indicates an indefinite region.

After the values of X0 to Xn are determined (the portion where the values are determined in FIG. 5 is indicated by 101), the clock signal C
At the rising edge of CLK, the value is stored in the flip-flop, and the values of the signal lines Y0 to Yn change.

When a failure occurs in a certain logic cell 1 of the logic cell array 2, the value of the signal lines X0 to Xn may not be fixed to the correct value by the next rising of the clock signal CCLK due to its influence.

When the failure detection circuit incorporated in the self-checking logic cell 1 observes that the values of X0 to Xn are incorrect at the rising timing of the clock signal SCLK, it determines that a failure has occurred. , The occurrence of a failure is transmitted to the clock control circuit 7 via the signal line C1. The clock control circuit 7 stops the clock signal CCLK by seeing that the signal line C1 has changed to logic "1",
Prevent further erroneous circuit operation due to failure.

At the timing of the clock signal SCLK shown in FIG. 5, since an incorrect value of X0 to Xn is stored in the flip-flop at the time of failure, the operation result stored in the flip-flop up to that point is destroyed. Will be.

FIG. 6 is a waveform diagram showing another timing of clock signal SCLK. At tc in the figure, the signal line C1 changes after the failure is detected by the logic cell 1,
3 shows a delay time until the clock control circuit 7 stops the clock signal CCLK.

Referring to FIG. 6, clock signal SCLK
Has the same frequency as the clock signal CCLK, but its phase is advanced by more than the delay time tc for stopping the clock. Thus, when a failure is detected at the rising timing of clock signal SCLK, clock signal CCLK
The clock signal CCLK can be stopped before the next rising of CLK. For this reason, the flip-flop is kept holding the normal data before the data is contaminated by the fault, and after repairing the fault by reprogramming the logic cell array 2 or the like, the held data is used to perform processing. Can be continued.

In the case where the failure is temporary as in the example shown in FIG. 6, after the failure is resolved, the process can be continued by operating the clock signal CCLK again. However, in this case, the cycle time required for the circuit operation is increased by the clock stop delay time tc.

FIG. 8 is a diagram showing a configuration of the third embodiment of the present invention, which is obtained by further adding a restoration control circuit 9 to the second embodiment shown in FIG.

Referring to FIG. 8, programming information of logic cell 1 constituting logic cell array 2 is stored in a built-in rewritable memory. The signal line C1 output from the logic cell array 2 for transmitting the occurrence of a fault is output to the repair control circuit 9 and the outside.

The signal line C7 for controlling the clock control circuit 7 is output from the repair control circuit 9 and input to the clock control circuit 7 via the signal line C7.
Is used to control the operation of the clock control circuit. The signal line C3 of the clock signal SCLK is also input to the repair control circuit 9, and the repair control circuit 9
It operates at the timing given to CLK.

The program information output from the logic cell array 2 is input to the repair control circuit 9 through the signal line C5, and enables the repair control circuit 9 to read the program information of the logic cell array 2. The repair control circuit 9
Is input to the logic cell array 2 through the signal line C6, and enables the repair control circuit 9 to program the logic cell array 2.

When the occurrence of a failure is notified by the signal line C1, the repair control circuit 9 sends the signal line C to the clock control circuit 7.
7, the stop of the clock signal CCLK is instructed, whereby the clock control circuit 7 stops supplying the clock signal CCLK.

Next, the repair control circuit 9 outputs the clock signal SC
Wait for several cycles of LK and check if the failure is temporary
It is determined whether the failure is permanent.

In other words, after waiting for several cycles of the clock signal SCLK, if the failure is resolved and the value of the signal line C1 indicates normal, the repair control circuit 9 sends a signal to the clock control circuit 7 through the signal line C7. To restart the operation of the clock signal CCLK.

On the other hand, if after a wait of several cycles of the clock signal SCLK, the failure is not resolved and the value of the signal line C1 still indicates the occurrence of the failure, it is determined that the failure is permanent, and the failure is repaired. The control circuit 9 starts repairing the fault by reprogramming the logic cell array 2. The repair of the failure is performed by transferring the program information of the failed logic cell to a normal logic cell. When the repair of the failure is completed, the repair control circuit 9 sends the clock signal CCLK to the clock control circuit 7 through the signal line C7.
To restart the operation of.

FIG. 9 shows a first example of a reprogramming method for repairing a fault in this embodiment.
Referring to FIG. 9, the logic cell array 2 including the failed logic cell is replaced with the normally used logic cells 10, 13, and 14.
And unused redundant logic cells 11 and failed used logic cells 12. Some unused redundant logic cells 11 are prepared for repair.

In the reprogramming, first, the contents of the memory built in the logic cell 10 which determines the function of the normal logic cell 10 are transferred to the memory of the unused redundant logic cell 11 so that the normal logic cell 10 The circuit functions of 10 are transferred to unused redundant cells 11.

Next, the wiring between the logic cell 10 and the logic cell 14 (see FIG. 9A) is changed by rewriting the memory for programming the wiring, so that the wiring between the logic cell 14 and the logic cell 11 is changed. (See FIG. 9B).

Similarly, by transferring the contents of the memory that determines the function of the failed logic cell 12 to the memory of the unused logic cell 10 by transferring the function to the unused logic cell 11, The circuit function of the failed logic cell 12 is transferred to the logic cell 10.

Next, the wiring between the logic cell 12 and the logic cell 13 (see FIG. 9A) is changed by rewriting the memory for programming the wiring, so that the wiring between the logic cell 13 and the logic cell 10 is changed. (See FIG. 9B).
By the data transfer between the memories as described above, the failure is repaired and the circuit function of the logic cell array 2 is restored.

FIG. 10 shows a second example of a reprogramming method for repairing a fault. Row 1 of unused logic cells consisting of unused redundant logic cells 11 for fault recovery
Prepare one or more lines of 5. The repair of the failure is performed by transferring the function of the row 17 of the logic cell including the logic cell 12 in which the failure has occurred to the row 15 of the unused logic cell.

First, the contents of the memory of the logic cell included in the used logic cell row 16 are transferred to the memory of the corresponding logic cell of the unused logic cell row 15. As a result, the function of the logic cell row 16 is transferred to the unused logic cell row 15, and the logic cell row 16 becomes unused.

Next, similarly, the failed logic cell 12
Are transferred to the logic cell row 16 by transferring data between memories.

Finally, the logic cell rows 18 and 17
And finally, logic cell row 16 and logic cell row 1
7 is reconnected to the wiring between the logic cell row 18 and the logic cell row 16 by rewriting the memory storing the program information of the wiring.

With the above operation, the repair of the failure is completed.
The circuit function of the logic cell array 2 is restored. In this repair example, the logic cell row 17 including the failed logic cell 12 is used.
The normal logic cell included in the above can not be used due to the repair of the failure, but the reprogramming of the wiring is simpler than the first repair example shown in FIG.
There is an advantage that the required amount of wiring resources of the logic cell array 2 and the circuit amount of the repair control circuit 9 can be reduced.

In this repair example, repair is performed in the column direction for each row of the logical cell array. However, an unused redundant logic cell may be prepared in the column direction and repaired in the row direction. further,
By preparing a plurality of unused redundant logic cell columns, a plurality of faults can be repaired.

Data transfer between memories is performed by providing a wiring for data transfer between memories between adjacent logic cells and controlling the repair control circuit 9 to transfer data from which logic cell to which logic cell. It can be carried out. Also,
For memory access, data transfer may be performed using an interface similar to that of a normal random access memory. A unique address is assigned to the memory of each logic cell.

The repair control circuit 9 gives the address of the memory of the logic cell to be read to the logic cell array 2 and reads the memory contents from the logic cell array 2. Next, the repair control circuit 9 gives the address of the logical cell to be written to the logical cell array 2, and writes the previously read data to the memory of the target logical cell. Also, when repairing,
If not only the contents of the memory that stores the logic cell functions and wiring program information but also the contents that are stored in the flip-flops built into the logic cells can be transferred, the processing before the failure occurs can be repaired. It is possible to continue as it is later.

The repair method is not limited to the above two methods as long as the circuit function of the logic cell array before the failure can be restored.

[0082]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in order to explain the present invention in more detail. FIG. 11 is a diagram illustrating an example of the configuration of the above-described third embodiment of the present invention as an example of the present invention.

Referring to FIG. 11, a self-checking programmable logic cell array 2 in which a plurality of self-checking programmable logic cells 1 are arranged on an array, a clock control circuit 7 and a repair control circuit 9 are provided. . Signal lines C26 to C output from logic cell array 2
35 is connected to the restoration control circuit 9 and the logic cell array 2
Signals the occurrence of a failure. Clock control circuit 7 from outside
The clock control circuit 7 receives the two clock signals CCLK and SCLK at the timing shown in FIG.
Generate. The clock signal CCLK is input from the clock control circuit 7 to the logic cell array 2 via the signal line C2, and is used as a clock signal of a flip-flop incorporated in the logic cell 1.

The clock signal SCLK is input from the clock control circuit 7 to the logic cell array 2 and the repair control circuit 9 via the signal line C3, and is used to give a timing for detecting a failure of the logic cell 1 or used as a clock signal for the repair control circuit. The address line C20 is connected to the external or repair control circuit 9
Are input to the logic cell array 2 to determine the address of the memory in which the programming information is written when programming the logic cell 1. The data line C22 is input to the logic cell array 2 from outside or from the repair control circuit 9, and transmits data to be written to an address specified by the address line C20. The data line C21 is input from the logical cell array 2 to the repair control circuit 9, and is used to read the contents of the address specified by the address line C20.

FIG. 12 is a diagram showing an example of the configuration of the logic cell 1 as one embodiment of the present invention. Referring to FIG. 12, logic cell 1 is implemented by two-wire logic to enable self-checking of a fault, and the same circuit is mounted for each of a positive line and a negative line. D flip-flop 24 with memory interface, 4-input lookup table 25, 2-wire code checker 2
6; a multiplexer 27; and an SRAM 29 for storing program information.

Logic cell 1 has four inputs (EI, EIB), (WI, WIB) from four adjacent logic cells,
(NI, NIB), (SI, SIB), and four outputs (EO, EOB) to four adjacent logic cells, (W
O, WOB), (NO, NOB) and (SO, SOB). Each input and output is composed of two lines, a positive line and a negative line, based on a two-wire code.

These four inputs are input to look-up table 25. As the look-up table 25, there are two look-up tables for a positive line and a negative line. The look-up table 25 interprets the four inputs as addresses of the connected SRAM 29 and outputs the corresponding contents of the SRAM 29. By changing the contents of the SRAM 29, an arbitrary four-input logic function can be realized.

The output of the lookup table 25 is input to the flip-flop 24 and the multiplexer 28.
The multiplexer 28 determines whether to output the output of the look-up table 25 as it is or to output it after storing it in the flip-flop 24, based on the contents of the connected SRAM 29.

The output of the multiplexer 28 is input to the multiplexer 27. The multiplexer 27 has four outputs (EO, EOB), (WO, WOB),
Inputs (EI, EIB), (WI, WIB), (NI, NI) for (NO, NOB) and (SO, SOB)
B) The SR connected whether to output (SI, SIB) as it is or to output the output from the multiplexer 28
Determined based on the contents of AM29.

As described above, the function of logic cell 1 is SR
It is programmed according to the contents of AM29. SRAM 29
Are individually assigned addresses in the logic cell array 2 and can be read and written in the same manner as a normal SRAM.

The interconnection between the logic cells 1 is as shown in FIG. That is, in the figure, the output (SO, SOB) of the logic cell adjacent to the upper side and the input (NI, NIB) of the own logic cell, and the input (S, S) of the logic cell adjacent to the upper side
I, SIB) and the output (NO, NOB) of the own logic cell, the output (NO, NOB) of the lower adjacent logic cell and the input (SI, SIB) of the own logic cell, the lower adjacent logic cell (NO, NOB). The inputs (NI, NIB) and the outputs (SO, S
OB), the output of the logic cell adjacent to the right side (WO, WO
B) and its own logic cell inputs (EI, EIB), the right adjacent logic cell inputs (WI, WIB) and its own logic cell outputs (EO, EOB), and the left adjacent logic cell outputs (EO, EOB). EOB) and the input of its own logic cell (WI, WI
B) Input of the logic cell adjacent to the left side (EI, EIB)
And the outputs (WO, WOB) of the own logic cell are connected.

Referring again to FIG. 12, four inputs (E
I, EIB), (WI, WIB), (NI, NIB),
And (SI, SIB) are the inputs (EI, EIB) from the adjacent logic cells in the row direction, (WI, WIB) and the inputs (NI, NIB) from the adjacent logic cells in the column direction, (S
I, SIB) are input to the two-wire code checker 26.

The two-wire type code checker 26 outputs (EI, EIB) at the rising timing of the clock signal SCLK.
(WI, WIB), (NI, NIB), (SI, SI
By determining whether B) is a two-wire codeword or an unsigned codeword, a failure in an adjacent logic cell is detected.
That is, (EI, EIB), (WI, WIB), (N
When the values of (I, NIB) and (SI, SIB) are (logic "0", logic "1") or (logic "1", logic "0"), respectively, they are two-wire codewords. Therefore, it is determined that no failure exists.

(EI, EIB), (WI, WIB),
When the values of (NI, NIB) and (SI, SIB) are (logic "0", logic "0") or (logic "1", logic "1"), respectively, a two-wire non-sign Therefore, it is determined that a failure has occurred.

Thus, the logic cell can separately detect a failure in a logic cell adjacent in the row direction and a failure in a logic cell adjacent in the column direction. The result of the determination is that the failure of the adjacent logic cell in the row direction is output via the signal line C40, and the failure of the adjacent logic cell in the column direction is output via the signal line C41.

In this embodiment, the failure of an adjacent logic cell is detected by connecting the two-wire code checker 26 to the input as described above. However, the two-wire code checker 26 is connected to the output. Alternatively, a failure of the own logic cell may be detected.

FIG. 13 shows one embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of a logic cell array 2 including the logic cells 1 described with reference to FIG.

Referring to FIG. 13, in the present embodiment,
The logic cells 1 are connected in a grid to form an array. The logic cell array 2 has a configuration in which the logic cell 1 has an array of 5 cells in the row direction and 5 cells in the column direction, but the size of the array is not limited to this.

As shown in FIG. 13, the output C4 of the two-wire code checker 26 for detecting a failure in an adjacent logic cell in the row direction is output.
0 is collectively connected to any of the precharge buses C26 to C30 for each row of the logic cell to which the logic cell belongs.

The output C41 of the two-wire code checker 26 for detecting the failure of the adjacent logic cell in the column direction is provided to the precharge bus C3 for each column of the logic cell to which the logic cell belongs.
1 to C35.

The precharge buses C26 to C35 are input to the restoration control circuit 9. Thus, the repair control circuit 9 can specify the row or the column of the logic cell including the logic cell in which the failure has occurred.

The repair of the fault is performed in the same manner as in the second example of the reprogramming for repairing the fault described in the fourth embodiment (see FIG. 10). Alternatively, the function can be performed by moving a column to a row or a column of an unused redundant logic cell and transferring the function to a normal logic cell.

In this embodiment, the precharge bus C
When the occurrence of a failure is notified by 26 to C30, the function is transferred in the column direction for each row of the logic cell. When the occurrence of a failure is transmitted by the precharge buses C31 to C35, the function is transferred in the row direction for each column of the logic cell. This is because the repair control circuit 9 issues the address of the memory of the data transfer source to the logical cell array 2 to read the data, and then issues the address of the data transfer destination to write the previously read data. It is done by that.

Finally, FIG. 10 shows the state after the restoration.
As shown in (B), it is necessary to connect rows (or columns) of adjacent logic cells vertically (or left and right) so as to straddle rows (or columns) of logic cells including a failed logic cell.

This embodiment can be performed by programming the multiplexer 27 that determines the output of the logic cell included in the row (or column) of the logic cell including the logic cell in which the failure has occurred. Specifically, when repairing in the column direction in units of rows of the logic cell 1, the output (SO, SOB)
Is input to the multiplexer 27 (NI, NI
B) is programmed to output the value, and the output (NO,
NOB) to the multiplexer 27 (S
(I, SIB).

This is possible because in this embodiment,
When reprogramming in the column direction for each row of the logic cell 1 when an adjacent logic cell in the row direction fails, at least the multiplexer 2 connected to the output (SO, SOB)
This is because the multiplexer 27 connected to 7 and the output (NO, NOB) is normal. Suppose output (SO, SOB)
And the output (NO, NO
If the multiplexer 27 connected to B) has a fault, the fault is detected by the vertically adjacent logic cells, and the logic cells are repaired in the row direction in column units.

Similarly, when restoring in the row direction for each column of logic cells, the multiplexer 27 connected to the outputs (EO, EOB) is programmed to output the value of the input (WI, WIB), and the output ( A program is performed to output the value of the input (EI, EIB) to the multiplexer 27 connected to the WO (WO, WOB).

In the present embodiment, at the time of restoration, connection between logic cells can be established by the above-described method, and therefore, there is an advantage that it is not necessary to prepare special wiring resources for restoration. .

The flip-flop incorporated in the logic cell 1 of this embodiment is provided with a means for reading and writing the stored contents in the same procedure as that of the SRAM 29, and is assigned a unique address. At the time of restoration, the stored contents can be transferred in the same manner as the SRAM 29 for storing program information. Therefore, after the restoration is completed, by restarting the operation of the clock signal CCLK again, the processing before the occurrence of the failure can be continued.

[0110]

As described above, according to the present invention,
By configuring a logic circuit with a programmable logic circuit realized by a self-checking circuit, the circuit designer can use the logic without special knowledge about fault-tolerance or special design for making it fault-tolerant.
There is an effect that a fault-tolerant logic circuit can be realized. According to the present invention, a programmable logic circuit having higher reliability than a conventional programmable logic circuit can be obtained.

Further, according to the present invention, since the function of a failed logic cell can be replaced with a normal logic cell by reprogramming, a plurality of failures can be dealt with and the amount of redundant circuits can be reduced. This has the effect.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a configuration principle of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing another configuration example of the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a waveform chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 6 is a waveform chart for explaining the operation of the second exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a general sequential circuit.

FIG. 8 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 9 shows a first example of reprogramming for repairing a fault in the embodiment of the present invention.

FIG. 10 shows a second example of reprogramming for repairing a fault in the embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of an example of the present invention.

FIG. 12 is a diagram for describing one embodiment of the present invention, and is a diagram illustrating a configuration example of a self-checking programmable logic cell.

FIG. 13 is a diagram for explaining one embodiment of the present invention, and is a diagram showing a configuration of a self-checking programmable logic cell array.

FIG. 14 is a diagram for explaining one embodiment of the present invention, and is a diagram showing connection of a self-checking logic cell.

[Explanation of symbols]

1, 10, 13, 14 Self-checking programmable logic cell 2 Self-checking programmable logic cell array 3 Control circuit in case of failure 4 Fault-tolerant logic circuit 7 Clock control circuit 9 Repair control circuit 24 Flip-flop 25 Look-up table 26 2 Line code checkers 27, 28 Multiplexer 29 SRAM C1, C26 to C35 Signal lines for notifying occurrence of failure C2, C3, C4 Clock signal lines

Claims (7)

(57) [Claims] 1. A programmable logic circuit comprising: a plurality of programmable logic cells each storing program information of the programmable logic circuit in a rewritable memory and having a self-checking function. is provided with means for performing the reprogramming of the clock control means and the programmable logic circuit, wherein said clock control means generates a first clock signal for operating the flip-flops included in the programmable logic cell <br/>, wherein when a failure in the programmable logic cell is detected, the stop of the first clock signal, the fault is transient, when it is detected that said fault has been eliminated, the supply of the first clock signal Function means for restarting the operation of the programmable logic circuit. Means for performing a ram, a permanent fault upon occurrence, failure occurred Pro
Programmable logic with normal function of grammar logic cell
A logic circuit, comprising: functional means for repairing a fault by substituting a cell and restoring a circuit function before the fault. Wherein said clock control means, said first black
In addition to the first clock signal, a second clock signal having a phase advanced from the first clock signal is generated, and a failure is detected based on the second clock signal, thereby detecting the first clock signal. 2. A stop is performed.
Logic circuit as described. 3. The rewritable memory for storing program information.
The re-programming means reads and writes the contents of the rewritable memory by designating the address of the memory from which the data is to be read. 3. The logic circuit according to claim 1, wherein the reprogramming is performed by designating an address of a memory for performing the rewriting and writing the contents of the rewritable memory previously read. 4. The rewritable storage of program information.
A unique address is assigned to the flip-flop incorporated in the logic cell in addition to the functional memory , and means for reading and writing contents stored in the same procedure as the rewritable memory is provided. Item 3. The logic circuit according to Item 3. 5. A computer having a self-checking function.
Roguramaburu failure detection result of the logic cell, self check
2. The reprogramming device according to claim 1, wherein the reprogramming is performed in units of rows or columns by grouping the programmable logic cells having a king function in rows or columns.
5. The logic circuit according to any one of claims 1 to 4. 6. A method according to claim 1, wherein a row or a column of an unused redundant logic cell is prepared in advance for repairing the fault, and the means for reprogramming detects the fault detected by the row or column of the programmable logic cell. Based on the result, the row or column of the used logic cell between the row or column of the logic cell including the failed logic cell and the row or column of the redundant logic cell is replaced with the row of the redundant logic cell. 6. The logic circuit according to claim 5, wherein the fault is repaired by moving in parallel toward the column. 7. The computer having a self-checking function.
The programmable logic cell separately examines inputs from the row direction and the column direction, and separately detects a failure of a logic cell adjacent in the row direction and a failure of a logic cell adjacent in the column direction. The logic circuit according to claim 1, wherein: