CN112230970A - FPGA refreshing method suitable for satellite-borne XILINX V2 - Google Patents
FPGA refreshing method suitable for satellite-borne XILINX V2 Download PDFInfo
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Abstract
A method suitable for refreshing a satellite-borne XILINX V2 FPGA is disclosed, wherein single event upset caused by non-single event functional interruption can be corrected by refreshing; single event upset can only be recovered by pulling down the PROG pin and reconfiguring the FPGA. The refreshing function can avoid single event effect accumulation, prolong the working time of the satellite-borne signal processing FPGA and improve the reliability of the satellite-borne equipment. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause the interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not influence the function of the signal processing FPGA. The invention also provides a frame address increment step and a frame-based refresh command during refresh.
Description
Technical Field
The invention relates to a refreshing method suitable for a satellite-borne XILINX V2 FPGA.
Background
When the satellite-borne electronic equipment runs in an orbit, the influence of cosmic high-energy rays on the electronic equipment must be considered. A single event upset changes the logic state of a static storage element. The function of an FPGA depends on the data stored in the millions of configuration registers of the FPGA. A single event upset in a configuration memory array can have a significant impact on the desired function. The single event upset of the configuration storage space may or may not affect the function. The elimination of the single event upset effect can be realized by adopting a triple modular redundancy design technology.
The V2 series FPGA SelectMap interface achieves the most efficient post-configuration control by reading or writing to the configuration storage array. The read-back is a configuration read operation after configuration storage, and the partial reconfiguration is a configuration write operation after configuration storage. The read-back and partial reconfiguration can detect and repair the single event upset of the configuration storage space on the premise of not influencing the application of a user. If a single event upset phenomenon occurs that affects user applications, it can only be corrected by reconfiguring the FPGA.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: in the on-orbit operation process of the satellite-borne electronic equipment, if single event upset occurs but single event function interruption does not occur, the single event effect can be corrected through refreshing, the accumulation of the single event effect is avoided, and meanwhile, the user function is not interrupted. The invention overcomes the defects of the prior art, provides a refreshing method suitable for a satellite-borne XILINX V2 FPGA, and single event upset caused by non-single event functional interruption can be corrected through refreshing; single event upset can only be recovered by pulling down the PROG pin and reconfiguring the FPGA. The refreshing function can avoid single event effect accumulation, prolong the working time of the satellite-borne signal processing FPGA and improve the reliability of the satellite-borne equipment. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause the interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not influence the function of the signal processing FPGA. The invention also provides a frame address increment step and a frame-based refresh command during refresh.
The purpose of the invention is realized by the following technical scheme:
a refreshing method suitable for an on-board XILINX V2 FPGA comprises the following steps:
s1, powering up the FPGA;
s2, pulling down the PROG pin of the FPGA for at least 300 ns;
s3, downloading configuration data from the nonvolatile storage device to configure the FPGA;
s4, testing the frame address register, and returning to S2 if the test fails; otherwise, go to S5;
s5, activating read-back, if the read-back data is consistent with the configuration data, switching to S6, otherwise, returning to S2;
s6, performing CRC check, if the CRC check fails, returning to S2, if the CRC check has errors, transferring to S7, and if the CRC check has no errors, transferring to S4;
and S7, performing activated partial reconfiguration, if the reconfiguration is normal, turning to S4, and if not, returning to S2.
The above method for refreshing the on-board XILINX V2 FPGA is preferably implemented by monitoring the status register between S4 and S5, and if the status register normally goes to S5, otherwise, returning to S2.
Preferably, in S2, the PROG pin of the FPGA is pulled down for at least 300ns until the INIT pin of the FPGA becomes high.
Preferably, in the method for refreshing the on-board XILINX V2 FPGA, DriveDone and PWRDWN _ Stat of the configuration option register and persistence and Security Level of the control register are refreshed in S3.
Preferably, in the above method for refreshing the on-board XILINX V2 FPGA, in S4, the frame address register test first writes a predefined value into the frame address register and then reads back the frame address register.
The above method for refreshing the on-board XILINX V2 FPGA is preferably such that in S5, the first readback sequence covers all GCLK, IOI, CLB, and IOB except the last IOB frame; the second read-back sequence reads back only the last IOB frame in the buffer; the third read-back sequence validates all remaining configuration frames that control the BRAM interconnect.
Preferably, in the refreshing method suitable for the satellite-borne XILINX V2 FPGA, the ascending sequence of the frame addresses is the minimum address, the row address and the block address; that is, when the minimum address is incremented to the maximum frame number, the minimum address is reset to 0, the column address starts to increment, when the column address is incremented to the maximum column, the column address is reset to 0, the block address starts to increment, and when the block address is incremented to the maximum block, the block address is reset to 0.
Compared with the prior art, the invention has the following beneficial effects:
(1) when the satellite-borne electronic equipment works on the orbit, the configuration management engine refreshes the FPGA of the satellite-borne signal processing, so that the accumulation of single event effect is avoided, the reliability of the satellite-borne equipment during working is improved, and the service life of the satellite-borne electronic equipment is prolonged.
(2) When single event upset occurs due to single event functional interruption, the function is recovered by reconfiguring the signal processing FPGA, and if single event upset occurs due to non-single event functional interruption, the function can be corrected by refreshing, and the refreshing does not affect the function of the signal processing FPGA.
(3) And adding a monitoring state register between the test and the activation read-back of the frame address register, activating the read-back if the frame address register is normal, and pulling down the PROG pin to reconfigure the FPGA if the frame address register is normal. Unnecessary readback is avoided, and the fault-free working time of the satellite-borne electronic equipment is prolonged.
(4) The detection of single event functional interruption is influenced by DriveDone, PWRDWN _ Stat of the configuration option register, Persist and Security Level of the control register. Thus, both registers are flushed to improve the probability of detection of a single event functional interrupt.
(5) If a look-up table is used, such as SRL16 or distributed ram (lutram), a read-back or partial reconfiguration will destroy the contents of this part of the primitive. Problems with SRL16 or distributed ram (lutram), BRAM are also encountered. Therefore, the invention avoids the BRAM block address when reading back and reconfiguring.
(6) If the FPGA design does not use any BRAM, the configuration management engine will read back the entire configuration memory space using a sequence. Otherwise, a full read-back requires three read-back sequences to avoid corrupting the BRAM content. The first read-back sequence of the present invention covers all GCLK, IOI, CLB, part of IOB. Omitting the last IOB frame prevents the first BRAM frame from entering the buffer, thus corrupting the BRAM. The second read-back sequence reads back only the last IOB frame in the buffer. The third read-back sequence validates all remaining configuration frames that control the BRAM interconnect. In the second read-back sequence, the frame address register points to an unused address. When this unused address is read back, the first virtual frame read back is the last IOB frame stored in the first read back sequence buffer.
Drawings
FIG. 1 is a storage space architecture for V2 configuration;
FIG. 2 is a V2 column level configuration memory map;
FIG. 3 is a schematic diagram of a single event effect cancellation circuit;
FIG. 4 is a flow chart of a single event upset detection and correction algorithm;
fig. 5 is a flow chart of frame address incrementing.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A refreshing method suitable for an on-board XILINX V2 FPGA comprises the following steps:
s1, powering up the FPGA;
s2, pulling down the PROG pin of the FPGA for at least 300 ns;
s3, downloading configuration data from the nonvolatile storage device to configure the FPGA;
s4, testing the frame address register, and returning to S2 if the test fails; otherwise, go to S5;
s5, activating read-back, if the read-back data is consistent with the configuration data, switching to S6, otherwise, returning to S2;
s6, performing CRC check, if the CRC check fails, returning to S2, if the CRC check has errors, transferring to S7, and if the CRC check has no errors, transferring to S4;
and S7, performing activated partial reconfiguration, if the reconfiguration is normal, turning to S4, and if not, returning to S2.
As a preferred scheme of the invention, between S4 and S5, the status register is monitored, and if the status register normally goes to S5, otherwise, the status register returns to S2.
In a preferred embodiment of the present invention, in S2, the PROG pin of the FPGA is pulled down for a minimum of 300ns until the INIT pin of the FPGA goes high.
In a preferred embodiment of the present invention, DriveDone and PWRDWN _ Stat of the configuration option register and persistence and Security Level of the control register are refreshed in S3.
As a preferred aspect of the present invention, in S4, the frame address register test first writes a predefined value to the frame address register and then reads back the frame address register.
As a preferred aspect of the present invention, in S5, the first readback sequence covers all GCLK, IOI, CLB, and IOB except the last IOB frame; the second read-back sequence reads back only the last IOB frame in the buffer; the third read-back sequence validates all remaining configuration frames that control the BRAM interconnect.
As a preferred scheme of the invention, when refreshing, the ascending order of the frame address is the minimum address, the row address and the block address; that is, when the minimum address is incremented to the maximum frame number, the minimum address is reset to 0, the column address starts to increment, when the column address is incremented to the maximum column, the column address is reset to 0, the block address starts to increment, and when the block address is incremented to the maximum block, the block address is reset to 0.
Example (b):
1. configuration storage architecture
The most basic configuration unit in the V2 architecture is a frame. The configuration frame group is composed of CLB, IOB, IOI, GCLK, BRAM interconnections columns. Columns are divided into three block types: CLBs (including GLKC, CLBs, IOB1&2), BRAMs, and BRAM Interconnects. The V2 configuration storage space architecture is shown in fig. 1.
The V2 frame addresses start at 0x00000000h (the starting address of the middle GCLK column of the device), increment the frame address up to the leftmost IOB column, and then increment to the right. The frame address register is composed of three parts, a block address, a main address and a smaller address. When the FDRI or FDRO command requires the configuration of multiple frames or the reading back of multiple frames, the frame address register automatically increments the smaller address, the primary address, and the block address. Block address 00 covers all GCLK, IOB, IOI and CLB columns, block address 01 contains all BRAM columns, and block address 10 contains all BRAM interconnections columns. The master address is a function of the size of the device, determined by the number of columns in the device. The V2 column level configuration memory map is shown in fig. 2.
Special considerations are needed in the design implementation for read-back and partial reconfiguration operations. If a look-up table is used, such as SRL16 or distributed ram (lutram), a read-back or partial reconfiguration will destroy the contents of this part of the primitive. Problems with SRL16 or distributed ram (lutram), BRAM are also encountered. Therefore, the BRAM block address must be avoided for read back and re-write. However, the BRAM Interconnect frame contains only configuration information and does not contain special RAM primitives, and thus, is freely accessible like a CLB frame.
The single event upset of the configuration store may destroy the user design or may not have any effect on the user design. Most of the flipping of the configuration store will not have any impact on the user design, since most of the configuration store is not relevant to the user design. Routing control bits account for more than 60% of the configuration bits, whereas typical designs use only 10% -20% of the routing resources. The configuration store is read back and the read back data is compared to the stored configuration data to determine if the configuration store bit has flipped.
V2 single event upset detection method
(1) Monitoring for DONE signals
After the device configuration is successful, the DONE pin should remain high. If DONE goes low, it indicates that a single event upset has occurred in the powered-on portion of the circuit, resulting in a global or partial flush of the configuration store, requiring a reconfiguration.
(2) Write and read frame address register
Before each flush and read-back operation, the frame address registers should be written and read to quickly identify SelectMAP interface problems or other configuration logic disturbances.
(3) Computing and comparing readback CRC
When reading back, the read back data may be used to calculate a CRC value. An incorrect CRC value will result in an incorrect SEFI detection if no comparison of CRCs is made, and therefore, when CRCs do not agree, a reconfiguration is required to obtain a correct CRC value.
(4) Monitoring BUSY signals
In a write operation, the BUSY pin should remain low. In a read operation, the BUSY pin should remain high. When the BUSY pin changes from high level to low level, the data on the data line is indicated to be correct data. When the write operation is converted into the read operation, if the time that the BUSY pin keeps high level exceeds 32 clock cycles, SMAP SEFI is indicated.
(5) Verifying read-back data
In readback, the readback data is compared to the configuration data to ensure that there are no differences. The CRC value may be calculated from the read back data.
(6) Monitoring status register
The status register stores the critical device status. Bit 12 is the state of the DONE pin. Bit 7 indicates the GHIGH state, the internal pull-up of the GHIGH control signal. Bit 6 is global write enable and bit 5 is a global tri-state.
2. Configuration management engine
For most on-orbit applications, a configuration management engine is required to prevent accumulation of single event upsets in the configuration storage space, and detect and recover configuration control logic single event functional interrupts. The schematic diagram of the single event effect elimination circuit is shown in FIG. 3. The flow chart of the single event upset detection and correction algorithm is shown in fig. 4.
2.1 full configuration
After the single machine is powered on, the configuration management engine pulls down the FPGA PROG pin by a minimum of 300 ns. And when the INIT pin is detected to be high, the FPGA is initialized and ready to be configured. The configuration management engine should download configuration data from a non-volatile memory device (e.g., PROM) to configure the FPGA. The detection of single event functional interruption is influenced by DriveDone, PWRDWN _ Stat of the configuration option register, Persist and Security Level of the control register. Therefore, these two registers should be flushed to ensure detection of a single event functional interrupt. For refresh purposes, a typical value for the control register is X "0000000D" and a typical value for the configuration option register is X "00043F E5". The recommended sequence of read-back configuration option registers or control registers is shown in table 1.
TABLE 1
2.2 Single event upset detection
After the FPGA is successfully configured, the single event upset detection can be carried out. Single event upset detection begins with a frame address register test. The frame address register test first writes a predefined value to the frame address register and then reads back the frame address register. If the read-back value is consistent with the expected value, the configuration management engine may read back the entire configuration storage space. If the read-back data of the frame address register is not consistent with the expected value, the single event functional interruption is possible to happen, and the configuration engine needs to reconfigure the data. After the test of the frame address register fails, there is a possibility that a single event function interruption does not occur, but a single event upset causes an error of readback data. The frame address register test sequence is shown in table 2.
TABLE 2
After the frame address register is tested successfully, the status register should be read back and verified. If bits 5 or 6 of the status register become 0, the device will have tri-state outputs or the capability to update synchronous device components will fail. To eliminate this problem, the device must be shut down and restarted. The sequence of the read status register is shown in table 3.
TABLE 3
After the frame address register and status register check passes, a device read back should be performed. The device read-back can detect general single event upset, and the integrity of refreshing is guaranteed. If the device does not contain any SRL16 or LUTRAM primitives, the read-back data may be aligned with configuration data in the non-volatile storage. If the FPGA design does not use any BRAM, the configuration management engine will read back the entire configuration memory space using a sequence. Otherwise, a full read-back requires three read-back sequences to avoid corrupting the BRAM content. The first read-back sequence covers all GCLK, IOI, CLB, part of IOB. Omitting the last IOB frame prevents the first BRAM frame from entering the buffer, thus corrupting the BRAM. The second read-back sequence reads back only the last IOB frame in the buffer. The third read-back sequence validates all remaining configuration frames that control the BRAM interconnect. In the second read-back sequence, the frame address register points to an unused address. When this unused address is read back, the first virtual frame read back is the last IOB frame stored in the first read back sequence buffer.
The readback data may be compared with configuration data in the nonvolatile memory, or may be subjected to CRC check. The CRC and check may be based on either a single frame or a device. Read-back checks should be performed to ensure that single event upsets are corrected. An uncorrected single event upset indicates that a single event functional interrupt caused a configuration store write failure.
If the CRC check passes and there are no read-back errors, then there is no rollover in the configuration store. The designer can choose to repeat the read-back until finding the single event upset error, and then refresh, or choose to automatically and continuously refresh. The read-back sequence is shown in table 4.
TABLE 4
2.3 Refresh
After a single event upset event is detected when a non-single event function interrupts, the FPGA needs to be refreshed to prevent accumulation of single event upsets. After the refresh is completed, a read-back should be performed to ensure that the single event upset is corrected. A read-back operation or a refresh operation may destroy LUT storage primitives, such as: SRL16s and LUTRAM. Therefore, the design should not include SRL16 or LUTRAM to simplify the refresh process. When using BRAM, two refresh procedures are required: the first refresh sequence covers all GCLK, IOB, IOI and CLB columns, and the second refresh sequence covers only BRAM interconnect columns. The refresh sequence is shown in table 5.
TABLE 5
3-frame address increasing method
The XILINX V2 FPGA supports the refresh of the zeroth and second type blocks. When refreshing, the ascending sequence of the frame address is the minimum address, the column address and the block address. When the minimum address is increased to the maximum frame number, the minimum address is reset to 0, the column address starts to be increased, when the column address is increased to the maximum column, the column address is reset to 0, the block address starts to be increased, and when the block address is increased to the maximum block, the block address is reset to 0. The refresh time frame address increment flow chart is shown in fig. 5.
The frame address incrementing step is as follows:
(1) initializing, wherein the frame address is 0;
(2) the smaller address is incremented;
(3) the smaller address is increased to the maximum value of the corresponding column type, the smaller address is reset to be 0, and the column address is increased; otherwise, returning to the step (2);
(4) the column address is increased to the maximum value, the column address is reset to 0, and the block address is increased; otherwise, returning to the step (2);
(5) the block address is 1 or 2, and the step (2) is returned; the block address is 3, end.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (7)
1. A refreshing method suitable for an on-board XILINX V2 FPGA is characterized by comprising the following steps:
s1, powering up the FPGA;
s2, pulling down the PROG pin of the FPGA for at least 300 ns;
s3, downloading configuration data from the nonvolatile storage device to configure the FPGA;
s4, testing the frame address register, and returning to S2 if the test fails; otherwise, go to S5;
s5, activating read-back, if the read-back data is consistent with the configuration data, switching to S6, otherwise, returning to S2;
s6, performing CRC check, if the CRC check fails, returning to S2, if the CRC check has errors, transferring to S7, and if the CRC check has no errors, transferring to S4;
and S7, performing activated partial reconfiguration, if the reconfiguration is normal, turning to S4, and if not, returning to S2.
2. The FPGA refreshing method suitable for on-board XILINX V2 as claimed in claim 1, wherein between S4 and S5, the status register is monitored, and if the transition is normal, S5 is performed, otherwise S2 is performed.
3. The method for refreshing the FPGA adapted to the on-board XILINX V2 of claim 1, wherein in S2, the PROG pin of the FPGA is pulled down for a minimum of 300ns until the INIT pin of the FPGA goes high.
4. The method for refreshing the XILINX V2 FPGA on board a satellite according to claim 1, wherein DriveDone and PWRDWN _ Stat of configuration option registers and Persist and Security Level of control registers are refreshed in S3.
5. The method for refreshing the FPGA adapted to be XILINX V2 on board the satellite as claimed in claim 4, wherein in S4, the frame address register test first writes a predefined value into the frame address register and then reads back the frame address register.
6. The method of claim 1, wherein in S5, the first readback sequence covers all GCLK, IOI, CLB, and IOB except the last IOB frame; the second read-back sequence reads back only the last IOB frame in the buffer; the third read-back sequence validates all remaining configuration frames that control the BRAM interconnect.
7. A refreshing method suitable for an on-board XILINX V2 FPGA according to any one of claims 1-6, wherein, during refreshing, the ascending sequence of frame addresses is a minimum address, a column address and a block address; that is, when the minimum address is incremented to the maximum frame number, the minimum address is reset to 0, the column address starts to increment, when the column address is incremented to the maximum column, the column address is reset to 0, the block address starts to increment, and when the block address is incremented to the maximum block, the block address is reset to 0.
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