CN111552500A - Refreshing method suitable for satellite-borne FPGA - Google Patents
Refreshing method suitable for satellite-borne FPGA Download PDFInfo
- Publication number
- CN111552500A CN111552500A CN202010225328.9A CN202010225328A CN111552500A CN 111552500 A CN111552500 A CN 111552500A CN 202010225328 A CN202010225328 A CN 202010225328A CN 111552500 A CN111552500 A CN 111552500A
- Authority
- CN
- China
- Prior art keywords
- register
- fpga
- refreshing
- value
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A satellite-borne XILINX V4 FPGA refreshing method belongs to the technical field of FPGA configuration and monitoring. The refreshing function can avoid single event effect accumulation, prolong the working time of the satellite-borne signal processing FPGA and improve the reliability of the satellite-borne equipment. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause the interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not influence the function of the signal processing FPGA.
Description
Technical Field
The invention relates to a refreshing method suitable for a satellite-borne FPGA, in particular to a refreshing method suitable for a satellite-borne XILINXV4 FPGA, and belongs to the technical field of FPGA configuration and monitoring.
Background
The single event upset caused by space irradiation may cause interruption of single event function. The single event upset is divided into two types, one is single event functional interrupt type single event upset, and the other is non-single event functional interrupt type single event upset. For non-single event functional interrupt type single event upset, the method comprises two conditions of SMAP/JTAG single event functional interrupt and frame address register single event functional interrupt. Wherein, using SelectMAP or JTAG port, SMAP/JTAG single particle function interruption can occur, leading to failure of post-configuration control (such as read-back or configuration refresh); and a single event upset that causes a read or write failure of a frame address register is referred to as a frame address register single event functional interrupt. The two situations can not interrupt the application of a user, but further single event effect detection and correction can be invalid, the working stability and reliability of the FPGA are directly influenced, the satellite-borne equipment is subjected to in-orbit failure, and the normal in-orbit operation of the satellite is seriously endangered.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method overcomes the defects of the prior art, and provides the refreshing method suitable for the satellite-borne FPGA, the refreshing function can avoid single event effect accumulation, the working time of the satellite-borne signal processing FPGA is prolonged, and the reliability of satellite-borne equipment is improved. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause the interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not influence the function of the signal processing FPGA.
The purpose of the invention is realized by the following technical scheme:
a refreshing method suitable for a satellite-borne FPGA comprises the following steps:
s1, selecting the type block capable of being refreshed in the status register and the control register, and taking the sequence from the minimum address, the row address, the top bit to the bottom bit, and the sequence from the type block with smaller ordinal number to the type block with larger ordinal number as the ascending sequence of the frame address of the selected type block;
s2, writing a preset defined value into the frame address register, then reading back the value of the frame address register, if the preset defined value is consistent with the read-back value, the frame address register is normal, and the operation goes to S3; otherwise, judging that the frame address register is abnormal, and turning to S4;
s3, reading back the value of the status register or the value of the control register, if the read back value is not consistent with the corresponding default value, judging that the status register is abnormal or the control register is abnormal;
s4, when the frame address register is abnormal, the FPGA is reconfigured, and when the state register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1; then, S2 to S4 are repeated.
According to the refreshing method suitable for the satellite-borne FPGA, preferably, refreshed configuration data are stored in the three memories, and three-mode comparison is performed when the data are read.
Preferably, in the refreshing method applicable to the satellite-borne FPGA, the comparison granularity is bit level in the three-mode comparison.
Preferably, each memory stores multiple configuration files, when the status register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1, the status register or the control register is detected again after the refreshing, and if the status register or the control register is still abnormal, the configuration storage area is refreshed by replacing the configuration storage area with other configuration files.
Preferably, the refresh is performed by a frame-based refresh command or a device-based refresh command.
According to the refreshing method applicable to the satellite-borne FPGA, preferably, the default value of the state register is 0x00007 EFC; if the GLUT _ MASK _ B of the FPGA is enabled, the default value of the control register is 0x20000009, otherwise the default value of the control register is 0x 20000109.
In the above refreshing method for the satellite-borne FPGA, preferably, if the bit4 or 5 or 6 or 7 or 13 or 14 of the status register becomes 0, or the bit1 or 15 or 16 of the status register becomes 1, it is determined that the value of the status register is inconsistent with the corresponding default value; if the bit0, or 4, or 5, or 6, or 9, or 10, or 11, or 13-30 of the control register does not match the corresponding default value, then the control register is determined not to match the corresponding default value.
Preferably, the type blocks capable of being refreshed in the frame address register include a zeroth type block, a first type block, and a sixth type block.
Preferably, when a frame-based refresh command is adopted, two frames of data need to be written, the first frame of data is actual refresh data, and the second frame of data is virtual data.
Preferably, the second frame data is 0.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention refreshes the on-track signal processing FPGA, and can improve the reliability of the signal processing FPGA and prolong the working time of the signal processing FPGA compared with the non-refreshing.
(2) The refreshing method refreshes the zeroth type block, the first type block and the sixth type block completely without omission.
(3) The refreshing method of the invention can flexibly use the SRL16 and the LUTRAM by setting the GLUT _ MASK bit of the control register, thereby better utilizing resources.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
fig. 2 is a flow chart of frame address increment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
A refreshing method suitable for an on-board FPGA is disclosed, as shown in FIG. 1, the type blocks capable of being refreshed in a frame address register comprise a zeroth type block, a first type block and a sixth type block, and the method comprises the following steps:
s1, selecting the type block capable of being refreshed in the status register and the control register, and taking the sequence from the minimum address, the row address, the top bit to the bottom bit, and the sequence from the type block with smaller ordinal number to the type block with larger ordinal number as the ascending sequence of the frame address of the selected type block;
s2, writing a preset defined value into the frame address register, then reading back the value of the frame address register, if the preset defined value is consistent with the read-back value, the frame address register is normal, and the operation goes to S3; otherwise, judging that the frame address register is abnormal, and turning to S4;
s3, reading back the value of the status register or the value of the control register, if the read back value is not consistent with the corresponding default value, judging that the status register is abnormal or the control register is abnormal;
s4, when the frame address register is abnormal, the FPGA is reconfigured, when the state register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1, and the refreshing adopts a frame-based refreshing command or an equipment-based refreshing command; then, S2 to S4 are repeated.
The default value of the status register is 0x00007 EFC; if the GLUT _ MASK _ B of the FPGA is enabled, the default value of the control register is 0x20000009, otherwise the default value of the control register is 0x 20000109.
If bit4 or 5 or 6 or 7 or 13 or 14 of the status register becomes 0, or bit1 or 15 or 16 of the status register becomes 1, it is determined that the value of the status register is inconsistent with the corresponding default value; if the bit0, or 4, or 5, or 6, or 9, or 10, or 11, or 13-30 of the control register does not match the corresponding default value, then the control register is determined not to match the corresponding default value.
Example (b):
a refreshing method of a satellite-borne XILINX V4 FPGA is suitable for the satellite-borne FPGA, the refreshing function can avoid single event effect accumulation, the working time of the satellite-borne signal processing FPGA is prolonged, and the reliability of satellite-borne equipment is improved. When the single event effect causes the interruption of the single event function, the signal processing FPGA needs to be reconfigured. When the single event effect does not cause the interruption of the single event function, the single event effect needs to be corrected through refreshing, and the refreshing does not influence the function of the signal processing FPGA.
Specifically, as shown in fig. 2, the method for refreshing a satellite-borne FPGA includes the following steps:
s1, selecting the type block capable of refreshing in the status register and the control register, and using the sequence from the least address, the column address, the row address, the top bit to the bottom bit, and the type block with smaller ordinal number to the type block with larger ordinal number as the frame address ascending sequence of the selected type block.
The XILINX V4 FPGA supports the refresh of the zeroth, first, sixth type blocks. During refreshing, the ascending sequence of the frame address is a minimum address, a column address, a row address, a top/bottom bit and a block type. When the minimum address is increased to the maximum frame number, the minimum address is reset to be 0, the column address starts to be increased, when the column address is increased to the rightmost column, the column address is reset to be 0, the row address starts to be increased, when the row address is increased to the maximum row number, the row address is reset to be 0, the top bit is switched to be the bottom bit, the refreshing of the bottom address is started, the refreshing mode of the bottom address is the same as that of the top address, after the refreshing of the bottom address is completed, the refreshing of a first type block is started, the refreshing mode of the first type block is the same as that of a zeroth type block, only the number of the refreshed frames is different, and after the refreshing of the first type block is completed, the refreshing of a sixth type block is started. The frame address register is shown in table 1. The refresh time frame address increment flow chart is shown in fig. 2.
TABLE 1
The frame address incrementing step is as follows:
(1) initializing, wherein the frame address is 0;
(2) the smaller address (lower 6 bits of the frame address) is incremented;
(3) the smaller address (the lower 6 bits of the frame address) is incremented to the maximum value of the corresponding column type, the smaller address is reset to 0, and the column address is incremented; otherwise, returning to the step (2);
(4) the column address is increased to the maximum value, the column address is reset to 0, and the row address is increased; otherwise, returning to the step (2);
(5) the row address is increased to the maximum value, the row address is reset to be 0, and whether the row address is the top or the bottom is judged; otherwise, returning to the step (2);
(6) if the top part is the top part, switching the top part to the bottom part, and returning to the step (2);
(7) if yes, judging whether the block type is 0, 1 or 6;
(8) if the value is 0 or 1, switching to 1 when the block type is 0, and switching to 6 when the block type is 1, and returning to the step (2);
(9) if 6, the frame address increment ends.
S2, writing a preset defined value into the frame address register, then reading back the value of the frame address register, if the preset defined value is consistent with the read-back value, the frame address register is normal, and the operation goes to S3; otherwise, the frame address register is judged to be abnormal, and the process goes to S4.
The configuration management engine writes a predefined value to the frame address register and then reads back the frame address register value. If the readback value matches the expected value, the device is declared to have not been SMAP and FAR SEFI. If the frame address register readback data does not match the expected value, indicating that SEFI may have occurred, the configuration management engine should reconfigure the device as soon as the system allows it. The recommended sequence for performing the frame address register test using the SMAP8 interface is shown in table 2.
TABLE 2
S3, reading back the value of the status register or the value of the control register, if the read back value is not consistent with the corresponding default value, judging that the status register is abnormal or the control register is abnormal.
If bit4 or 5 or 6 or 7 or 13 or 14 of the status register becomes 0, or bit1 or 15 or 16 flips to 1; or the read-back value of the control register bit0 or 4 or 5 or 6 or 9 or 10 or 11 or 13 to 30 does not coincide with the desired value, the FPGA should be reconfigured. The default value of the status register is 0x00007EFC, and the default value of the control register is 0x 20000109. If GLUT _ MASK _ B is enabled, then the value of the control register is 0x 20000009. The status and control register read back recommendation sequence is shown in table 3.
TABLE 3
S4, when the frame address register is abnormal, the FPGA is reconfigured, when the state register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1, and the refreshing adopts a frame-based refreshing command or an equipment-based refreshing command; then, S2 to S4 are repeated.
By setting the GLUT _ MASK bit of the control register, the Virtex-4 FPGA can flexibly use the SRL16 and the LUTRAM so as to better utilize resources.
There are two types of refresh commands, the first being device-based refresh commands, as shown in table 4. The second is a frame-based refresh command, as shown in table 5.
TABLE 4
Supplementary description of table 4:
1. if the design uses SRL16/LUTRAM, then the GLUT _ MASK _ B bit needs to be set to 0.
The number of FDRI words depends on the device type.
3. The refresh data is data configuring block 0, block 1 and block 6 in the bit stream.
TABLE 5
Supplementary description of table 5:
1. the frame address is variable.
2. Considering data buffering, two frames of data need to be written, the first frame of data is real refresh data, the second frame of data is dummy data, and real data is pushed for writing.
3. The first frame data is real data and the second frame data is preferably all 0's.
The refreshed configuration data can be stored in the three-chip memory, and when the data is read, three-mode comparison is carried out, the comparison granularity is bit level, so that the reliability of the configuration data is improved, namely the refreshing success rate is improved.
The memory stores a plurality of configuration files, when the abnormality of the state register or the abnormality of the control register is detected, the refreshing is started, after the refreshing is finished, the state register or the control register is detected again, if the abnormality still exists, the configuration file in the memory is damaged, the other configuration file is replaced for refreshing, and the refreshing success rate is improved.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (10)
1. A refreshing method suitable for a satellite-borne FPGA is characterized by comprising the following steps:
s1, selecting the type block capable of being refreshed in the status register and the control register, and taking the sequence from the minimum address, the row address, the top bit to the bottom bit, and the sequence from the type block with smaller ordinal number to the type block with larger ordinal number as the ascending sequence of the frame address of the selected type block;
s2, writing a preset defined value into the frame address register, then reading back the value of the frame address register, if the preset defined value is consistent with the read-back value, the frame address register is normal, and the operation goes to S3; otherwise, judging that the frame address register is abnormal, and turning to S4;
s3, reading back the value of the status register or the value of the control register, if the read back value is not consistent with the corresponding default value, judging that the status register is abnormal or the control register is abnormal;
s4, when the frame address register is abnormal, the FPGA is reconfigured, and when the state register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1; then, S2 to S4 are repeated.
2. The refreshing method suitable for the satellite-borne FPGA according to claim 1, wherein the refreshed configuration data is stored in three pieces of memory, and when the data is read, three-mode comparison is performed.
3. The refreshing method suitable for the satellite-borne FPGA according to claim 2, wherein in the three-mode alignment, the alignment granularity is bit level.
4. The method according to claim 2, wherein a plurality of configuration files are stored in each memory, when the status register is abnormal or the control register is abnormal, the configuration storage area of the FPGA is refreshed according to the frame address increasing sequence in S1, the status register or the control register is detected again after the refreshing, and if the status register or the control register is still abnormal, the configuration storage area is replaced with another configuration file for refreshing.
5. A refreshing method suitable for an FPGA on board a satellite according to any one of claims 1 to 4, characterized in that the refreshing adopts a frame-based refresh command or a device-based refresh command.
6. The refreshing method for the FPGA according to any one of claims 1 to 4, wherein the default value of the status register is 0x00007 EFC; if the GLUT _ MASK _ B of the FPGA is enabled, the default value of the control register is 0x20000009, otherwise the default value of the control register is 0x 20000109.
7. A refreshing method suitable for an FPGA (field programmable gate array) on board as claimed in any one of claims 1 to 4, wherein if bit4 or 5 or 6 or 7 or 13 or 14 of the status register becomes 0, or bit1 or 15 or 16 of the status register becomes 1, the value of the status register is determined not to be consistent with the corresponding default value; if the bit0, or 4, or 5, or 6, or 9, or 10, or 11, or 13-30 of the control register does not match the corresponding default value, then the control register is determined not to match the corresponding default value.
8. The refreshing method for the FPGA on board a satellite according to any one of claims 1 to 4, wherein the type blocks capable of being refreshed in the frame address register comprise a zeroth type block, a first type block and a sixth type block.
9. The method according to claim 5, wherein two frames of data need to be written when a frame-based refresh command is used, the first frame of data is actual refresh data, and the second frame of data is dummy data.
10. The method according to claim 9, wherein the second frame data are all 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010225328.9A CN111552500B (en) | 2020-03-26 | 2020-03-26 | Refreshing method suitable for spaceborne FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010225328.9A CN111552500B (en) | 2020-03-26 | 2020-03-26 | Refreshing method suitable for spaceborne FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111552500A true CN111552500A (en) | 2020-08-18 |
| CN111552500B CN111552500B (en) | 2023-06-06 |
Family
ID=72005578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010225328.9A Active CN111552500B (en) | 2020-03-26 | 2020-03-26 | Refreshing method suitable for spaceborne FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111552500B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230970A (en) * | 2020-09-16 | 2021-01-15 | 北京遥测技术研究所 | FPGA refreshing method suitable for satellite-borne XILINX V2 |
| CN114661531A (en) * | 2022-02-28 | 2022-06-24 | 成都市硅海武林科技有限公司 | Fine-grained self-repairing circuit and method for FPGA |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080098279A1 (en) * | 2006-10-18 | 2008-04-24 | Trellisware Technologies, Inc. | Using no-refresh dram in error correcting code encoder and decoder implementations |
| CN101826038A (en) * | 2010-04-28 | 2010-09-08 | 复旦大学 | Circuit and method for resisting SEU of SRAM FPGA device |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN104281742A (en) * | 2014-09-11 | 2015-01-14 | 上海卫星工程研究所 | SRAM (static random access memory) type large-scale FPGA (field programmable gate array) anti-single-particle device and method |
| CN105068969A (en) * | 2015-07-17 | 2015-11-18 | 西安空间无线电技术研究所 | Single event effect protection system and method for digital signal processing platform architecture |
| CN105223494A (en) * | 2015-09-25 | 2016-01-06 | 中国人民解放军国防科学技术大学 | A kind of system single particle effect detection method based on parallel testing and system |
| US20160350002A1 (en) * | 2015-05-29 | 2016-12-01 | Intel Corporation | Memory device specific self refresh entry and exit |
| CN106557346A (en) * | 2016-11-24 | 2017-04-05 | 中国科学院国家空间科学中心 | A kind of primary particle inversion resistant star-carried data processing system and method |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
| CN110555237A (en) * | 2019-07-31 | 2019-12-10 | 北京遥测技术研究所 | FPGA (field programmable Gate array) on-orbit dynamic reconfigurable method |
-
2020
- 2020-03-26 CN CN202010225328.9A patent/CN111552500B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080098279A1 (en) * | 2006-10-18 | 2008-04-24 | Trellisware Technologies, Inc. | Using no-refresh dram in error correcting code encoder and decoder implementations |
| CN101826038A (en) * | 2010-04-28 | 2010-09-08 | 复旦大学 | Circuit and method for resisting SEU of SRAM FPGA device |
| CN103473159A (en) * | 2013-10-13 | 2013-12-25 | 西安电子科技大学 | FPGA (Field Programmable Gate Array) configuration information turnover testing platform based on dynamic reconfiguration and testing method |
| CN104281742A (en) * | 2014-09-11 | 2015-01-14 | 上海卫星工程研究所 | SRAM (static random access memory) type large-scale FPGA (field programmable gate array) anti-single-particle device and method |
| US20160350002A1 (en) * | 2015-05-29 | 2016-12-01 | Intel Corporation | Memory device specific self refresh entry and exit |
| CN105068969A (en) * | 2015-07-17 | 2015-11-18 | 西安空间无线电技术研究所 | Single event effect protection system and method for digital signal processing platform architecture |
| CN105223494A (en) * | 2015-09-25 | 2016-01-06 | 中国人民解放军国防科学技术大学 | A kind of system single particle effect detection method based on parallel testing and system |
| CN106557346A (en) * | 2016-11-24 | 2017-04-05 | 中国科学院国家空间科学中心 | A kind of primary particle inversion resistant star-carried data processing system and method |
| CN107894898A (en) * | 2017-11-28 | 2018-04-10 | 中科亿海微电子科技（苏州）有限公司 | Refresh device, implementation method and the fpga chip with error correction on SRAM type FPGA pieces |
| CN110555237A (en) * | 2019-07-31 | 2019-12-10 | 北京遥测技术研究所 | FPGA (field programmable Gate array) on-orbit dynamic reconfigurable method |
Non-Patent Citations (3)
| Title |
|---|
| LI WANG 等: "Design and implementation of DDR SDRAM controller based on FPGA in satellite navigation system", 《2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING》 * |
| 宋琪: "星载固态存储管理技术的应用研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
| 张衡: "星载电子设备FPGA的动态刷新方法及实现", 《制导与引信》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230970A (en) * | 2020-09-16 | 2021-01-15 | 北京遥测技术研究所 | FPGA refreshing method suitable for satellite-borne XILINX V2 |
| CN114661531A (en) * | 2022-02-28 | 2022-06-24 | 成都市硅海武林科技有限公司 | Fine-grained self-repairing circuit and method for FPGA |
| CN114661531B (en) * | 2022-02-28 | 2023-08-29 | 成都市硅海武林科技有限公司 | Fine-granularity self-repairing circuit and method for FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111552500B (en) | 2023-06-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100305311B1 (en) | Refresh period control apparatus and method, and computer | |
| KR101089409B1 (en) | Memory array error correction apparatus, systems, and methods | |
| US9685217B2 (en) | Memory device with over-refresh and method thereof | |
| CN112667445B (en) | Method and device for repairing packaged memory, storage medium and electronic equipment | |
| US9514843B2 (en) | Methods for accessing a storage unit of a flash memory and apparatuses using the same | |
| WO2015073900A1 (en) | Method and apparatus for multiple-bit dram error recovery | |
| CN108511029B (en) | Built-in self-test and repair system and method for dual-port SRAM array in FPGA | |
| CN111552500B (en) | Refreshing method suitable for spaceborne FPGA | |
| US8843805B1 (en) | Memory error protection using addressable dynamic ram data locations | |
| CN103578565A (en) | Calibration method and device of NAND Flash memory chip | |
| CN101477480A (en) | Memory control method, apparatus and memory read-write system | |
| US11257563B2 (en) | Apparatus and method for testing a defect of a memory module and a memory system | |
| JP4196743B2 (en) | Semiconductor memory device | |
| CN114077384A (en) | Memory device and method for controlling refresh operation of memory device | |
| US9564205B2 (en) | Memory apparatus and method for accessing memory | |
| US20220270701A1 (en) | Method and system for replacement of memory cells | |
| US20170322880A1 (en) | Methods for Reprogramming Data and Apparatuses using the Same | |
| US20120042118A1 (en) | Method for Flash Memory and Associated Controller | |
| JP4627411B2 (en) | Memory device and memory error correction method | |
| EP2418648A1 (en) | RAM memory device selectively protectable with ECC | |
| WO2021179213A1 (en) | Method and device for repairing memory chip | |
| JP6220972B2 (en) | Integrated circuit and programmable device | |
| US10734079B1 (en) | Sub block mode read scrub design for non-volatile memory | |
| CN116959545A (en) | Chip testing method and device | |
| US11662941B2 (en) | System and method for mitigating effect of erase cells on adjacent cells |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |