KR100204576B1 - Structure of common block register built-in memory and shadow recovery structure & method - Google Patents

Abstract

The present invention relates to a memory structure for transaction processing and a method for recovering a database system. The method of managing a page table does not require a backup to disk by introducing a shadow page recovery structure and a recovery technique using a common block register internal memory. There is no need to perform backup and recovery block by block, and even a small number of locks can be performed, and the copy time, which was the biggest burden when executing a transaction, can be almost ignored. As it can be reduced enough to eliminate all the burden on a transaction, a structure of a common block register internal memory capable of fast transaction processing and recovery, and a shadow page recovery structure and a recovery technique using the same are presented.

Description

Structure of Common Block Register Embedded Memory and Its Shadow Page Recovery Structure

The present invention relates to a memory structure for transaction processing and a recovery method of a database system, and more particularly, to a structure of a common block register embedded memory, a shadow page recovery structure, and a recovery technique using the same.

Conventionally, a disk is mainly used as a medium for storing a database. However, due to the development of semiconductor technology, a main memory database system (MMDBS) using a large memory has emerged. The database needs a recovery algorithm to maintain consistency in the event of an error. In other words, unlike regular updates, database updates should restore their original values to ensure consistency when an error occurs during the update. This main memory database is used for communication networks or industrial applications that require real-time processing.

The shadow page technique is a recovery method to maintain consistency. The shadow page technique has one original and one copy when executing a transaction to update a database. The problem of the conventional shadow page technique will be described with reference to FIG.

1 is a block diagram illustrating a conventional shadow page technique. Typically, a database is stored on disk and divided into blocks of pages. To update the database stored in the disk, the transaction first copies the original block i 100 before updating to block k 101 of the main memory. Next, after updating block k 101, block k 101 is copied to block j 102, which is a disk area different from block i 100. Next, as shown in FIG. Since the block moves at this time, the page table is used to map the block with the database processing program. There is a burden of updating this page table in the prior art. This is one of the factors that reduces the performance of shadow pages.

Another disadvantage of the conventional disk-based shadow page technique is that small unit locking is difficult. The database system can be accessed by several processes at the same time. If another process accesses the same block of the database, the database will not be consistent. The process here operates on the same processor or multiple processors. In order to prevent inconsistencies, the prior art allows the block to be marked before use, that is, locked and then accessed to wait for another process. After use, release the lock and let other processes use it. In this case, in a conventional disk-based database system, a block must be copied to a main memory device to update a block. Blocks are often paged, with pages organized into records. A small unit lock means that multiple processors are made available on these records. This is necessary for multiple processors because concurrency increases to increase system performance. In the log-based recovery technique, the problem does not occur because each process writes modifications to the log buffer. However, in the case of the shadow page technique, the problem occurs because the modification is written directly to the record. As an example, suppose two transactions access different records in one block. The block i 100 is copied to the main memory and the two transactions are locked to records of the different parts of the block k 101 and then updated. If both transactions are successful, you can copy block k (101) to the other part of disk, block j (102), update the page table, and complete it. If it fails, it cannot be withdrawn or completed.

As such, the conventional shadow page technique has a disadvantage in that a page table is managed and a small unit lock is difficult. Therefore, the shadow page technique is less than the conventional log-based recovery scheme. When the shadow page technique is applied to the main memory, the existing memory is volatile, and thus a recovery problem occurs when a power failure occurs. However, since the shadow page technique is simpler to recover than the log-based recovery technique, the shadow page technique is required for a communication network or an industrial field requiring real-time restart.

Accordingly, an object of the present invention is to speed up transaction processing and recovery by providing a structure of a common block register embedded memory, a shadow page based recovery structure, and a shadow page recovery technique using the same.

The structure of the common block register built-in memory according to the present invention for achieving the above object is a memory block composed of a plurality for storing data, the memory block is selected in accordance with an external signal and the block write / read control logic circuit A decoder and selection logic circuit for outputting a signal, a block write / read control logic circuit for inputting the decoder and selection logic circuit and an external control signal to control block write / read between a memory block and a common block register; Block write / read control A common block register for performing a block write / read with a memory block by a control signal of a logic circuit, and a block parity for checking whether a parity error occurs when writing to the common block register from the memory block. In case of performing block copy on the check logic circuit and the memory block The cylinder block made of a block size selection logic circuit to enable block copy of a unit smaller than the register characterized.

The shadow page recovery structure using the common block register built-in memory according to the present invention for achieving the above object is a database processor consisting of a processor chip, a memory connected to the database processor and a built-in operation program of the database processor, and the database It is characterized by consisting of a memory having a common block register connected to the processor and performing a data write / read, a block write read control line, a block size selection control line, and a block parity status notification control line.

In addition, the shadow page recovery scheme using the common block register built-in memory according to the present invention for achieving the above object is the step of copying the original memory block to the common block register, and the common block register from which the original memory block is copied Copying a memory block of another region to a common block register, copying a memory block of another copied region to a common block register, Checking whether a first parity error has occurred in the common block register to which the memory block of the region has been copied; updating a original memory block if a parity error has occurred as a result of the check of the first parity error; and Checking whether the updating of the memory block of the memory module is successful; Checking whether the update is successful or not, if the update is successful, copying the updated memory block to the common block memory, copying the updated memory block to the common memory block, and then checking whether there is a second parity error. If a parity error has not occurred as a result of checking whether the second parity error has occurred, releasing the use of the memory block of another area used for the backup; Notifying the transaction and ending the transaction; if the execution of the check result of the update execution is unsuccessful, moving the memory block of another backed up area to the common memory block, and copying the common memory block to the original memory block. And copying the copied original memory block to a common block register. And terminating after notifying a transaction execution failure when a third parity error of the common block register has not occurred, and when the parity error has occurred as a result of the inspection of the occurrence of the second and third parity errors. Discarding the original memory block, selecting another memory block to replace the original memory block with the original memory block, and replacing the original memory block with the original memory block; Copying the data through the common block register, copying the selected original memory block to the common block register, and checking whether a fourth parity error has occurred, and checking whether the fourth parity error has occurred or not. Transitioning to discarding the original memory block if it occurs; If the parity error does not occur as a result of the inspection of the presence or absence of the error occurs, the step of notifying the transaction failure and characterized in that it is terminated.

1 is a block diagram illustrating a conventional shadow page technique.

2 is a structural diagram of a common block register built-in memory according to the present invention.

3 is a block diagram illustrating an embodiment of an operation of a built-in common block register memory according to the present invention;

4 is a block diagram showing an embodiment of an operation of a block size selection logic circuit according to the present invention;

5 is a block diagram showing a shadow page recovery structure according to the present invention.

6A and 6B are a process flow diagram of a shadow page recovery technique in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

201: memory block 202: decoder and selection logic circuit

203: common block register 204: block write / read control logic

205: block parity check logic circuit 206: block size selection logic circuit

The present invention will be described in detail with reference to the accompanying drawings.

2 is a structural diagram of a common block register built-in memory according to the present invention. As shown, the memory 200 structure of the present invention is as follows. The memory block 201 is composed of a plurality of memory means for storing contents. The decoder and selection logic circuit 202 selects a memory block to reference the contents of the memory according to an external signal and outputs a signal to the block write / read control logic circuit. The block write / read control logic 204 inputs an external control signal to the decoder and selection logic circuit 202 to control block write / read between the memory block 201 and the common block register 203. The common block register 203 performs block write / read with the memory block 201 by a control signal of the block write / read control logic circuit 204. The block parity check logic circuit 205 checks whether a parity error has occurred when writing to the common block register 203, and the block size selection logic circuit 206 enables copying of blocks smaller than the common block register. do.

The memory block 201 may use an existing volatile memory or nonvolatile memory cell. However, since the memory block and the like must be nonvolatile for the main memory shadow page recovery structure of the present invention, an uninterruptible power supply must be used externally when a volatile cell is used. Since the common block register 203 is used as a buffer when writing / reading blocks, a volatile cell may be used. Currently, nonvolatile cells have a limited number of writes, so the common block registers that are used frequently use volatile cells that have unlimited number of writes.

3 is a block diagram illustrating an embodiment of an operation of a built-in common block register memory according to the present invention. The decoder 303 decodes the input address bus 302 to output the first and second signals to the block write / read control logic circuit 304, and output the remaining signals to the first and second signals of the memory block 310. Outputs the remaining bytes except the second byte. The block write / read control logic circuit 304 uses the signal of the block write / read control line 300 and two signals output from the decoder 303 to receive the read control signal 306 and the write control signal 307. The memory block 310 outputs the enable signal and outputs the enable signal to the first byte and the second byte of the memory block 310. In this case, when the block write / read control line 300 is '0', the selected memory contents are input through the data bus 305 by decoding the address bus 302 inputted to the decoder 303 like the existing memory chip. Or output However, when the address bus 302 is address '0' of each block, the selected block is written to the common block register 312, and when address '1' is read from the common block register 312. The block parity check logic circuit 313 checks the integrity of the contents stored in the memory block 310 as a means for detecting a parity error occurrence in each byte on a block basis, and checks the parity state notification control line 309 for the result of the check. Output to the outside through. This detecting means is particularly necessary when the memory blocks are constituted by nonvolatile cells and not by an external uninterruptible power supply. Currently developed nonvolatile cells have a limited number of writes. Therefore, after a certain number of writes, a method of moving to another block should be used. You can also use write counters as a way of determining the time that needs to be moved, but for databases that require a high level of integrity, continuous integrity checks are required. In the present invention, the integrity check is performed in units of blocks when writing to the common block register to minimize the total check time. Since the common block register 312 is physically fixed at the time of chip fabrication, the common block register 312 may be implemented by writing / reading a plurality of blocks in a large block application. However, problems arise in applications where smaller blocks are needed, and block size selection logic circuit 311 is used as a means to solve this problem.

4 is a block diagram illustrating an embodiment of an operation of a block size selection logic circuit in a memory structure according to the present invention. Memory block movement is possible by controlling the write control line. The memory block 405 is divided into a first memory 9906 and a second memory 407 to write to the first register 409 and the second register 410 of the common block register 408, respectively. In this embodiment, when the block write / read control line 400 is '1' and the address '0' of each block is accessed, the first logical product is decoded by decoding the address bus 401 input to the decoder 402. The first memory 406 is written to the first register 409 by driving the circuit 403. When the address '1' of each block is accessed, the second memory circuit 404 is driven by decoding the address bus 401 input to the decoder 402 to drive the first memory 407 to the second register 410. Write on When accessing the '2' address of each block, the address bus 401 input to the decoder 402 is decoded to simultaneously drive the first logical multiplier circuit 403 and the second logical multiplier circuit 404 so that the memory block ( 405 is written to the common block register 408, making it applicable even if a small block is needed. In another embodiment, when a block is divided into more physical blocks, it can be solved by using an internal address line such as '0', '1', '2', or '3'. In the case of reading a block from the common block register 408, the same method can be applied to solve the problem. The size of the physical block and the size of the divided block are fixed at the time of manufacture.

5 is a block diagram illustrating a shadow page recovery structure using a common block register embedded memory according to the present invention. The database processor 500 configured of a general processor chip is connected to a memory 501 in which an operation program of the database processor is embedded. The database processor 500 is connected to the common block register internal memory 506 to perform data write / read (502), and the memory block 509 and the common block using the common block write / read control line 503. The block write / read logic circuit 511 which writes and reads between the registers 513 is controlled. In addition, the parity by the parity check logic circuit 512 which controls the block size selection logic circuit 511 for selecting a block size through the block size selection control line 504 and checks the parity generation when writing / reading a common block. The state is received through the parity state notification control line 505.

6A and 6B are operational flowcharts of the shadow page technique according to the present invention. The shadow page technique according to the present invention does not need to manage the page table because it overwrites the same place unlike the conventional method. The operation sequence is as follows. After copying the original memory block to the common block register (601), the common block register is copied, i.e., backed up to the memory block of another region (602), and the memory block of the other region copied for the integrity check of the data is copied. Copy to common block register (603). It is checked whether a parity error has occurred (604). If a parity error occurs as a result of the check, the memory block of the selected other area is discarded and restarted from the first step (605). If the parity error has not occurred, the original memory block is updated (606). Then, it is checked whether the update has been successfully performed (607). If the result of the check is successful, the updated memory block is copied to the common block memory (609) and then a parity error is detected (610). If a parity error does not occur as a result of the check, the memory block of the other area used for the backup is released (611), the update is completed, and the transaction is terminated (612). If the update fails in step 607, the memory block of another backed up area is moved to the common memory block and then copied to the original memory block (608). The recovered original memory block is copied to the common block register (613) and a parity error is checked (614). If a parity error does not occur as a result of the check, the program terminates after notifying a transaction execution failure (619). If a parity error occurs in steps 610 and 614, the original memory block is discarded (615). The other memory block is selected and replaced with the original memory block (616), and the original contents backed up in the memory block of the other area are copied to the selected original memory block through the common block register (617). After copying the selected original memory block to the common block register (618), it is checked whether a parity error has occurred (619). If a parity error occurs as a result of the check, the process starts again from step 9515, and if the parity error does not occur, it notifies of a transaction failure and ends (620).

As described above, in the recovery structure of the present invention, since the copy time, which was the greatest burden when performing a transaction, is performed as a block unit, it is almost negligible to minimize, thereby minimizing the burden required for the transaction, thereby performing fast transaction processing and recovery. That has a great effect. In particular, the parity check is performed block by block to maximize the integrity of the database. Since small blocks can also be manipulated, it has a great effect to solve the problem of small unit lock, which was difficult to implement in the conventional shadow page technique. .

Claims (4)

A memory block composed of a plurality of memory blocks for storing data, a decoder and selection logic circuit for selecting the memory block according to an external signal and outputting a signal to a block write / read control logic circuit, the decoder and selection logic circuit and an external device A block write / read control logic circuit for controlling a block write / read between a memory block and a common block register by inputting a control signal of the memory block, and a block write / mutual block write / read by a control signal of the block write / read control logic circuit. A common block register for performing a read, a block parity check logic circuit for checking whether a parity error occurs when writing to the common block register in the memory block, and a block copy in the memory block, which is smaller than the common block register. Block size selection logic circuit allowing block copying of units The structure of a common block, characterized in that the built-in memory register is made. The structure of claim 1, wherein the plurality of memory blocks are formed of any one of a volatile cell and a nonvolatile cell. A database processor comprising a processor chip, a memory connected to the database processor, a memory having an operation program of the database processor, a data write / read with the database processor, a block write / read control line, a block size selection control line, A shadow page recovery structure using a common block register internal memory, comprising a memory having a common block register connected to a block parity status notification control line. Copying the original memory block to a common block register; copying the common block register from which the original memory block is copied to a memory block of another region; and copying the copied memory block of the other region to a common block register. Copying; checking whether a first parity has occurred in a common block register to which the memory block of the other area is copied; and checking a memory of another selected area when a parity error occurs as a result of checking whether the first parity error has occurred. Transitioning to copying the original memory block to the common block register after discarding the block, updating the original memory block if a parity error has not occurred as a result of checking whether the first parity error has occurred; Checking whether the updating of the original memory block was successful; Checking whether the update is successful or not. If the update is successful, copying the updated memory block to the common block memory, and copying the updated memory block to the common memory block and checking whether a second parity error occurs. Canceling use of a memory block of another area used for backup if a parity error does not occur as a result of the check of the presence or absence of the second parity error; updating after releasing the use of the memory block of the other area; Notifying the completion of the transaction and ending the transaction; if a result of the check on whether the update has been performed successfully fails, moving the memory block of another backed up area to the common memory block; and copying the common memory block to the original memory block. And copying the copied original memory block to a common block register. Copying to the terminal, checking whether a third parity error has occurred in the common block register, notifying a transaction execution failure if a parity error has not occurred as a result of the inspection of the third parity error occurrence, and terminating; Discarding the original memory block if a parity error occurs as a result of the inspection of the occurrence of the second and third parity errors; and discarding the original memory block and selecting another memory block and replacing the original memory block with the original memory block. Copying, through a common block register, original contents backed up to a block of another area replaced by the original memory block, and copying the selected original memory block to a common block register, and then generating a fourth parity error. Checking whether there is a parity error; Transitioning to discarding the original memory block if it occurs, and terminating after notifying a transaction failure when a parity error does not occur as a result of the check of the presence or absence of the fourth parity error. Shadow page recovery using internal memory.