JP2012053778A - Error correction circuit of programmable logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction circuit of a programmable logic circuit capable of dynamically performing detection, correction and restoration of an error in a configuration memory, with the error concealed, without influencing the programmable logic circuit.SOLUTION: An error correction circuit 11 includes: a configuration memory 12 where configuration data indicating circuit configuration or wiring configuration of a programmable logic circuit and the error detection encoding data for the configuration data are read out from a base memory M and stored; an error detection unit 131 that detects occurrence of an error on the basis of the configuration data and the error detection encoding data; an alternative storage unit 134 that stores the configuration data prior to the occurrence of the error; a multiplexer unit 133 that switches the configuration data to the configuration data stored by the alternative storage unit 134 in response to error notification; and a reconfiguration control unit 14 that reads out the configuration data from the base memory M and writes the data in the configuration memory 12 for reconfiguration.

Description

  The present invention relates to an error correction circuit of a programmable logic circuit that can form a logic circuit in a programmable manner.

  Programmable logic circuits are called PLDs (Programmable Logic Devices) and are employed in various devices such as CPLDs (Complex Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays).

  The programmable logic circuit can have a desired configuration for the logic circuit based on the configuration data read from the configuration memory. Since this configuration memory is composed of, for example, an SRAM (Static Random Access Memory), it is known that soft errors due to α rays and neutron rays occur. When data is destroyed due to the influence of a soft error, circuit information that determines a logic circuit changes, which may cause a malfunction.

  Generally, high reliability of a programmable logic circuit is achieved by combining hardware redundancy such as triple redundancy (TMR) and scrubbing for repairing erroneous data. As such conventional techniques, for example, those described in Patent Documents 1 to 3 are known.

  Patent Document 1 discloses a semiconductor memory with an error correction function including a memory cell array unit having three or more odd number of memory cells for one bit of one address, and a data output unit having a majority circuit, In addition, there is described a semiconductor memory with an error correction function including a selector that switches memory cells to be written in a normal mode and a high reliability mode, and a multiplexer that switches read memory data and output data from a majority circuit.

  Further, Patent Document 2 reads information on a configuration memory affected by a soft error, and corrects an error in the configuration memory data using an error check bit (error correction code), thereby scrubbing inside the PLD. The method of doing is described.

  Further, in Patent Document 3, a duplex configuration of an active FPGA and a spare FPGA is used, and when a soft error occurs in the active FPGA, the active FPGA is switched to the spare FPGA, and before the switching. A soft error correction method is described in which a spare FPGA is switched to an active FPGA and a soft error occurrence location of the spare FPGA is reconfigured.

JP-A-6-52697 JP 2007-293856 A JP 2005-235074 A

However, the triple redundancy as described in Patent Document 1 increases the amount of hardware because it has three configuration memories and data read circuits, and therefore the increase in area and the increase in wiring are large. This is a problem.
In the method described in Patent Document 2, when a plurality of bits are affected by a soft error and cannot be repaired with an error correction code, it is necessary to temporarily stop the circuit operation and rewrite the entire circuit. Therefore, there is a possibility that it cannot cope with a multi-bit soft error.
In addition, the soft error correction method described in Patent Document 3 can dynamically repair soft errors, but it is dealt with by a large-scale method of switching the circuit itself. Error detection and reconfiguration start from soft error occurrence The error concealment up to is not considered.

  When an abnormality occurs in the configuration data, not only the configuration data is restored, but also the error concealment can be restored so that the programmable logic circuit that configures the circuit based on this configuration data is not affected. is important.

  Accordingly, the present invention provides an error correction circuit for a programmable logic circuit capable of dynamically performing a process from detection, correction, and recovery of an error in the configuration memory in a state of concealing the error without affecting the programmable logic circuit. The purpose is to do.

  An error correction circuit for a programmable logic circuit according to the present invention includes: a second memory in which configuration data indicating a circuit configuration or a wiring configuration of the programmable logic circuit is read from the first memory and stored; and the second memory An error detection unit that detects the occurrence of an error from the configuration data read from the configuration data and the error detection encoded data of the configuration data, an alternative storage unit that stores configuration data before an error from the second memory occurs, and the error An error detection and correction unit including a multiplexer unit that switches from the configuration data from the second memory to the configuration data held in the alternative storage unit and outputs the configuration data to the programmable logic circuit using the error notification from the detection unit as a switching instruction; , Reading the configuration data from the first memory in response to an error notification from the error detection unit, and the second Characterized in that a reconfiguration control unit which reconstructs write to memory.

  The error correction circuit of the programmable logic circuit according to the present invention includes a second memory for storing configuration data from the first memory. In addition to the configuration data, the second memory stores error detection encoded data that can detect an error in the configuration data. The error detection unit checks whether or not a reading error such as a soft error has occurred based on the configuration data from the second memory and the error detection encoded data. When the occurrence of an error is detected, the error detection unit switches the configuration data output from the multiplexer unit to the programmable logic circuit from the configuration data from the second memory to the configuration data from the alternative storage unit. Since the configuration data before the occurrence of the error from the second memory is held in the alternative storage unit, the configuration data without error can be output to the programmable logic circuit. At this time, since the reconfiguration control unit reads the configuration data from the first memory and writes the data to the second memory for reconfiguration, even if a soft error occurs in the second memory, the programmable logic circuit is affected. It can be restored to the correct original configuration data without giving.

The reconfiguration control unit reconfigures the second memory based on an error notification from the error detection unit, and outputs a notification instructing the multiplexer unit to maintain the switching state during the reconfiguration. It is desirable to do.
When an error occurs, the error detection unit immediately switches the multiplexer unit. However, the switching state needs to be maintained while the reconfiguration control unit reconfigures the second memory. Therefore, by outputting a notification instructing the maintenance of the switching state to the multiplexer unit, the configuration data from the alternative storage unit is reliably transferred to the programmable logic circuit while the reconfiguration control unit is reconfiguring the configuration memory. Can be output.

The alternative storage unit is a latch that outputs the configuration data from the multiplexer unit as it is when there is no switching instruction, and holds the configuration data from the multiplexer unit according to the switching instruction, and the first input to the multiplexer unit After the error detection unit starts detection processing of the configuration data from the memory of No. 2, the detection processing detects an error, notifies the multiplexer unit of the error, and the multiplexer unit switches the configuration data It is desirable to provide a delay unit that delays by the amount of time.
Since the alternative storage unit inputs and updates the configuration data from the multiplexer unit, if there is no delay unit, the error detection unit starts the detection process and then detects and notifies an error by this detection process. There is a possibility that the configuration data in an error state may be held during the time until the multiplexer unit switches the configuration data. However, when the delay unit delays the configuration data from the second memory that is input to the multiplexer unit, the configuration data before the occurrence of the error is input at the timing when the update of the configuration data in the alternative storage unit is stopped. Therefore, configuration data before the occurrence of an error can be held, and correct configuration data can be output to the programmable logic circuit.

  In addition, a plurality of the second memories are provided, and each second memory stores configuration data corresponding to each part of the programmable logic circuit, and the plurality of second memories include: The error detection / correction unit may be provided in correspondence with each other.

  The second memory, the error detection unit, the alternative storage unit, and the multiplexer unit are formed in a first layer that is the same layer as the semiconductor layer in which the programmable logic circuit is formed, and the first memory And the reconfiguration control unit are formed in a second layer, which is the same semiconductor layer, and the wiring between the first layer and the second layer is connected by a through via to form a three-dimensional structure. Therefore, the chip area can be reduced.

  The second memory, the error detection unit, the alternative storage unit, the multiplexer unit, and the reconfiguration control unit are the same layer as the semiconductor layer in which the programmable logic circuit is formed. The first memory is formed in a second layer different from the first layer, and interconnects between the first layer and the second layer are connected by through vias. You can also. When configured in this manner, it can be mixed with a highly integrated memory process and can be arranged three-dimensionally, so that the chip area can be reduced.

Furthermore, any one of a plurality of configuration data of different programmable logic circuits stored in the first memory is written into the second memory, and the reconfiguration control unit is configured to detect the error. Instead of error notification from the unit, switching output from the circuit switching unit is used as a switching instruction, and the output of the multiplexer unit is switched from configuration data from the second memory to configuration data held by the alternative storage unit And outputting to the programmable logic circuit, reading the configuration data selected based on the circuit switching notification from the first memory, writing to the second memory, reconfiguring, and then outputting the output of the multiplexer unit The other configuration data written to the second memory from the configuration data held by the alternative storage unit Switch, the other configuration data can also be output to the programmable logic circuit.
With this configuration, the error correction circuit can function as a logic circuit selection unit that dynamically switches a plurality of logic circuits.

  In the present invention, when an error occurs, the second memory can be restored by the reconfiguration control unit while outputting normal configuration data from the alternative storage unit, so that a soft error occurs in the second memory. Even in such a case, the original original configuration data can be restored without affecting the programmable logic circuit. Therefore, according to the present invention, it is possible to dynamically perform detection, correction, and recovery from errors in the configuration memory in a state of concealing errors without affecting the programmable logic circuit.

It is a block diagram which shows PLD using the error correction circuit of the programmable logic circuit which concerns on Embodiment 1 of this invention. 2 is a flowchart for explaining the operation of the error correction circuit shown in FIG. It is a figure for demonstrating the arrangement pattern of the correction circuit shown in FIG. It is a figure which shows an example which has arrange | positioned the error correction circuit in the three-dimensional structure. It is a figure which shows the other example which has arrange | positioned the error correction circuit in the three-dimensional structure. It is a block diagram which shows PLD using the error correction circuit of the programmable logic circuit which concerns on Embodiment 3 of this invention.

(Embodiment 1)
An error correction circuit of a programmable logic circuit according to the first embodiment of the present invention will be described with reference to the drawings.
As shown in FIG. 1, the error correction circuit 11 according to the present embodiment incorporated in a PLD 10 which is a programmable logic circuit generates a soft error generated in the configuration memory 12 by a logic cell group or a wiring switch unit (hereinafter, programmable). This circuit is concealed without affecting the logic circuit P and corrects the configuration data.

  An external base memory M that stores configuration data indicating the circuit configuration or wiring configuration of the programmable logic circuit P is connected to the PLD 10. The base memory M is a nonvolatile memory in which configuration data and error detection encoded data are stored and read out serially. Hereinafter, data obtained by combining the configuration data and the error detection encoded data is hereinafter referred to as configuration data. As the error detection code, a Hamming code is adopted, but ECC (Error Correcting / Detecting Code), parity, CRC (Cyclic Redundancy Check), etc. can also be adopted, and arbitrary encoding can be adopted.

  In the present embodiment, the base memory M is an external storage unit, but it may be built in the PLD 10. Further, the base memory M does not necessarily need to be non-volatile, and may be a volatile memory. Furthermore, an error detection and correction unit that performs error check on the configuration data read from the base memory M may be provided.

The error correction circuit 11 includes a configuration memory 12, an error detection correction unit 13, and a reconfiguration control unit 14.
The configuration memory 12 is a volatile memory formed by a shift register in which serial data read from the base memory M is output as parallel data. As the configuration memory 12, for example, an SRAM can be used, but other memories such as a DRAM can be used as long as serial input and parallel output are possible. In the configuration memory 12 of the present embodiment, the configuration data is n bits wide and the error detection encoded data is m bits wide.

The error detection / correction unit 13 includes an error detection unit 131, a delay unit 132, a multiplexer unit 133, and an alternative storage unit 134.
The error detection unit 131 has a function of detecting the occurrence of an error from the configuration data and the error detection encoded data and outputting an error notification.
The delay unit 132 delays the configuration data from the configuration memory 12. The delay unit 132 can be a multi-stage connected MOS switch, an analog element such as an RC circuit, or the like, and can also be a general delay element composed of digital elements in which NOT gates and NAND gates are connected in multiple stages. .

The multiplexer unit 133 has a function of switching from the n-bit configuration data from the delay unit 132 to the n-bit configuration data from the alternative storage unit 134 by a switching instruction.
The alternative storage unit 134 inputs n-bit configuration data from the output of the multiplexer unit 133 and outputs the configuration data to the multiplexer unit 133. The configuration data being input by the error notification and the notification from the reconfiguration control unit 14 is input. Is a through latch that latches and holds the state.
The reconfiguration control unit 14 has a scrubbing function that reads configuration data stored in the base memory M and writes the configuration data to the configuration memory 12 in response to an error notification. The reconfiguration control unit 14 validates the scrubbing enable signal as a switching instruction while scrubbing.

The operation and use state of the error correction circuit according to the first embodiment of the present invention configured as described above will be further described with reference to FIG.
First, the error detection unit 131 checks whether an error has occurred in the configuration data input from the configuration memory 12 in step S10.
In step S20, when an error due to a soft error or the like has not occurred in the configuration data from the configuration memory 12, the error detection unit 131 outputs an “L” level indicating that no error has occurred. is doing. Accordingly, the multiplexer unit 133 outputs the configuration data from the delay unit 132. The alternative storage unit 134 receives the configuration data from the multiplexer unit 133 and outputs the configuration data to the input of the multiplexer unit 133 as it is. The configuration data from the multiplexer unit 133 is output to the programmable logic circuit P as it is.

If an error due to a soft error or the like occurs in the configuration data in step S20, the error detection unit 131 outputs an “H” level indicating that an error has occurred (step S30).
This error notification is notified to the multiplexer unit 133 via the OR gate 133a. Further, the error notification from the OR gate 133a is notified to the alternative storage unit 134 via the NOT gate 133b.

  With this error notification as a switching instruction, the output of the multiplexer unit 133 is switched from the configuration data from the delay unit 132 to the configuration data from the alternative storage unit 134 (step S40). Further, the alternative storage unit 134 latches the input configuration data in response to the input of the error notification, and holds the state.

  Configuration data from the configuration memory 12 is input to the multiplexer unit 133 via the delay unit 132. The delay unit 132 detects the error by the detection process after the error detection unit 131 starts the detection process, notifies the multiplexer unit 133 of the error, and waits until the multiplexer unit 133 switches the configuration data. Since the delay is delayed, the configuration data latched by the alternative storage unit 134 by the error notification becomes the configuration data before the error occurs. Therefore, correct configuration data before the occurrence of an error is held in the alternative storage unit 134.

  By switching the multiplexer unit 133, the configuration data before the error occurrence held in the alternative storage unit 134 is output to the programmable logic circuit P. Therefore, even if a soft error occurs, the programmable logic circuit P is not affected.

  The reconfiguration control unit 14 validates (“H” level) a scrubbing enable signal that instructs the multiplexer unit 133 to continue switching via the OR gate 133a in response to an error notification from the error detection unit 131 (step S50). Further, the reconfiguration control unit 14 starts a scrubbing operation that reads the configuration data from the base memory M and writes the configuration data to the configuration memory 12 through the configuration path (step S60).

Since the scrubbing enable signal is also notified to the alternative storage unit 134 by the NOT gate 133b, the alternative storage unit 134 maintains the held state by continuing to enable the scrubbing enable signal during the scrubbing operation (step S70).
Therefore, even if the error state is temporarily canceled while the contents of the configuration memory 12 are being rewritten, the configuration data from the alternative storage unit 134 is programmable logic until the rewriting is completed and the state is completely restored. It can be output to the circuit P. Therefore, it is possible to prevent the multiplexer unit 133 from being switched back by mistake.
When the scrubbing operation by the reconfiguration controller 14 is completed, the scrubbing enable signal is disabled ("L" level) (step S80). Further, since the configuration data of the configuration memory 12 is restored to the original data, no error notification is notified from the error detection unit 131.

  By invalidating the scrubbing enable signal, the multiplexer unit 133 outputs the configuration data from the delay unit 132 obtained by delaying the configuration data from the configuration memory 12 that has been normally rewritten to the programmable logic circuit P. Further, the alternative storage unit 134 releases the latch, and outputs according to the input (step S90).

  As described above, even if an error occurs in the configuration data from the configuration memory 12, the configuration data in the configuration memory 12 is rewritten and restored to the original data without affecting the programmable logic circuit P. Therefore, from error detection to correction and recovery can be performed dynamically with errors hidden.

  The error correction circuit according to the first embodiment configured as described above requires an n-bit + m-bit memory as the configuration memory 12 and an n-bit memory as the alternative storage unit 134. That is, a total of 2n bits + m bits of memory is required. However, triple redundancy requires 3 memories corresponding to the configuration memory 12 and therefore becomes 3n. Usually, the bit width of the error detection encoded data is smaller than that of the error detection target data, so that the relationship of n> m is satisfied. Therefore, since the memory capacity can be reduced, the error correction circuit 11 can reduce the area.

  In addition, in the case of triple redundancy, when an error occurs in two configuration memories, the majority decision cannot be obtained, so it is difficult to perform error concealment without performing error notification as well as repair. 10, if the error of the configuration data can be detected by the error detection encoded data, even a multi-bit error can be repaired / restored without affecting the programmable logic circuit P while concealing the error.

  Further, since the error detection and correction unit 13 is inserted between the configuration memory 12 and the programmable logic circuit P that is a logic cell or wiring switch unit, the error detection and correction unit 13 does not depend on the structure of the logic cell or wiring. Therefore, the present invention can be applied to various types of PLD architectures.

  In the error correction circuit 11 according to the first embodiment, the error detection encoded data of the configuration data is stored in the base memory M in advance, but only the configuration data may be stored. In that case, when the configuration data is written into the configuration memory 12 by the reconfiguration control unit 14, an encoding unit that generates and writes error detection encoded data may be provided.

FIG. 3 shows a logic cell or wiring switch portion which is the programmable logic circuit P.
As shown in FIG. 3, the programmable logic circuit device P includes a logic block (Logic Block: hereinafter referred to as LB) in which a programmable logic circuit configuring the logic circuit is arranged based on configuration data of the configuration memory. A connection box (Connection Box: hereinafter referred to as CB) functioning as a wiring switch unit for connecting the LB and the wiring, and a switch box (Switch Box: hereinafter referred to as SB) serving as a cross point of wiring are provided. Yes.

This LB can change the logical function by rewriting the configuration data stored in the configuration memory in the LB. In addition, the connection relationship can be changed by rewriting the configuration data in the CB and SB.
The error correction circuit 11 can be arranged in various patterns with respect to the LB, CB and SB.

For example, in the pattern A, one LB, an SB that is in an oblique positional relationship with the LB, and two CBs that have wirings connected to the LB and the SB are defined as one tile that is a basic configuration, and one tile is included in this tile. A set of configuration memory 12 and an error detection and correction unit 13 are provided in correspondence with each other.
In the pattern B, adjacent tiles are grouped as one group, and a set of configuration memory 12 and an error detection / correction unit 13 are associated with each other.
In the pattern C, a plurality of configuration memories 12 and an error detection / correction unit 13 are provided in one tile.
Further, in the pattern D, a set of configuration memory 12 and an error detection / correction unit 13 are provided corresponding to one SB. In this case, LB or CB can be used instead of SB.

  Since the configuration memory 12 and the error detection and correction unit 13 do not depend on the structure of the configuration data supply destination, the configuration memory 12 and the error detection and correction unit 13 can be applied without being restricted by the framework of functional blocks and tile units.

  In the pattern A and the pattern B, since a large number of functional blocks are targeted, a large number of configuration data is targeted by the error detection and correction unit 13. Since the bit width of the error detection encoded data does not increase proportionally even if the bit width of the configuration data increases, increasing the number of functional blocks to be subjected to error correction increases the amount of memory of the configuration memory 12. Can be suppressed. Therefore, the number of configuration paths from the external memory to the configuration memory 12 can be reduced according to the number of circuits of the error detection / correction unit 13.

  However, in the case of the pattern A and the pattern B, the number of target configuration blocks increases and the number of configuration memories increases, so the circuit scale of the error detection and correction unit 13 increases. Therefore, by reducing the number of target configuration memories such as the pattern C and the pattern D, the circuit scale of the error detection and correction unit 13 can be reduced, and an effect of reducing the circuit scale can be obtained. it can.

  As described above, the error detection / correction unit 13 does not depend on the functional block and can be applied with an optimum granularity, and can be configured by combining these patterns A to D as appropriate.

(Embodiment 2)
Next, a configuration when the error correction circuit 11 shown in FIG. 1 is mounted on the PLD 10 will be described with reference to FIGS. 4 and 5. In FIG. 1, the base memory M in which the configuration data to be scrubbed into the configuration memory 12 is externally attached, but in the second embodiment, it is built in the PLD.

  As shown in FIG. 4, the PLD 20 is provided with a programmable logic circuit P, a configuration memory 12, and an error detection and correction unit 13 in the upper layer, which is the first layer. Further, the PLD 20 is provided with a reconfiguration control unit 14 and a base memory M in a lower layer which is a second layer. A wiring for notifying an error, a wiring for reporting a scrubbing enable signal, and a wiring for a configuration path are connected via a through via. As this through via, for example, a so-called TSV (Through Silicon Via) used for connecting signals between layers can be adopted.

  As shown in FIG. 5, the PLD 30 is provided with a programmable logic circuit P, a configuration memory 12, an error detection and correction unit 13, and a reconfiguration control unit 14 in the upper layer, which is the first layer. ing. Further, the PLD 20 is provided with a base memory M in a lower layer which is the second layer. A wiring to the base memory M for the reconfiguration control unit 14 that performs the scrubbing operation and a wiring for the configuration path are connected via a through via.

If the base memory M is formed in the same layer as other circuits, a mounting area increases, which causes a problem. However, by mounting on an LSI having a three-dimensional structure as shown in FIG. 4 and FIG. 5 and separating the layers of the base memory M and other circuits, the chip area can be reduced, so that the area efficiency is increased. Is possible. In addition, by using a through via as a configuration path that requires a large number of wiring areas according to the bit width, the wiring area can be reduced, and the area efficiency can be further improved.
Further, the base memory M shown in FIG. 5 can be three-dimensionalized by a mixed process by achieving high integration using a DRAM. Thus, the chip area can be reduced by employing a manufacturing process suitable for each layer.

  In addition to the DRAM, the base memory M can be a non-volatile memory by using a flash memory. In addition to the two layers, three or more layers are also possible. In the case of three layers, the upper layer of the PLD 20 shown in FIG. 4 is divided into the programmable logic circuit P and other circuits, or the upper layer of the PLD 30 shown in FIG. 5 is divided into the programmable logic circuit P and other circuits. Can be.

(Embodiment 3)
An error correction circuit according to Embodiment 3 of the present invention will be described with reference to FIG. The error correction circuit 11x of the PLD 10x according to the third embodiment dynamically changes the circuit configuration and wiring configuration of the programmable logic circuit P in response to switching notification from the circuit switching unit 15. In FIG. 6, the same components as those in FIG.

  The base memory Mx stores configuration data indicating a plurality of different circuit configurations of the programmable logic circuit P, a plurality of wiring configurations, or a combination of a circuit configuration and a wiring configuration. For example, it is assumed that the configuration data of the first circuit is written in the configuration memory 12. It is assumed that configuration data of a plurality of circuits including the first circuit is written in the base memory Mx.

  At that time, the switching notification from the circuit switching unit 15 is input to the reconfiguration control unit 14x, and the switching notification includes identification information for specifying the circuit to be switched. For example, if four circuits are stored in the base memory Mx, the numbers “1” to “4” can be designated to instruct circuit switching. In the case of two circuits, switching can be instructed depending on the presence / absence of switching notification.

  When this switching notification is input, the reconfiguration control unit 14x validates the scrubbing enable signal and identifies the circuit notified by the switching notification among the configuration data stored in the base memory Mx, similarly to the error notification. The configuration data of the circuit selected based on the identification information to be written is written to the configuration memory 12 through the configuration path. For example, when the identification information “4” is designated by the switching notification, the configuration data of the fourth circuit is read from the base memory M and written to the configuration memory 12.

The multiplexer 133 outputs the configuration data from the alternative storage unit 134 to the programmable logic circuit P when the scrubbing enable signal becomes valid.
Then, the reconfiguration control unit 14x makes the scrubbing enable signal valid until the configuration data of the fourth circuit is written to the configuration memory 12, so that the programmable logic circuit P until the contents of the configuration memory 12 are replaced. Outputs the configuration data of the first circuit.

  When the reconfiguration control unit 14x finishes writing the configuration data of the fourth circuit, the reconfiguration control unit 14x invalidates the scrubbing enable signal, and after the time delayed by the delay unit 132, the reconfiguration control unit 14x outputs the fourth circuit from the configuration memory 12. Since the configuration data is output from the multiplexer unit 133, the programmable logic circuit P can operate as the fourth circuit.

  Thus, while the reconfiguration control unit 14x reconfigures the configuration memory 12 using the switching notification from the circuit switching unit 15 as a switching instruction instead of the error notification from the error detection unit 131, the multiplexer unit 133 Enable the scrubbing enable signal. In response to this switching instruction, the multiplexer unit 133 outputs the configuration data of the alternative storage unit 134, and switching is performed when the contents of the configuration memory 12 are rewritten. Therefore, the circuit to be mounted is changed as necessary. be able to. Therefore, area efficiency can be improved. In addition, the processing of the entire system is speeded up by mounting an optimum circuit according to the situation.

  The present invention is suitable for a PLD that can form a logic circuit in a programmable manner based on configuration data such as CPLD and FPGA.

10, 20, 30, 10x PLD
DESCRIPTION OF SYMBOLS 11, 11x Error correction circuit 12 Configuration memory 13 Error detection correction part 131 Error detection part 132 Delay part 133 Multiplexer part 133a OR gate 133b NOT gate 134 Alternative storage part 14, 14x Reconfiguration control part 15 Circuit switching part M, Mx Base memory

Claims (7)

A second memory in which configuration data indicating a circuit configuration or a wiring configuration of the programmable logic circuit is read from the first memory and stored;
An error detection unit for detecting an error occurrence from the configuration data read from the second memory and the error detection encoded data of the configuration data; an alternative for holding the configuration data before the error from the second memory occurs A storage unit, and a multiplexer unit that switches the configuration data from the second memory to the configuration data held by the alternative storage unit and outputs it to the programmable logic circuit using an error notification from the error detection unit as a switching instruction An error detection and correction unit;
An error correction circuit for a programmable logic circuit, comprising: a reconfiguration control unit that reads out configuration data from the first memory in response to an error notification from the error detection unit, and writes and reconfigures data in the second memory .   The reconfiguration control unit reconfigures the second memory based on an error notification from the error detection unit, and outputs a notification instructing the multiplexer unit to maintain the switching state during the reconfiguration. An error correction circuit for a programmable logic circuit according to claim 1. The alternative storage unit is a latch that outputs the configuration data from the multiplexer unit as it is when there is no switching instruction, and holds the configuration data from the multiplexer unit according to the switching instruction,
The configuration data from the second memory input to the multiplexer unit is detected by the error detection unit after the error detection unit starts the detection process, and an error is detected by the detection process, and the error is notified to the multiplexer unit. The error correction circuit of the programmable logic circuit according to claim 1 or 2, further comprising a delay unit that delays by a time until the multiplexer unit switches the configuration data. A plurality of the second memories are provided, and each second memory stores configuration data corresponding to each part of the programmable logic circuit,
The error correction circuit of the programmable logic circuit according to any one of claims 1 to 3, wherein the error detection and correction unit is provided corresponding to each of the plurality of second memories. The second memory, the error detection unit, the alternative storage unit, and the multiplexer unit are formed in a first layer that is the same layer as the semiconductor layer in which the programmable logic circuit is formed,
The first memory and the reconfiguration control unit are formed in a second layer, which is the same semiconductor layer,
The error correction circuit of the programmable logic circuit according to any one of claims 1 to 4, wherein the wiring between the first layer and the second layer is connected by a through via. The second memory, the error detection unit, the alternative storage unit, the multiplexer unit, and the reconfiguration control unit are formed in a first layer that is the same layer as the semiconductor layer on which the programmable logic circuit is formed. And
The first memory is formed in a second layer different from the first layer;
The error correction circuit of the programmable logic circuit according to any one of claims 1 to 4, wherein the wiring between the first layer and the second layer is connected by a through via. In the second memory, any one of a plurality of different configuration data of the programmable logic circuit stored in the first memory is written,
The reconfiguration control unit uses the switching notification from the circuit switching unit as a switching instruction instead of the error notification from the error detection unit, and outputs the output of the multiplexer unit from the configuration data from the second memory. The configuration data held by the alternative storage unit is switched to be output to the programmable logic circuit, the configuration data selected based on the circuit switching notification is read from the first memory, and the configuration data is rewritten to the second memory. After the configuration, the output of the multiplexer unit is switched from the configuration data held in the alternative storage unit to the other configuration data written in the second memory, and the other configuration data is switched to the programmable logic circuit. The error correction of the programmable logic circuit according to any one of claims 1 to 6 Road.

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