JP2008015965A - Information processor, operation method of information processor, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restore a soft error of a SRAM (static random access memory) in an FPGA (field programmable gate array) holding information of circuit configuration in the SRAM. <P>SOLUTION: Attribute information for defining a logic circuit is read from the FPGA (step S203) and compared with an expected value prepared beforehand (step S205). Whether the attribute information written in the FPGA has an error or omission caused by the soft error is thereby determined, and when the soft error is detected, the expected value is written in the FPGA (step S206), and the troubled attribute information is overwritten to redefine the circuit configuration of the troubled FPGA, thus restoring the influence of the soft error. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus including an FPGA, and relates to a technique for suppressing a system down caused by a soft error occurring in an FPGA by examining attributes (circuit logic) defined in the FPGA.

  As a malfunction of the semiconductor memory, a hard error that is a physical failure such as destruction of a transistor or a capacitor and cannot be recovered, and a soft error that occurs accidentally due to the influence of cosmic rays such as α particles are known. Soft errors are mainly caused by fluctuations in the amount of charge stored in the memory cell due to the charge of cosmic rays and the charge generated by the collision. Since soft errors are not physical destruction, they can be recovered by an error correction function such as an appropriate error correcting code (ECC). These techniques are described in Patent Documents 1 and 2, for example.

JP-A-57-044298 (abstract) JP-A-57-100694 (abstract)

  By the way, a field programmable gate array (FPGA) is known as a kind of gate array in which a unique logic circuit can be written after the device is completed. The FPGA is an integrated circuit in which a logic circuit can be written (or rewritten) by defining a combination of basic logic circuits according to the state of SRAM (static random access memory) memory cells. Note that some FPGAs use an EEPROM (electrically erasable programmable read only memory) or an antifuse in addition to an SRAM as a device for storing circuit information.

  The soft error described above is particularly problematic in a DRAM (dynamic random access memory) or the like, but not so much in SRAM. However, in an FPGA that can define a circuit with a higher degree of integration, such as an ASIC for image processing, the circuit scale of the SRAM becomes large, so the influence of soft errors cannot be ignored. In the case of the FPGA, the combination of basic logic circuits is determined based on information stored in the SRAM, so that the possibility that the system of the logic circuit that has been defined to generate a soft error will go down increases.

  Patent Document 2 described above describes a configuration in which an error correction circuit is provided in a storage device using an SRAM, and a soft error occurring in the SRAM is detected and repaired. However, since it is necessary for the FPGA to incorporate various circuits with a high degree of integration, it is not appropriate to incorporate an error correction circuit as described in Patent Document 2 in order to increase the degree of integration. Increases manufacturing costs.

  Therefore, the present invention is capable of repairing a soft error occurring in the SRAM in the FPGA that holds the information of the circuit configuration in the SRAM, and detecting it when there is a possibility that the system is down. It aims at providing the technology which controls the outbreak of the accident accompanying the down.

  An information processing apparatus according to the present invention includes a field programmable gate array (FPGA), a control device that can rewrite attribute information that defines the internal configuration of the FPGA, and a storage device. Then, the control device reads out the attribute information from the FPGA, compares the read attribute information with the expected value, compares the read attribute information with the expected value, and uses the expected value based on the result of the comparing step. And logic for executing a redefinition step for redefining the internal structure.

  According to the information processing apparatus of the present invention, attribute information for defining a logic circuit in the FPGA is read from the inside of the FPGA by the control device and compared with an expected value prepared in advance. Thereby, it can be determined whether the attribute information written in the FPGA is free from errors or omissions due to soft errors. In addition, when there is a missing or incorrect attribute information (that is, when a soft error is detected), an expected value is written in the FPGA and the problematic attribute information is overwritten to define the circuit configuration of the FPGA. Fix the effects of soft errors. The attribute information for defining the logic circuit in the FPGA is information for determining the hardware configuration of the FPGA, and is also called configuration data.

  According to this configuration, there is no need to arrange a redundant circuit that does not directly contribute to the original operation of the error correction circuit or the like inside the FPGA. Further, since it is only necessary to determine whether the attribute information matches the expected value, it is possible to detect a soft error in the SRAM in the FPGA regardless of the content of the defined attribute.

  The FPGA may be configured to define attribute information using an EEPROM or an antifuse in addition to the SRAM. As the control device, a CPU (central processing unit) is generally available, but a dedicated integrated circuit may be used. The expected value may be the attribute information itself written in the FPGA or a part thereof.

  The present invention is suitable for use in an image processing apparatus that handles a large amount of data. Specifically, a printing apparatus (printer), a copier (copier), a FAX communication machine, or a multi-function machine having a function combining these functions can be cited as an application target of the present invention. Further, as an aspect of the information processing apparatus of the present invention, a board (a board on which a CPU or FPGA is mounted) that controls these devices can be cited.

  In the information processing apparatus of the present invention, it is desirable to perform the reading step and the comparing step at predetermined time intervals. According to this aspect, the attribute information written in the FPGA is periodically checked. Cosmic rays reach the ground with a certain probability, so that soft errors can be detected efficiently. The predetermined time interval may be a constant time interval or a combination of a plurality of time intervals.

  In the information processing apparatus of the present invention, the storage device includes a nonvolatile semiconductor memory or a hard disk device, and the expected value is preferably stored in the nonvolatile semiconductor memory or the hard disk device. Nonvolatile semiconductor memories (EPROM and EEPROM) are suitable for storing expected values because the structure of the device hardly changes the charge retention state due to cosmic rays. The hard disk device is also suitable for the storage location of the expected value because it is difficult for the retained data to change due to the influence of cosmic rays. It is also possible to arrange a nonvolatile semiconductor memory in the FPGA and store the expected value there.

  In the information processing apparatus of the present invention, it is desirable that a diagnostic program for confirming the operation of the FPGA is executed after the redefinition step and the result is stored in the storage device. The diagnostic program is a program that defines a procedure for testing the operation of the logic circuit defined in the FPGA. According to this aspect, it is possible to detect a trouble (for example, a hardware failure) that cannot be recovered even if attribute information is rewritten.

  In the present invention, the case where the comparison result in the comparison step is mismatched is detected, the counting means for counting the cumulative number of occurrences, the determination means for determining whether or not the cumulative number of occurrences exceeds a predetermined MAX value, It is desirable to provide notification processing means for performing a predetermined notification process based on the determination result.

  According to this aspect, even when redefinition is repeated, it is possible to detect a case where mismatch between the attribute information written in the FPGA and the expected value frequently occurs. Even if redefinition is repeated, if the mismatch between the attribute information written in the FPGA and the expected value frequently occurs, the possibility of a hardware problem due to element degradation or the like is suspected. According to the present embodiment, the number of mismatches between the attribute information read from the FPGA and the expected value is counted, and it is determined whether the count number exceeds a predetermined upper limit value. The occurrence of problems can be predicted. Thereby, the occurrence of inconvenience such as a sudden system down can be suppressed.

  The present invention is an operation method of an information processing apparatus including an FPGA, and includes an attribute information reading step of reading attribute information defining the internal configuration from the FPGA, and a comparison step of comparing the read attribute information with an expected value And a redefinition step of redefining the internal configuration of the FPGA using the expected value based on the result of the comparison step.

  Further, the present invention is a program that is read and executed by a computer equipped with an FPGA, wherein an attribute information reading step for reading attribute information defining the internal configuration from the FPGA, and comparison between the read attribute information and an expected value are performed. It can also be grasped as an invention of a program characterized by executing a comparison step to be performed and a redefinition step for redefining the internal configuration of the FPGA using an expected value based on the result of the comparison step.

  According to the present invention, it is possible to detect a soft error occurring in the SRAM in the FPGA by reading out the attribute information defining the internal configuration of the FPGA from the FPGA and comparing it with the expected value. Thereby, even if a soft error occurs in the SRAM, it can be repaired, and when there is a possibility that the system is down, it can be detected and the occurrence of an accident due to the system down can be suppressed.

(1) First embodiment (configuration of the embodiment)
FIG. 1 shows an example of a block diagram of an information processing apparatus using the present invention. FIG. 1 shows an information processing apparatus 100. In this example, the information processing apparatus 100 constitutes a control part of the copying machine. The information processing apparatus 100 includes a CPU 101, a main storage device 102, a secondary storage device 103, an FPGA 104, and other circuits 105 connected by a bus 106.

  The CPU 101 controls operations performed by the information processing apparatus 100. For example, the CPU 101 executes a self-diagnosis process described later. The CPU 101 has a function of directly accessing the FPGA 104 via the bus 106, reading data from the SRAM in the FPGA 104, and writing data to the SRAM in the FPGA 104. The main storage device 102 is configured by a ROM (read only memory), and stores an operation program of the information processing device 100, a diagnostic program described later, and various parameters. The secondary storage device 103 includes a DRAM, SRAM, EEPROM, and hard disk device, and is used as an area for temporarily storing a program to be operated and a working area for temporarily storing data necessary for the operation. . The secondary storage device 103 stores data obtained during operation.

  The FPGA 104 includes an SRAM, and a combination of gate arrays is determined according to the state of the storage cell of the SRAM, thereby expressing a predetermined function. This function can be changed from the outside by changing attribute information (definition data for determining a combination of circuit elements) written in the SRAM.

  In this example, the FPGA 104 includes a conversion process to a predetermined data format, a color space conversion process for determining a color arrangement, a resolution conversion process for determining a resolution, a filtering process for performing noise removal and contour correction, and an image output unit (printing unit). It functions as an ASIC (application specific integrated circuit) for image processing that performs image processing necessary for a copying machine such as screen processing for conversion into a data format that can be interpreted. That is, the logic circuit for performing these image processing is defined in the FPGA 104 and functions as an integrated circuit including hardware dedicated to image processing. The attribute information for performing this definition is stored in the main storage device 102, read out from the information processing device 100, and written in the SRAM in the FPGA 104. By writing the attribute information, the FPGA 104 is defined as a hardware configuration according to the attribute information and becomes an ASIC having the above-described image processing function.

  The other circuit 105 is an interface circuit for exchanging signals with an image reading unit and an image output unit (not shown). Although not shown, the information processing apparatus 100 includes a display device for notifying the user of predetermined information and operation means for the user to perform various settings and operations.

(Operation of the embodiment)
Hereinafter, an example of a diagnostic process for detecting a soft error in the FPGA 104 will be described. FIG. 2 is a flowchart showing an example of the procedure of this diagnosis process. The following processing is executed under the control of the CPU 101.

  When the information processing apparatus 100 is activated, the attribute information of the FPGA 104 stored in the main storage device 102 is first read and written into the SRAM in the FPGA 104. Further, the diagnosis process is started (step S201), and it is determined whether or not it is the timing to read the attribute information written in the FPGA 104 first (step S202). Here, in step S202, it is determined whether or not the continuous operation time of the apparatus (time during which the power is turned on) has elapsed since the apparatus was started, or whether a predetermined time has elapsed since the previous reading. In step S202, it may be determined whether or not it is a predetermined time set in advance.

  If it is the read timing, the process proceeds to step S203; otherwise, the process returns to the previous stage of step S202. In step S203, the attribute information written in the FPGA 104 is read, and the expected value corresponding to this attribute information is read from the main storage device 102 (step S204). Here, the expected value is the same data as the attribute information.

  Next, the attribute information read in step S203 is compared with the expected value read in step S204, and it is determined whether or not they match (step S205). If they match, it is determined that there is no error, and the processing in step S202 and subsequent steps is repeated. If they do not match, it is determined that there is an error, and the process proceeds to step S206.

  In step S <b> 206, the expected value stored in the main storage device 102 is written into the FPGA 104. That is, the expected value read in step S204 is written in the FPGA 104 in the form of being overwritten on the attribute information read from the FPGA 104 in step S203.

  Next, a self-diagnosis process for confirming the operation of the FPGA 104 is performed using a diagnostic program stored in the main storage device 102 (step S207). This self-diagnosis process is performed by causing the FPGA 104 to perform a predetermined operation and verifying whether or not the result matches an expected value prepared in advance. After this self-diagnosis process, it is determined whether or not there is an abnormality in the diagnosis result (step S208). If there is an abnormality in the diagnosis result, the diagnosis result is stored in a non-volatile area (EEPROM or hard disk device) of the secondary storage device 103, and then the process proceeds to step S211. If there is no abnormality, the process proceeds to step S209.

  In step S211, a notification of a system error for displaying that effect on a display device (not shown) is performed. Thereafter, a process for bringing down the information processing apparatus 100 is performed (step S212). In step S209, the counter value is incremented by +1. The value of this counter is stored in the secondary storage device 103. This counter is 0 when the system is activated, and +1 is added every time the determination in step S205 is NO. Then, it is reset to 0 when the system is down (power OFF).

  After step S209, the process proceeds to step S210 to determine whether or not the counter value exceeds a predetermined value. If the counter value exceeds the predetermined value, a system error notification (step S211) and system down (step S212). On the other hand, if the counter value does not exceed the specified value, the processing from step S202 is executed again.

  The above is the outline of the diagnostic processing related to the detection of the soft error that has occurred in the FPGA 104. In addition to the above processing, there are various operations as a copying machine. Since these operations are the same as those in a normal copying machine, a description thereof will be omitted.

  According to the operation procedure shown in FIG. 2, the attribute information written in the FPGA 104 is read at a predetermined timing (step S202, step S203) and compared with the expected value (step S205). If the attribute information written in the FPGA 104 matches the expected value, it is determined that there is no error, the process returns to step S202, and execution of the diagnosis process is in a standby state until the next diagnosis.

  If the attribute information does not match the expected value, it is determined that some error including a soft error has occurred, and the attribute information is rewritten using the expected value. If the error is a soft error, this rewriting corrects the missing or incorrect SRAM data and prevents the FPGA from malfunctioning due to the soft error. If the attribute information does not match the expected value (NO at S205) and there is no problem with the result of the self-diagnosis process (NO at S208), the counter value is incremented by one (step S209). When the mismatch between the attribute information and the expected value is frequently detected, the integrated value of this counter increases in a short time, and the degree is detected by the determination in step S210. If the frequency of mismatch between the attribute information and the expected value exceeds a certain level, the presence of a serious error factor other than a mere soft error is predicted, and system error notification (step S211) and system down processing (step) S212) is performed. By doing so, it is possible to prevent the inconvenience that a malfunction occurs suddenly during the operation of the system.

  In addition, even if an abnormality is detected in the attribute information (NO in step S205) and the attribute information is rewritten (step S206), if an abnormality is detected in the operation test by the diagnostic program, the attribute information is re-established. It is determined that an error that cannot be repaired by writing has occurred, and system error notification (step S211) and system down processing (step S212) are performed. By doing so, it is possible to deal with a problem that cannot be detected by the determination in step S205.

  Furthermore, if there is an abnormality in the diagnostic result by the diagnostic program for performing the operation test, the diagnostic result is stored in the non-volatile area (EEPROM or hard disk device) of the secondary storage device 103. It can be carried out.

(Modification of the first embodiment)
In step S203, instead of reading all the attribute information written in the FPGA 104, a part of the attribute information may be read and compared with the corresponding expected value. Also, the attribute information written in the FPGA 104 is divided into a plurality of parts, the first divided part of the attribute information is read at the first timing, and the second divided part of the attribute information is read at the second timing. May be performed cyclically.

(2) Second Embodiment FIG. 3 is a block diagram showing an example of another information processing apparatus using the present invention. 3, in addition to the configuration shown in FIG. 1, a dedicated IF control circuit 107 is arranged as an interface for writing and reading attribute information to and from the FPGA 104. The dedicated IF control circuit 107 has an interface function necessary for data transfer between the FPGA 104 and the CPU 101. The interface standard provided in the dedicated IF control circuit 107 includes JTAG, which is a standard for testing integrated circuits, and SEEPROM (serial electronically erasable and programmable read only memory), which is an electrically rewritable ROM connected to a serial bus. ) Interface standards can be used.

  The configuration other than the dedicated IF control circuit 107 is the same as that in FIG. The basic operation procedure is also the same as that shown in FIG. This embodiment is different from the first embodiment in that attribute information is written to and read from the FPGA 104 via the dedicated IF control circuit 107 in the operation shown in FIG.

  The present invention relates to a printing apparatus equipped with an FPGA, a copying machine, a FAX communication machine, a multifunction machine having a function combining these functions, a computer, or a board for controlling these devices (a board on which a CPU or FPGA is mounted). Can be used.

It is a block diagram which shows the outline | summary of the information processing apparatus using invention. 3 is a flowchart illustrating an example of an operation of the information processing apparatus illustrated in FIG. 1. It is a block diagram which shows the outline | summary of the other information processing apparatus using invention.

Explanation of symbols

  100: Information processing apparatus

Claims (7)

FPGA (field programmable gate array),
A control device capable of rewriting attribute information defining the internal configuration of the FPGA and a storage device;
The controller is
An attribute information reading step of reading the attribute information from the FPGA;
A comparison step for comparing the read attribute information with an expected value;
An information processing apparatus comprising: a logic for executing a redefinition step for redefining an internal configuration of the FPGA using the expected value based on a result of the comparison step.   The information processing apparatus according to claim 1, wherein the reading step and the comparison step are performed at predetermined time intervals. The storage device includes a nonvolatile semiconductor memory or a hard disk device,
The information processing apparatus according to claim 1, wherein the expected value is stored in the nonvolatile semiconductor memory or the hard disk device.   4. The information processing according to claim 1, wherein a diagnostic program for confirming the operation of the FPGA is executed after the redefinition step, and the result is stored in the storage device. apparatus. Detecting the case where the comparison results in the comparison step are inconsistent, and counting means for counting the cumulative number of occurrences;
Determining means for determining whether the generated cumulative number exceeds a predetermined MAX value;
The information processing apparatus according to claim 1, further comprising: a notification processing unit that performs a predetermined notification process based on the determination result. An operation method of an information processing apparatus including an FPGA,
An attribute information reading step of reading attribute information defining the internal configuration from the FPGA;
A comparison step for comparing the read attribute information with an expected value;
And a redefinition step of redefining the internal configuration of the FPGA using the expected value based on the result of the comparison step. A program that is read and executed by a computer having an FPGA,
An attribute information reading step of reading attribute information defining the internal configuration from the FPGA;
A comparison step for comparing the read attribute information with an expected value;
And a redefinition step of redefining the internal configuration of the FPGA using the expected value based on the result of the comparison step.

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