CN111176884A - SEC (Security and Security) verification method and device for FPGA (field programmable Gate array) configuration memory - Google Patents

SEC (Security and Security) verification method and device for FPGA (field programmable Gate array) configuration memory Download PDF

Info

Publication number
CN111176884A
CN111176884A CN201911395482.4A CN201911395482A CN111176884A CN 111176884 A CN111176884 A CN 111176884A CN 201911395482 A CN201911395482 A CN 201911395482A CN 111176884 A CN111176884 A CN 111176884A
Authority
CN
China
Prior art keywords
data
configuration memory
fpga configuration
error
sec
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911395482.4A
Other languages
Chinese (zh)
Other versions
CN111176884B (en
Inventor
张亭亭
蔡旭伟
王兴兴
贾红
陈维新
韦嶔
程显志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Original Assignee
XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc filed Critical XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
Priority to CN201911395482.4A priority Critical patent/CN111176884B/en
Publication of CN111176884A publication Critical patent/CN111176884A/en
Application granted granted Critical
Publication of CN111176884B publication Critical patent/CN111176884B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses an SEC (Security and Security) verification method for an FPGA (field programmable Gate array) configuration memory, which comprises the following steps of: acquiring and storing a reference ECC check code; performing ECC (error correction code) check on the data in the FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data; and performing CRC check on the data in the FPGA configuration memory and performing data reset on all frames in the configuration memory when an error occurs. The SEC checking device comprises a check code storage module, an SEC checking module, a correction module, a configuration module and an off-chip memory and is used for executing the SEC checking method. The method and the device of the invention use ECC check and CRC check to detect and correct errors of data in the FPGA configuration memory when the FPGA chip works normally, and the two check modes work together, thereby improving the working accuracy and stability of the FPGA chip.

Description

SEC (Security and Security) verification method and device for FPGA (field programmable Gate array) configuration memory
Technical Field
The invention belongs to the technical field of FPGA configuration memories, and particularly relates to an SEC (Security and Security) verification method and device for an FPGA configuration memory.
Background
The FPGA (Field Programmable Gate Array) configuration memory is distributed throughout the whole FPGA chip, and is the storage unit with the largest number in the chip, and the data therein controls the configurable logic resources such as wiring resources and lookup tables, and determines the behavior of the user circuit. In the process of configuring the FPGA chip, the FPGA chip is divided into a plurality of addresses according to the distribution positions of each storage unit of the configuration memory, and each address stores data with fixed length. After the FPGA configuration enters a normal operating state, due to various factors, data in the internal configuration memory of the chip may be in error, which results in that the chip cannot operate normally. In order to ensure the working correctness and stability of the FPGA chip, in the normal working process of the FPGA chip, it is necessary to monitor, detect and correct errors occurring in the configuration memory.
The prior art discloses a soft error detection method for checking and correcting errors in an FPGA configuration memory, which is implemented by reading all data in the FPGA configuration memory, performing Cyclic Redundancy Check (CRC), restarting configuration if an error is found, and writing all configuration data stored in an off-chip memory into the FPGA configuration memory again, but the restarting configuration can be performed only in an MSPI (Master Serial peripheral interface) configuration mode, errors in configuration data cannot be corrected in other configuration modes, and the error detection rate and the error modification rate are limited by the Check method itself.
Another existing soft Error buffering method is used for checking and Correcting errors in an FPGA configuration memory, and the implementation method is to perform ECC (Error correction Code) check and CRC check on data in the FPGA configuration memory, and during the data correction process, rewriting a frame of corrected configuration data into the FPGA configuration memory is implemented by controlling a start configuration module through a plurality of modules and executing a command for writing configuration data, and the operation is complex when bit stream data that can be identified by the configuration module is to be generated.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an SEC verification method and apparatus for an FPGA configuration memory. The technical problem to be solved by the invention is realized by the following technical scheme:
one aspect of the present invention provides an SEC checking method for an FPGA configuration memory, including:
acquiring and storing a reference ECC check code;
performing ECC (error correction code) check on the data in the FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data;
and performing CRC check on the data in the FPGA configuration memory and performing data reset on all frames in the configuration memory when an error occurs.
In one embodiment of the present invention, acquiring and storing the reference ECC check code includes:
when data are read from the FPGA configuration memory for the first time after SEC verification is started, sequentially reading each frame of data in all addresses from the 0 address of the FPGA configuration memory;
and calculating the reference ECC check code of each frame of data according to an ECC check code calculation method and storing the reference ECC check code of each frame of data to a corresponding position of a check code memory.
In an embodiment of the present invention, performing ECC check on data in the FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data includes:
calculating an actual ECC check code of current frame data in the FPGA configuration memory;
and judging whether the actual ECC check code is consistent with the reference ECC check code corresponding to the current frame data, if so, continuously acquiring the ECC check code of the next frame data and carrying out ECC check on the next frame data, and if not, modifying the current frame error data or reconfiguring all data in the FPGA configuration memory.
In an embodiment of the present invention, modifying the current frame error data or reconfiguring all data in the FPGA configuration memory includes:
judging whether to correct the error data of the current frame according to parameters set by a user, if not, sending an error indication signal to a status register, and performing ECC (error correction code) check from the 0 address of the FPGA configuration memory again; if the current frame error data is set to be corrected in advance, judging whether the current frame error data is a correctable error or not, if the current frame error data is the correctable error, modifying the current frame error data, and rewriting the modified data into the corresponding position of the FPGA configuration memory; and if the error is uncorrectable, sending a check error report and reconfiguring all data in the FPGA configuration memory according to user settings.
In an embodiment of the present invention, if the error is correctable, modifying the error data of the current frame, and rewriting the modified data into the corresponding location of the FPGA configuration memory, includes:
determining the address of the error data of the current frame in the FPGA configuration memory and the error bit of the current frame;
reading the current frame error data from the corresponding address of the FPGA configuration memory by controlling an address shift register and a data shift register according to the address of the current frame error data, and negating the corresponding bit of the current frame error data according to the error bit;
and rewriting the corrected data into the corresponding address of the FPGA configuration memory by controlling the address shift register and the data shift register.
In an embodiment of the present invention, if the error is an uncorrectable error, sending a check error report and reconfiguring all data in the FPGA configuration memory according to user settings includes:
judging whether the current user setting can be restarted for configuration, if not, sending an error indication signal to a state register, and starting ECC (error correction code) verification from the 0 address of the FPGA configuration memory again; and if so, resetting all data in the FPGA configuration memory, and starting to perform ECC (error correction code) verification again from the 0 address of the FPGA configuration memory after data resetting.
In an embodiment of the present invention, performing CRC check on data in the FPGA configuration memory and performing data reset according to user settings when error data occurs includes:
after ECC (error correction code) checking is completed on the last frame of data in the FPGA configuration memory, performing CRC (cyclic redundancy check) checking on the data in the FPGA configuration memory, and if the CRC checking is successful, performing ECC checking from the 0 address of the FPGA configuration memory again; if the CRC fails, judging whether the configuration can be restarted or not according to user setting, if so, resetting all data in the FPGA configuration memory, and starting to perform ECC check again from the address 0 of the FPGA configuration memory after the data is reset, otherwise, sending an error indication signal to a status register, and starting to perform ECC check again from the address 0 of the FPGA configuration memory.
The invention provides an SEC verification device for an FPGA configuration memory, which is used for executing the SEC verification method in any one of the above embodiments, and the SEC verification device includes a verification code storage module, an SEC verification module, a correction module, a configuration module, and an off-chip memory, where the verification code storage module is used to acquire and store a reference ECC verification code;
the SEC check module is connected with the check code storage module and is used for performing CRC check and performing ECC check on data in the FPGA configuration memory according to the reference ECC check code;
the correcting module is connected with the SEC verifying module and the FPGA configuration memory and is used for modifying correctable errors in the FPGA configuration memory according to control signals of the SEC verifying module;
the configuration module is connected with the SEC check module and the off-chip memory, the off-chip memory is connected with the FPGA configuration memory, and the configuration module is used for reconfiguring the FPGA configuration memory when ECC correction errors cannot be carried out in the FPGA configuration memory by using the FPGA configuration data in the off-chip memory according to the control signal of the SEC check module, and resetting all data in the FPGA configuration memory.
In an embodiment of the present invention, the correction module includes an address shift register and a data shift register, where the address shift register and the data shift register are configured to, when it is detected that current frame data is a correctable error, read and modify the current frame data from the FPGA configuration memory, and rewrite the modified data into a corresponding address of the FPGA configuration memory.
The SEC checking device for the FPGA configuration memory further comprises a status register which is connected with the SEC checking module and used for receiving and storing an error indication signal from the SEC checking module when the detected signal is an uncorrectable error or an error which is set by a user not to be corrected.
Compared with the prior art, the invention has the beneficial effects that:
1. the SEC checking method for the FPGA configuration memory of the invention uses ECC checking and CRC checking to detect and correct errors of data in the FPGA configuration memory when the FPGA chip works normally, wherein the ECC checking can correct 1 bit error in each frame of configuration data without restarting the configuration process, does not influence the normal work of the FPGA chip and can be carried out repeatedly; any error in the configuration data can be detected by CRC check, the method is not influenced by the number of error bits, all data in the configuration memory can be refreshed, and the working accuracy and stability of the FPGA chip are improved through the combined action of the two checks.
2. The SEC verification control circuit of the invention is reserved with a user intervention interface, and a user can autonomously determine the enabling and closing of verification and the verification times according to specific requirements.
3. According to the SEC verification method and device, after one frame of data is corrected, the original address shift register and data shift register in the FPGA chip are controlled through simple control signals, and the corrected data are rewritten into the corresponding position of the FPGA configuration memory, so that the circuit and the control flow are simplified.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a flowchart of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention;
fig. 2 is another flowchart of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention;
fig. 3 is a block diagram of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention;
fig. 4 is a structural diagram of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention.
Detailed Description
In order to further illustrate the technical means and effects of the present invention adopted to achieve the predetermined invention purpose, the SEC verification method and apparatus for FPGA configuration memory according to the present invention are described in detail below with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Example one
Referring to fig. 1, fig. 1 is a flowchart of an SEC verification method for an FPGA configuration memory according to an embodiment of the present invention. And after the configuration of the FPGA chip is completed, starting an SEC soft error check function through a control signal. The SEC verification method of the present embodiment includes:
s1: acquiring and storing a reference ECC check code;
s2: performing ECC (error correction code) check on the data in the FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data;
ECC is a memory error correction method, which can locate and correct a 1-bit error in a frame of data; when there is a 2-bit error in one frame data, the error can be detected. ECC is realized by adding check bits on original data bits, if the data bits are 8 bits, 5 bits are needed to be added for ECC error check and correction, and when the data bits are doubled, ECC is added with only one check bit, that is, when the data bits are 16 bits, the ECC bits are 6 bits, when the data bits are 32 bits, the ECC bits are 7 bits, when the data bits are 64 bits, the ECC bits are 8 bits, and so on, when the data bits are doubled, the ECC bits are added with only one bit.
S3: and performing CRC check on the data in the FPGA configuration memory and performing data reset on all frames in the configuration memory when an error occurs.
CRC is a hash function that generates a short fixed bit check code from data, and is mainly used to detect or check errors that may occur after data transmission or storage, and is not limited by the number of erroneous bits.
Further, step S1 includes:
when data are read from the FPGA configuration memory for the first time after SEC verification is started, sequentially reading each frame of data in all addresses from the 0 address of the FPGA configuration memory; and calculating the reference ECC check code of each frame of data according to an ECC check code calculation method and storing the reference ECC check code of each frame of data to a corresponding position of a check code memory.
Specifically, in this embodiment, after the configuration of the FPGA configuration memory is completed, the SEC checking device is started, and the SEC checking module sequentially reads data in all addresses from the 0 address of the FPGA configuration memory. And when one frame of data is read, calculating a reference ECC check code of the frame of data according to an ECC check code calculation method, and if the data is read from the FPGA configuration memory for the first time, sequentially storing the reference ECC check code of each frame of data in a corresponding address of the ECC check code memory. Preferably, the ECC check code memory is a sram _ sp _ hde memory.
Further, step S2 includes:
s21: calculating an actual ECC check code of current frame data in the FPGA configuration memory;
specifically, after the first data reading is completed and the reference ECC check code is generated, all data in the FPGA configuration memory are sequentially read in real time starting from the 0 address of the FPGA configuration memory again. And when one frame of data is read, calculating the ECC check code of the current frame of data according to an ECC check code calculation method to serve as the actual ECC check code of the current frame of data.
S22: and judging whether the actual ECC check code is consistent with the corresponding reference ECC check code, if so, continuously acquiring the ECC check code of the next frame of data and carrying out ECC check on the next frame of data, and if not, modifying the error data of the current frame or reconfiguring all data in the FPGA configuration memory.
Further, the modifying the current frame error data or reconfiguring all data in the FPGA configuration memory in step S22 includes:
judging whether to correct the error data of the current frame according to parameters preset by a user, if not, sending an error indication signal to a status register, and starting ECC (error correction code) verification from the 0 address of the FPGA configuration memory again; if the current frame error data is set to be corrected in advance, judging whether the current frame error data is a correctable error or not, if the current frame error data is the correctable error, modifying the current frame error data, and rewriting the modified data into the corresponding position of the FPGA configuration memory; and if the error is uncorrectable, sending a check error report and reconfiguring all data in the FPGA configuration memory according to user settings.
Specifically, the device for executing the SEC checking method of this embodiment may set a user intervention interface, and the user may autonomously determine the enabling, closing and checking times of the checking according to specific requirements, for example, the user may set whether to modify or send an alarm for a detected error according to requirements, or the user may set to perform a cyclic check or perform only one check on data in the FPGA configuration memory according to requirements.
Further, if the error is correctable, modifying the error data of the current frame, and rewriting the modified data into the corresponding position of the FPGA configuration memory, including:
determining the address of the error data of the current frame in the FPGA configuration memory and the error bit of the current frame; reading the current frame error data from the corresponding address of the FPGA configuration memory by controlling an address shift register and a data shift register according to the address of the current frame error data, and negating the corresponding bit of the current frame error data according to the error bit; and rewriting the corrected data into the corresponding address of the FPGA configuration memory by controlling the address shift register and the data shift register.
Further, if the error is uncorrectable, sending a check error report and reconfiguring all data in the FPGA configuration memory according to user settings, including:
judging whether the current user setting can be restarted for configuration, if not, sending an error indication signal to a state register, and starting ECC (error correction code) verification from the 0 address of the FPGA configuration memory again; and if so, resetting data of all the data in the FPGA configuration memory, canceling an SEC error report, and starting to perform ECC (error correction code) verification again from the 0 address of the FPGA configuration memory after data resetting.
Further, performing CRC check on data in the FPGA configuration memory and performing data reset according to user settings when error data occurs, including:
after ECC (error correction code) checking is completed on the last frame of data in the FPGA configuration memory, performing CRC (cyclic redundancy check) checking on the data in the FPGA configuration memory, and if the CRC checking is successful, performing ECC checking from the 0 address of the FPGA configuration memory again; if the CRC fails, judging whether the configuration can be restarted or not according to user setting, if so, resetting all data in the FPGA configuration memory, and starting to perform ECC check again from the address 0 of the FPGA configuration memory after the data is reset, otherwise, sending an error indication signal to a status register, and starting to perform ECC check again from the address 0 of the FPGA configuration memory.
The SEC checking method for the FPGA configuration memory of this embodiment uses ECC checking and CRC checking to detect and correct errors of data in the FPGA configuration memory when the FPGA chip normally works, wherein the ECC checking can correct 1-bit errors in each frame of configuration data, does not need to restart the configuration process, does not affect the normal work of the FPGA chip, and can be repeatedly performed; any error in the configuration data can be detected by CRC check, the method is not influenced by the number of error bits, all data in the configuration memory can be refreshed, and the working accuracy and stability of the FPGA chip are improved through the combined action of the two checks.
Example two
Referring to fig. 2, fig. 2 is another flowchart of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention.
The SEC verification method of the present embodiment includes:
after the configuration of the FPGA configuration memory is completed, starting an SEC checking device, sequentially reading data in all addresses by an SEC checking module from the 0 address of the FPGA configuration memory, judging whether the data are read from the FPGA configuration memory for the first time, if so, sequentially calculating an ECC checking code of each frame of data as a reference ECC checking code, and storing the ECC checking code in a corresponding address of the ECC checking code memory, preferably, the ECC checking code memory is an sram _ sp _ hde memory, if not, reading the data from the FPGA configuration memory for the first time, indicating that the reference ECC checking code is stored in the previous step, and at this time, calculating an actual checking code of a currently read frame of data and reading the reference checking code of the frame of data from the corresponding address of the memory for comparison operation.
Then, whether the actual ECC check code is consistent with the reference ECC check code corresponding to the frame data is judged, if so, it is indicated that the frame data has no error, and then, whether the frame data is the last frame data of the FPGA configuration memory is judged, if not, the ECC check code of the next frame data is continuously obtained and the ECC check is performed on the next frame data, and if the frame data is the last frame data, the CRC check step is entered, and a specific process of the CRC check step is described in detail below.
If the actual ECC check code is not consistent with the reference ECC check code corresponding to the frame data, judging whether to correct the error data of the current frame according to parameters preset by a user, if not, pulling up a corresponding sed error indication signal in a status register, and starting ECC check from the 0 address of the FPGA configuration memory again; if the current frame error data is preset to be corrected, judging whether the current frame error data is a correctable error or not, if the current frame error data is the correctable error, determining the address of the current frame error data in the FPGA configuration memory and the error bit of the current frame, reading the current frame error data from the corresponding address of the FPGA configuration memory through controlling an address shift register and a data shift register according to the address of the current frame error data, inverting the corresponding bit of the current frame error data according to the error bit, and rewriting the corrected data into the corresponding address of the FPGA configuration memory through controlling the address shift register and the data shift register; if the error is uncorrectable, judging whether the current user setting can be restarted for configuration, if not, sending an error indication signal to a state register, and performing ECC (error correction code) check from the 0 address of the FPGA configuration memory again; and if so, resetting data of all the data in the FPGA configuration memory, canceling an SEC error report, and starting to perform ECC (error correction code) verification again from the 0 address of the FPGA configuration memory after data resetting.
It should be noted that, when data in the FPGA configuration memory is read each time, it is determined that the frame data is the last frame data of the FPGA configuration memory, if yes, the CRC checking step is performed, and if not, the ECC checking code of the next frame data is continuously obtained and the ECC checking is performed on the next frame data.
After ECC (error correction code) checking is completed on the last frame of data in the FPGA configuration memory, performing CRC (cyclic redundancy check) checking on the data in the FPGA configuration memory, and if the CRC checking is successful, performing ECC checking from the 0 address of the FPGA configuration memory again; if the CRC fails, judging whether the configuration can be restarted or not according to user setting, if so, resetting all data in the FPGA configuration memory, and starting to perform ECC check again from the address 0 of the FPGA configuration memory after the data is reset, otherwise, sending an error indication signal to a status register, and starting to perform ECC check again from the address 0 of the FPGA configuration memory.
Further, after performing the CRC check, the method further includes:
and detecting whether continuous checking is set, if so, starting ECC checking from the 0 address of the FPGA configuration memory again, and if not, finishing the checking after one-time ECC checking and CRC checking on the FPGA configuration memory. Further, the number of verification cycles may also be set to a specific number.
EXAMPLE III
On the basis of the foregoing embodiment, the present embodiment provides an SEC verification apparatus for an FPGA configuration memory, which is used to execute the SEC verification method in the first embodiment.
Referring to fig. 3, fig. 3 is a block diagram of an SEC checking method for an FPGA configuration memory according to an embodiment of the present invention. The SEC checking device of this embodiment includes a check code storage module 101, an SEC checking module 102, a correction module 103, a configuration module 104, and an off-chip memory 105, where the check code storage module 101 is configured to obtain and store a reference ECC check code; the SEC check module 102 is connected to the check code storage module 101, and configured to perform CRC check and ECC check on data in the FPGA configuration memory (106) according to the reference ECC check code; the correction module 103 is connected to the SEC verification module 102 and the FPGA configuration memory 106, and configured to modify a correctable error in the FPGA configuration memory 106 according to a control signal of the SEC verification module 102; the configuration module 104 is connected to the SEC verification module 102 and the off-chip memory 105, the off-chip memory 105 is connected to the FPGA configuration memory 106, and the configuration module 104 is configured to reconfigure, according to a control signal of the SEC verification module 102, the FPGA configuration data in the off-chip memory 105 when an ECC error cannot be corrected in the FPGA configuration memory 106, and reset all data in the FPGA configuration memory.
In the actual operation process, after the configuration of the FPGA configuration memory 106 is completed, the SEC check is started, the SEC check module 102 sequentially reads data in all addresses from the address 0 of the FPGA configuration memory 106, and if the data is read from the FPGA configuration memory 102 for the first time, the ECC check code of each frame of data is sequentially calculated as the reference ECC check code and stored in the corresponding address of the ECC check code memory 101. The reference ECC check code is a standard for determining whether data of the FPGA configuration memory 102 is correct during subsequent ECC check. In this embodiment, the SEC check module 102 includes an ECC check unit and a CRC check unit.
Subsequently, after the first data reading is completed and the reference ECC check code is generated, the process of checking the data of the FPGA configuration memory 106 may be started. Specifically, in the normal operation of the FPGA chip, all data in the FPGA configuration memory 106 are sequentially read out in real time from the 0 address of the FPGA configuration memory 106 again. When reading a frame of data, the ECC check unit calculates the ECC check code of the current frame of data according to an ECC check code calculation method, and the ECC check code is used as the actual ECC check code of the current frame of data; and the ECC check unit compares the actual ECC check code with the reference ECC check code, and then controls the correction module 103 to modify the current frame error data or controls the configuration module 104 to reconfigure all data in the FPGA configuration memory 106 according to the comparison result.
Secondly, after the last frame of data in the FPGA configuration memory 106 completes the ECC check, performing CRC check on the data in the FPGA configuration memory 106 by using a CRC check unit, and if the CRC check is successful, performing the ECC check again from the address 0 of the FPGA configuration memory 106; if the CRC check fails, determining whether the configuration can be restarted according to user settings, and if the configuration can be restarted, sending a control signal to the configuration module 104 by the CRC check unit, controlling the configuration module 104 to perform data reset on all data in the FPGA configuration memory 106 by using the configuration data stored in the off-chip memory 105, and performing ECC check again from the address 0 of the FPGA configuration memory 106 after the data reset; and if the configuration cannot be restarted, sending an error indication signal to a status register, and performing ECC (error correction code) check from the 0 address of the FPGA configuration memory again.
The SEC checking device further includes a status register connected to the SEC checking module, and configured to receive and store an error indication signal from the SEC checking module when the detected signal is an uncorrectable error, an error preset to be uncorrected, or an error that is not resettable. The specific comparison and determination processes have been described in detail in the first and second embodiments, please refer to the first and second embodiments, and will not be described herein again.
Further, please refer to fig. 4, where fig. 4 is a structural diagram of an SEC verification method for an FPGA configuration memory according to an embodiment of the present invention. The correction module 103 includes an address shift register 1031 and a data shift register 1032, where the address shift register 1031 and the data shift register 1032 are configured to, when it is detected that the current frame data is a correctable error, read the current frame data from the FPGA configuration memory 106 and modify the current frame data, and rewrite the modified data into a corresponding address of the FPGA configuration memory 106. Preferably, the ECC check code memory 101 is a sram _ sp _ hde memory.
In addition, it should be noted that a user intervention interface is reserved in the SEC verification control circuit of this embodiment, and a user may autonomously determine the number of times of enabling, closing, and verifying according to a specific requirement, for example, the user may set whether to modify or send an alarm for a detected error according to a requirement, or the user may set to perform a cyclic verification or perform only one verification on data in the FPGA configuration memory according to the requirement.
In summary, in the verification method in the prior art, the corrected frame of configuration data is rewritten into the FPGA configuration memory by controlling the start of the configuration module through the plurality of modules and executing the command for writing the configuration data, and the operation is complicated to generate the bit stream data that can be identified by the configuration module. The SEC verification method and apparatus of this embodiment, after completing the correction of one frame of data, controls the original address shift register and data shift register in the FPGA chip through a simple control signal, and rewrites the error-corrected data into the corresponding position of the FPGA configuration memory, thereby simplifying the circuit and the control flow.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. An SEC verification method for FPGA configuration memory, the method comprising:
acquiring and storing a reference ECC check code;
performing ECC (error correction code) check on the data in the FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data;
and performing CRC check on the data in the FPGA configuration memory and performing data reset on all frames in the configuration memory when an error occurs.
2. The SEC checking method for FPGA configuration memory according to claim 1, wherein obtaining and storing the reference ECC check code comprises:
when data are read from the FPGA configuration memory for the first time after SEC verification is started, sequentially reading each frame of data in all addresses from the 0 address of the FPGA configuration memory;
and calculating the reference ECC check code of each frame of data according to an ECC check code calculation method and storing the reference ECC check code of each frame of data to a corresponding position of a check code memory.
3. The SEC checking method for FPGA configuration memory according to claim 1, wherein performing ECC checking on data in said FPGA configuration memory frame by frame according to said reference ECC check code and modifying error data comprises:
calculating an actual ECC check code of current frame data in the FPGA configuration memory;
and judging whether the actual ECC check code is consistent with the reference ECC check code corresponding to the current frame data, if so, continuously acquiring the ECC check code of the next frame data and carrying out ECC check on the next frame data, and if not, modifying the current frame error data or reconfiguring all data in the FPGA configuration memory.
4. The SEC verification method for FPGA configuration memory of claim 3, wherein modifying current frame error data or reconfiguring all data in said FPGA configuration memory comprises:
judging whether to correct the error data of the current frame according to parameters set by a user, if not, sending an error indication signal to a status register, and performing ECC (error correction code) check from the 0 address of the FPGA configuration memory again; if the current frame error data is set to be corrected in advance, judging whether the current frame error data is a correctable error or not, if the current frame error data is the correctable error, modifying the current frame error data, and rewriting the modified data into the corresponding position of the FPGA configuration memory; and if the error is uncorrectable, sending a check error report and reconfiguring all data in the FPGA configuration memory according to user settings.
5. The SEC verification method for FPGA configuration memory according to claim 4, wherein if it is a correctable error, modifying said current frame error data, and rewriting the modified data into the corresponding location of said FPGA configuration memory comprises:
determining the address of the error data of the current frame in the FPGA configuration memory and the error bit of the current frame;
reading the current frame error data from the corresponding address of the FPGA configuration memory by controlling an address shift register and a data shift register according to the address of the current frame error data, and negating the corresponding bit of the current frame error data according to the error bit;
and rewriting the corrected data into the corresponding address of the FPGA configuration memory by controlling the address shift register and the data shift register.
6. The SEC verification method for FPGA configuration memory of claim 4, wherein if it is an uncorrectable error, sending a check error report and reconfiguring all data in said FPGA configuration memory according to user settings, comprises:
judging whether the current user setting can be restarted for configuration, if not, sending an error indication signal to a state register, and starting ECC (error correction code) verification from the 0 address of the FPGA configuration memory again; and if so, resetting all data in the FPGA configuration memory, and starting to perform ECC (error correction code) verification again from the 0 address of the FPGA configuration memory after data resetting.
7. The SEC checking method for FPGA configuration memory according to claim 1, wherein performing CRC check on data in said FPGA configuration memory and performing data reset according to user setting when error data occurs comprises:
after ECC (error correction code) checking is completed on the last frame of data in the FPGA configuration memory, performing CRC (cyclic redundancy check) checking on the data in the FPGA configuration memory, and if the CRC checking is successful, performing ECC checking from the 0 address of the FPGA configuration memory again; if the CRC fails, judging whether the configuration can be restarted or not according to user setting, if so, resetting all data in the FPGA configuration memory, and starting to perform ECC check again from the address 0 of the FPGA configuration memory after the data is reset, otherwise, sending an error indication signal to a status register, and starting to perform ECC check again from the address 0 of the FPGA configuration memory.
8. An SEC checking apparatus for FPGA configuration storage, for performing the SEC checking method of any one of claims 1 to 7, comprising a check code storage module (101), an SEC checking module (102), a correction module (103), a configuration module (104) and an off-chip memory (105), wherein,
the check code storage module (101) is used for acquiring and storing a reference ECC check code;
the SEC check module (102) is connected with the check code storage module (101) and is used for performing CRC check and ECC check on data in the FPGA configuration memory (106) according to the reference ECC check code;
the correction module (103) is connected with the SEC check module (102) and the FPGA configuration memory (106) and is used for modifying correctable errors in the FPGA configuration memory (106) according to control signals of the SEC check module (102);
the configuration module (104) is connected to the SEC check module (102) and the off-chip memory (105), the off-chip memory (105) is connected to the FPGA configuration memory (106), and the configuration module (104) is configured to reconfigure the FPGA configuration memory (106) when an ECC error cannot be corrected by using the FPGA configuration data in the off-chip memory (105) according to a control signal of the SEC check module (102), and reset all data in the FPGA configuration memory.
9. An SEC checking device for FPGA configuration memory according to claim 8, wherein said correction module (103) comprises an address shift register (1031) and a data shift register (1032), wherein said address shift register (1031) and said data shift register (1032) are configured to read and modify the current frame data from said FPGA configuration memory (106) and rewrite the modified data into the corresponding address of said FPGA configuration memory (106) when detecting that the current frame data is a correctable error.
10. An SEC checking apparatus for FPGA configuration memory according to claim 8 or 9, further comprising a status register connected to said SEC check module (102) for receiving and storing an error indication signal from said SEC check module (102) when a detected signal is an uncorrectable error or an error which a user sets not to correct.
CN201911395482.4A 2019-12-30 2019-12-30 SEC (SEC) verification method and device for FPGA (field programmable Gate array) configuration memory Active CN111176884B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911395482.4A CN111176884B (en) 2019-12-30 2019-12-30 SEC (SEC) verification method and device for FPGA (field programmable Gate array) configuration memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911395482.4A CN111176884B (en) 2019-12-30 2019-12-30 SEC (SEC) verification method and device for FPGA (field programmable Gate array) configuration memory

Publications (2)

Publication Number Publication Date
CN111176884A true CN111176884A (en) 2020-05-19
CN111176884B CN111176884B (en) 2023-05-16

Family

ID=70654253

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911395482.4A Active CN111176884B (en) 2019-12-30 2019-12-30 SEC (SEC) verification method and device for FPGA (field programmable Gate array) configuration memory

Country Status (1)

Country Link
CN (1) CN111176884B (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112131828A (en) * 2020-09-18 2020-12-25 山东云海国创云计算装备产业创新中心有限公司 Data processing method, device and equipment and readable storage medium
CN113157633A (en) * 2021-01-28 2021-07-23 厦门智多晶科技有限公司 Method and device for starting reconfiguration in SEC (Security and Security) verification and FPGA (field programmable Gate array)
CN113608919A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA for improving reliability of key configuration code stream by multiplexing buffer memory
CN113608918A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA with automatic error detection and correction function for programmable logic module
US11604692B2 (en) 2021-08-19 2023-03-14 Wuxi Esiontech Co., Ltd. Field programmable gate array (FPGA) with automatic error detection and correction function for programmable logic modules

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7203890B1 (en) * 2004-06-16 2007-04-10 Azul Systems, Inc. Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits
CN101178675A (en) * 2007-12-14 2008-05-14 华为技术有限公司 Method and device for verifying data
US7398449B1 (en) * 2004-06-16 2008-07-08 Azul Systems, Inc. Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7203890B1 (en) * 2004-06-16 2007-04-10 Azul Systems, Inc. Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits
US7398449B1 (en) * 2004-06-16 2008-07-08 Azul Systems, Inc. Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module
CN101178675A (en) * 2007-12-14 2008-05-14 华为技术有限公司 Method and device for verifying data

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
王轩;常亮;李杰;: "基于FPGA的NAND Flash ECC校验系统设计与实现" *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112131828A (en) * 2020-09-18 2020-12-25 山东云海国创云计算装备产业创新中心有限公司 Data processing method, device and equipment and readable storage medium
CN112131828B (en) * 2020-09-18 2022-06-17 山东云海国创云计算装备产业创新中心有限公司 Data processing method, device and equipment and readable storage medium
CN113157633A (en) * 2021-01-28 2021-07-23 厦门智多晶科技有限公司 Method and device for starting reconfiguration in SEC (Security and Security) verification and FPGA (field programmable Gate array)
CN113157633B (en) * 2021-01-28 2023-05-26 厦门智多晶科技有限公司 Method and device for starting reconfiguration in SEC (SEC-based encryption) verification and FPGA (field programmable gate array)
CN113608919A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA for improving reliability of key configuration code stream by multiplexing buffer memory
CN113608918A (en) * 2021-08-19 2021-11-05 无锡中微亿芯有限公司 FPGA with automatic error detection and correction function for programmable logic module
WO2023019742A1 (en) * 2021-08-19 2023-02-23 无锡中微亿芯有限公司 Fpga having automatic error checking and correcting function for programmable logic module
US11604692B2 (en) 2021-08-19 2023-03-14 Wuxi Esiontech Co., Ltd. Field programmable gate array (FPGA) with automatic error detection and correction function for programmable logic modules
CN113608918B (en) * 2021-08-19 2023-04-28 无锡中微亿芯有限公司 FPGA with automatic error checking and correcting function for programmable logic module
CN113608919B (en) * 2021-08-19 2024-02-02 无锡中微亿芯有限公司 FPGA for improving reliability of key configuration code stream through multiplexing buffer memory

Also Published As

Publication number Publication date
CN111176884B (en) 2023-05-16

Similar Documents

Publication Publication Date Title
CN111176884B (en) SEC (SEC) verification method and device for FPGA (field programmable Gate array) configuration memory
US7412575B2 (en) Data management technique for improving data reliability
US8572444B2 (en) Memory apparatus and testing method thereof
KR20160024966A (en) Circuits, apparatuses, and methods for correcting data errors
CN110442473B (en) Nonvolatile data storage method and device, electronic equipment and medium
JP2016167669A (en) Programmable logic circuit device and error detection method
TWI685850B (en) Memory management method and storage controller
JP6290303B2 (en) Circuit and method for testing error correction capability
JP2019096281A (en) Data storage device and associated operating method
TWI816418B (en) Semiconductor device and operation method
JP2009520289A (en) Method for detecting a power outage in a data storage device and method for restoring a data storage device
WO2017107160A1 (en) Bad block identification processing and error correction method and system for heterogeneous hybrid memory-based nvm
JP2009506446A (en) Data processing system and driving method thereof
JP2017059278A (en) Semiconductor memory and verification method of semiconductor memory
US11088711B2 (en) Memory apparatus and data accessing method thereof
TWI437572B (en) Accessing method and system for error control coding using in the memory device
US9519539B2 (en) Monitoring data error status in a memory
WO2016101614A1 (en) Method and apparatus for controlling black box, black box device and computer storage medium
WO2016003449A1 (en) Memory controller
JP2907114B2 (en) Method and apparatus for correcting 1-bit error in EEPROM
CN112151104B (en) Memory storage device and dynamic data restoration method thereof
CN110874281B (en) Memory management method and memory controller
CN110825557B (en) Storage method and storage system
CN116013397A (en) Solid state disk fault injection testing method, device, equipment and medium
JPH054266U (en) Memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant